Repository: Xilinx/device-tree-xlnx Branch: master Commit: ac65e0142e52 Files: 1805 Total size: 10.5 MB Directory structure: gitextract__dnvpkf3/ ├── .github/ │ └── pull_request_template.md ├── .gitignore ├── RM/ │ └── data/ │ ├── RM.mdd │ └── RM.tcl ├── ai_engine/ │ └── data/ │ ├── ai_engine.mdd │ └── ai_engine.tcl ├── ams/ │ └── data/ │ ├── ams.mdd │ └── ams.tcl ├── apmps/ │ └── data/ │ ├── apmps.mdd │ └── apmps.tcl ├── audio_embed/ │ └── data/ │ ├── audio_embed.mdd │ └── audio_embed.tcl ├── audio_formatter/ │ └── data/ │ ├── audio_formatter.mdd │ └── audio_formatter.tcl ├── audio_spdif/ │ └── data/ │ ├── audio_spdif.mdd │ └── audio_spdif.tcl ├── axi_can/ │ └── data/ │ ├── axi_can.mdd │ └── axi_can.tcl ├── axi_cdma/ │ └── data/ │ ├── axi_cdma.mdd │ └── axi_cdma.tcl ├── axi_clk_wiz/ │ └── data/ │ ├── axi_clk_wiz.mdd │ └── axi_clk_wiz.tcl ├── axi_dma/ │ └── data/ │ ├── axi_dma.mdd │ └── axi_dma.tcl ├── axi_emc/ │ └── data/ │ ├── axi_emc.mdd │ └── axi_emc.tcl ├── axi_ethernet/ │ └── data/ │ ├── axi_ethernet.mdd │ └── axi_ethernet.tcl ├── axi_gpio/ │ └── data/ │ ├── gpio.mdd │ └── gpio.tcl ├── axi_iic/ │ └── data/ │ ├── axi_iic.mdd │ └── axi_iic.tcl ├── axi_mcdma/ │ └── data/ │ ├── axi_mcdma.mdd │ └── axi_mcdma.tcl ├── axi_pcie/ │ └── data/ │ ├── axi_pcie.mdd │ └── axi_pcie.tcl ├── axi_perf_mon/ │ └── data/ │ ├── axi_perf_mon.mdd │ └── axi_perf_mon.tcl ├── axi_qspi/ │ └── data/ │ ├── axi_qspi.mdd │ └── axi_qspi.tcl ├── axi_sysace/ │ └── data/ │ ├── axi_sysace.mdd │ └── axi_sysace.tcl ├── axi_tft/ │ └── data/ │ ├── axi_tft.mdd │ └── axi_tft.tcl ├── axi_timebase_wdt/ │ └── data/ │ ├── axi_timebase_wdt.mdd │ └── axi_timebase_wdt.tcl ├── axi_traffic_gen/ │ └── data/ │ ├── axi_traffic_gen.mdd │ └── axi_traffic_gen.tcl ├── axi_usb2_device/ │ └── data/ │ ├── axi_usb2_device.mdd │ └── axi_usb2_device.tcl ├── axi_vcu/ │ └── data/ │ ├── axi_vcu.mdd │ └── axi_vcu.tcl ├── axi_vdma/ │ └── data/ │ ├── axi_vdma.mdd │ └── axi_vdma.tcl ├── axi_vdu/ │ └── data/ │ ├── axi_vdu.mdd │ └── axi_vdu.tcl ├── axi_xadc/ │ └── data/ │ ├── axi_xadc.mdd │ └── axi_xadc.tcl ├── axis_switch/ │ └── data/ │ ├── axis_switch.mdd │ └── axis_switch.tcl ├── canfdps/ │ └── data/ │ ├── canfdps.mdd │ └── canfdps.tcl ├── canps/ │ └── data/ │ ├── canps.mdd │ └── canps.tcl ├── cpu/ │ └── data/ │ ├── cpu.mdd │ └── cpu.tcl ├── cpu_cortexa53/ │ └── data/ │ ├── cpu_cortexa53.mdd │ └── cpu_cortexa53.tcl ├── cpu_cortexa72/ │ └── data/ │ ├── cpu_cortexa72.mdd │ └── cpu_cortexa72.tcl ├── cpu_cortexa78/ │ └── data/ │ ├── cpu_cortexa78.mdd │ └── cpu_cortexa78.tcl ├── cpu_cortexa9/ │ └── data/ │ ├── cpu_cortexa9.mdd │ └── cpu_cortexa9.tcl ├── dccps/ │ └── data/ │ ├── dccps.mdd │ └── dccps.tcl ├── ddrcps/ │ └── data/ │ ├── ddrcps.mdd │ └── ddrcps.tcl ├── ddrps/ │ └── data/ │ ├── ddrps.mdd │ └── ddrps.tcl ├── ddrpsv/ │ └── data/ │ ├── ddrpsv.mdd │ └── ddrpsv.tcl ├── debug_bridge/ │ └── data/ │ ├── debug_bridge.mdd │ └── debug_bridge.tcl ├── demosaic/ │ └── data/ │ ├── demosaic.mdd │ └── demosaic.tcl ├── devcfg/ │ └── data/ │ ├── devcfg.mdd │ └── devcfg.tcl ├── device_tree/ │ └── data/ │ ├── common_proc.tcl │ ├── device_tree.mld │ ├── device_tree.mss │ ├── device_tree.tcl │ └── kernel_dtsi/ │ ├── 2014.4/ │ │ └── zynq/ │ │ ├── skeleton.dtsi │ │ └── zynq-7000.dtsi │ ├── 2015.1/ │ │ └── zynq/ │ │ ├── skeleton.dtsi │ │ └── zynq-7000.dtsi │ ├── 2015.2/ │ │ └── zynq/ │ │ ├── skeleton.dtsi │ │ └── zynq-7000.dtsi │ ├── 2015.3/ │ │ └── zynq/ │ │ ├── skeleton.dtsi │ │ └── zynq-7000.dtsi │ ├── 2015.4/ │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2016.1/ │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2016.2/ │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2016.3/ │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2016.4/ │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2017.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu102.dtsi │ │ │ ├── zcu106.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2017.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu102.dtsi │ │ │ ├── zcu106.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2017.3/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2017.4/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── 2018.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1275-revb.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2018.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1275-revb.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2018.3/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1275-revb.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ └── zedboard.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2019.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1275-revb.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-g-reva.dtsi │ │ │ ├── zynqmp-a2197-m-reva.dtsi │ │ │ ├── zynqmp-a2197-p-reva.dtsi │ │ │ └── zynqmp-a2197-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ └── pinctrl/ │ │ │ └── pinctrl-zynqmp.h │ │ ├── versal/ │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2019.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ └── zynqmp-e-a2197-00-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ └── pinctrl/ │ │ │ └── pinctrl-zynqmp.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2020.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ └── zynqmp-p-a2197-00-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2020.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ └── zynqmp-p-a2197-00-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2021.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva-mlcc.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva01-mlcc.dtsi │ │ │ ├── zynqmp-sm-k26-reva01.dtsi │ │ │ ├── zynqmp-sm-k26-revb-mlcc.dtsi │ │ │ ├── zynqmp-sm-k26-revb.dtsi │ │ │ ├── zynqmp-sm-k26-revb01-mlcc.dtsi │ │ │ ├── zynqmp-sm-k26-revb01.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2021.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2022.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2022.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── versal-net/ │ │ │ └── versal-net-ipp-rev1.9.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2023.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vek280-revb.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ ├── xlnx-versal-net-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ ├── mscc-phy-vsc8531.h │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── versal-net/ │ │ │ ├── versal-net-clk-ccf.dtsi │ │ │ ├── versal-net-clk.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ └── versal-net.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2023.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vek280-revb.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ ├── xlnx-versal-net-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ ├── mscc-phy-vsc8531.h │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── versal-net/ │ │ │ ├── versal-net-clk-ccf.dtsi │ │ │ ├── versal-net-clk.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ └── versal-net.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2024.1/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emb-plus-ve2302-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vek280-revb.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ ├── xlnx-versal-net-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ ├── mscc-phy-vsc8531.h │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── versal-net/ │ │ │ ├── versal-net-clk-ccf.dtsi │ │ │ ├── versal-net-clk.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ └── versal-net.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── 2024.2/ │ │ ├── BOARD/ │ │ │ ├── ac701-full.dtsi │ │ │ ├── ac701-lite.dtsi │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── kc705-full.dtsi │ │ │ ├── kc705-lite.dtsi │ │ │ ├── kcu105-tmr.dtsi │ │ │ ├── kcu105.dtsi │ │ │ ├── sp701-rev1.0.dtsi │ │ │ ├── vcu118-rev2.0.dtsi │ │ │ ├── versal-a2197-sc-reva.dtsi │ │ │ ├── versal-emb-plus-ve2302-reva.dtsi │ │ │ ├── versal-emu-itr8-cn13940875.dtsi │ │ │ ├── versal-net-emu-rev1.9.dtsi │ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi │ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi │ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi │ │ │ ├── versal-spp-itr8-cn13940875.dtsi │ │ │ ├── versal-v350-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── versal-vc-p-a2197-00-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-rev1.1.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vck190-reva.dtsi │ │ │ ├── versal-vck5000-reva.dtsi │ │ │ ├── versal-vek280-reva.dtsi │ │ │ ├── versal-vek280-revb.dtsi │ │ │ ├── versal-vhk158-reva.dtsi │ │ │ ├── versal-virt.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-rev1.1.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi │ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi │ │ │ ├── versal-vmk180-reva.dtsi │ │ │ ├── versal-vp-x-a2785-00-reva.dtsi │ │ │ ├── versal-vpk120-reva.dtsi │ │ │ ├── versal-vpk120-revb.dtsi │ │ │ ├── versal-vpk180-reva.dtsi │ │ │ ├── versal-x-ebm-01-reva.dtsi │ │ │ ├── versal-x-ebm-02-reva.dtsi │ │ │ ├── versal-x-ebm-03-reva.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc702.dtsi │ │ │ ├── zc706.dtsi │ │ │ ├── zcu100-reva.dtsi │ │ │ ├── zcu100-revb.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu104-revc.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ ├── zcu111-reva.dtsi │ │ │ ├── zcu1275-reva.dtsi │ │ │ ├── zcu1275-revb.dtsi │ │ │ ├── zcu1285-reva.dtsi │ │ │ ├── zcu208-reva.dtsi │ │ │ ├── zcu216-reva.dtsi │ │ │ ├── zcu670-reva.dtsi │ │ │ ├── zcu670-revb.dtsi │ │ │ ├── zedboard.dtsi │ │ │ ├── zynqmp-a2197-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-reva.dtsi │ │ │ ├── zynqmp-e-a2197-00-revb.dtsi │ │ │ ├── zynqmp-g-a2197-00-reva.dtsi │ │ │ ├── zynqmp-m-a2197-01-reva.dtsi │ │ │ ├── zynqmp-m-a2197-02-reva.dtsi │ │ │ ├── zynqmp-m-a2197-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi │ │ │ ├── zynqmp-p-a2197-00-reva.dtsi │ │ │ ├── zynqmp-sc-revb.dtsi │ │ │ ├── zynqmp-sc-revc.dtsi │ │ │ ├── zynqmp-sc-vek280-reva.dtsi │ │ │ ├── zynqmp-sc-vek280-revb.dtsi │ │ │ ├── zynqmp-sm-k24-reva.dtsi │ │ │ ├── zynqmp-sm-k26-reva.dtsi │ │ │ ├── zynqmp-smk-k24-reva.dtsi │ │ │ ├── zynqmp-smk-k26-reva.dtsi │ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi │ │ │ └── zynqmp-vpk120-reva.dtsi │ │ ├── include/ │ │ │ └── dt-bindings/ │ │ │ ├── clock/ │ │ │ │ ├── xlnx-versal-clk.h │ │ │ │ ├── xlnx-versal-net-clk.h │ │ │ │ └── xlnx-zynqmp-clk.h │ │ │ ├── dma/ │ │ │ │ └── xlnx-zynqmp-dpdma.h │ │ │ ├── gpio/ │ │ │ │ └── gpio.h │ │ │ ├── input/ │ │ │ │ └── input.h │ │ │ ├── interrupt-controller/ │ │ │ │ └── irq.h │ │ │ ├── net/ │ │ │ │ ├── mscc-phy-vsc8531.h │ │ │ │ └── ti-dp83867.h │ │ │ ├── phy/ │ │ │ │ └── phy.h │ │ │ ├── pinctrl/ │ │ │ │ └── pinctrl-zynqmp.h │ │ │ ├── power/ │ │ │ │ ├── xlnx-versal-net-power.h │ │ │ │ ├── xlnx-versal-power.h │ │ │ │ ├── xlnx-versal-regnode.h │ │ │ │ └── xlnx-zynqmp-power.h │ │ │ └── reset/ │ │ │ ├── xlnx-versal-net-resets.h │ │ │ ├── xlnx-versal-resets.h │ │ │ └── xlnx-zynqmp-resets.h │ │ ├── versal/ │ │ │ ├── versal-clk.dtsi │ │ │ ├── versal-spp-pm.dtsi │ │ │ └── versal.dtsi │ │ ├── versal-net/ │ │ │ ├── versal-net-clk-ccf.dtsi │ │ │ ├── versal-net-clk.dtsi │ │ │ ├── versal-net-ipp-rev1.9.dtsi │ │ │ └── versal-net.dtsi │ │ ├── zynq/ │ │ │ ├── skeleton.dtsi │ │ │ └── zynq-7000.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk-ccf.dtsi │ │ └── zynqmp.dtsi │ ├── v4.17/ │ │ ├── board/ │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcep108.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v4.18/ │ │ ├── board/ │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v4.19/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v4.20/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v5.0/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v5.1/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v5.2/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ ├── v5.3/ │ │ ├── board/ │ │ │ ├── avnet-ultra96-rev1.dtsi │ │ │ ├── zc1232-reva.dtsi │ │ │ ├── zc1254-reva.dtsi │ │ │ ├── zc1275-reva.dtsi │ │ │ ├── zc1751-dc1.dtsi │ │ │ ├── zc1751-dc2.dtsi │ │ │ ├── zc1751-dc3.dtsi │ │ │ ├── zc1751-dc4.dtsi │ │ │ ├── zc1751-dc5.dtsi │ │ │ ├── zcu100-revc.dtsi │ │ │ ├── zcu102-rev1.0.dtsi │ │ │ ├── zcu102-reva.dtsi │ │ │ ├── zcu102-revb.dtsi │ │ │ ├── zcu104-reva.dtsi │ │ │ ├── zcu106-reva.dtsi │ │ │ └── zcu111-reva.dtsi │ │ └── zynqmp/ │ │ ├── zynqmp-clk.dtsi │ │ └── zynqmp.dtsi │ └── v5.4/ │ ├── board/ │ │ ├── avnet-ultra96-rev1.dtsi │ │ ├── zc1232-reva.dtsi │ │ ├── zc1254-reva.dtsi │ │ ├── zc1275-reva.dtsi │ │ ├── zc1751-dc1.dtsi │ │ ├── zc1751-dc2.dtsi │ │ ├── zc1751-dc3.dtsi │ │ ├── zc1751-dc4.dtsi │ │ ├── zc1751-dc5.dtsi │ │ ├── zcu100-revc.dtsi │ │ ├── zcu102-rev1.0.dtsi │ │ ├── zcu102-reva.dtsi │ │ ├── zcu102-revb.dtsi │ │ ├── zcu104-reva.dtsi │ │ ├── zcu106-reva.dtsi │ │ └── zcu111-reva.dtsi │ └── zynqmp/ │ ├── zynqmp-clk.dtsi │ └── zynqmp.dtsi ├── dfx_axi_shutdown_manager/ │ └── data/ │ ├── dfx_axi_shutdown_manager.mdd │ └── dfx_axi_shutdown_manager.tcl ├── dmaps/ │ └── data/ │ ├── dmaps.mdd │ └── dmaps.tcl ├── dp/ │ └── data/ │ ├── dp.mdd │ └── dp.tcl ├── dp_rx/ │ └── data/ │ ├── dp_rx.mdd │ └── dp_rx.tcl ├── dp_tx/ │ └── data/ │ ├── dp_tx.mdd │ └── dp_tx.tcl ├── dpu_eu/ │ └── data/ │ ├── dpu_eu.mdd │ └── dpu_eu.tcl ├── emaclite/ │ └── data/ │ ├── emaclite.mdd │ └── emaclite.tcl ├── emacps/ │ └── data/ │ ├── emacps.mdd │ └── emacps.tcl ├── ernic/ │ └── data/ │ ├── ernic.mdd │ └── ernic.tcl ├── framebuf_rd/ │ └── data/ │ ├── framebuf_rd.mdd │ └── framebuf_rd.tcl ├── framebuf_wr/ │ └── data/ │ ├── framebuf_wr.mdd │ └── framebuf_wr.tcl ├── gamma_lut/ │ └── data/ │ ├── gamma_lut.mdd │ └── gamma_lut.tcl ├── generic/ │ └── data/ │ ├── generic.mdd │ └── generic.tcl ├── globaltimerps/ │ └── data/ │ ├── globaltimerps.mdd │ └── globaltimerps.tcl ├── gpiops/ │ └── data/ │ ├── gpiops.mdd │ └── gpiops.tcl ├── hdmi_ctrl/ │ └── data/ │ ├── hdmi_ctrl.mdd │ └── hdmi_ctrl.tcl ├── hdmi_gt_ctrl/ │ └── data/ │ ├── hdmi_gt_ctrl.mdd │ └── hdmi_gt_ctrl.tcl ├── hdmi_rx_ss/ │ └── data/ │ ├── hdmi_rx_ss.mdd │ └── hdmi_rx_ss.tcl ├── hdmi_tx_ss/ │ └── data/ │ ├── hdmi_tx_ss.mdd │ └── hdmi_tx_ss.tcl ├── i2s_receiver/ │ └── data/ │ ├── i2s_receiver.mdd │ └── i2s_receiver.tcl ├── i2s_transmitter/ │ └── data/ │ ├── i2s_transmitter.mdd │ └── i2s_transmitter.tcl ├── i3cpsx/ │ └── data/ │ ├── i3cpsx.mdd │ └── i3cpsx.tcl ├── iicps/ │ └── data/ │ ├── iicps.mdd │ └── iicps.tcl ├── intc/ │ └── data/ │ ├── intc.mdd │ └── intc.tcl ├── isppipeline/ │ └── data/ │ ├── ispipeline.mdd │ └── ispipeline.tcl ├── mig_7series/ │ └── data/ │ ├── mig_7series.mdd │ └── mig_7series.tcl ├── mipi_csi2_rx/ │ └── data/ │ ├── mipi_csi2_rx.mdd │ └── mipi_csi2_rx.tcl ├── mipi_dsi_tx/ │ └── data/ │ ├── mipi_dsi_tx.mdd │ └── mipi_dsi_tx.tcl ├── mixer/ │ └── data/ │ ├── mixer.mdd │ └── mixer.tcl ├── mrmac/ │ └── data/ │ ├── mrmac.mdd │ └── mrmac.tcl ├── multi_scaler/ │ └── data/ │ ├── multi_scaler.mdd │ └── multi_scaler.tcl ├── nandps/ │ └── data/ │ ├── nandps.mdd │ └── nandps.tcl ├── norps/ │ └── data/ │ ├── norps.mdd │ └── norps.tcl ├── nvme_aggr/ │ └── data/ │ ├── nvme_aggr.mdd │ └── nvme_aggr.tcl ├── ocmcps/ │ └── data/ │ ├── ocmcps.mdd │ └── ocmcps.tcl ├── ospips/ │ └── data/ │ ├── ospips.mdd │ └── ospips.tcl ├── pl310ps/ │ └── data/ │ ├── pl310ps.mdd │ └── pl310ps.tcl ├── pmups/ │ └── data/ │ ├── pmups.mdd │ └── pmups.tcl ├── pr_decoupler/ │ └── data/ │ ├── pr_decoupler.mdd │ └── pr_decoupler.tcl ├── ptp_1588_timer_syncer/ │ └── data/ │ ├── ptp_1588_timer_syncer.mdd │ └── ptp_1588_timer_syncer.tcl ├── qspips/ │ └── data/ │ ├── qspips.mdd │ └── qspips.tcl ├── ramps/ │ └── data/ │ ├── ramps.mdd │ └── ramps.tcl ├── rfdc/ │ └── data/ │ ├── rfdc.mdd │ └── rfdc.tcl ├── scene_change_detector/ │ └── data/ │ ├── scene_change_detector.mdd │ └── scene_change_detector.tcl ├── scugic/ │ └── data/ │ ├── scugic.mdd │ └── scugic.tcl ├── scutimer/ │ └── data/ │ ├── scutimer.mdd │ └── scutimer.tcl ├── scuwdt/ │ └── data/ │ ├── scuwdt.mdd │ └── scuwdt.tcl ├── sdfec/ │ └── data/ │ ├── sdfec.mdd │ └── sdfec.tcl ├── sdi_rx/ │ └── data/ │ ├── sdi_rx.mdd │ └── sdi_rx.tcl ├── sdi_tx/ │ └── data/ │ ├── sdi_tx.mdd │ └── sdi_tx.tcl ├── sdps/ │ └── data/ │ ├── sdps.mdd │ └── sdps.tcl ├── slcrps/ │ └── data/ │ ├── slcrps.mdd │ └── slcrps.tcl ├── smccps/ │ └── data/ │ ├── smccps.mdd │ └── smccps.tcl ├── spips/ │ └── data/ │ ├── spips.mdd │ └── spips.tcl ├── sync_ip/ │ └── data/ │ ├── sync_ip.mdd │ └── sync_ip.tcl ├── sysmonpsv/ │ └── data/ │ ├── sysmonpsv.mdd │ └── sysmonpsv.tcl ├── tmrctr/ │ └── data/ │ ├── tmrctr.mdd │ └── tmrctr.tcl ├── tpg/ │ └── data/ │ ├── tpg.mdd │ └── tpg.tcl ├── tsn/ │ └── data/ │ ├── tsn.mdd │ └── tsn.tcl ├── ttcps/ │ └── data/ │ ├── ttcps.mdd │ └── ttcps.tcl ├── uartlite/ │ └── data/ │ ├── uartlite.mdd │ └── uartlite.tcl ├── uartns/ │ └── data/ │ ├── uartns.mdd │ └── uartns.tcl ├── uartps/ │ └── data/ │ ├── uartps.mdd │ └── uartps.tcl ├── usbps/ │ └── data/ │ ├── usbps.mdd │ └── usbps.tcl ├── vid_phy_ctrl/ │ └── data/ │ ├── vid_phy_ctrl.mdd │ └── vid_phy_ctrl.tcl ├── vproc_ss/ │ └── data/ │ ├── vproc_ss.mdd │ └── vproc_ss.tcl ├── vtc/ │ └── data/ │ ├── vtc.mdd │ └── vtc.tcl ├── wdtps/ │ └── data/ │ ├── wdtps.mdd │ └── wdtps.tcl └── xadcps/ └── data/ ├── xadcps.mdd └── xadcps.tcl ================================================ FILE CONTENTS ================================================ ================================================ FILE: .github/pull_request_template.md ================================================ Please do not submit a Pull Request via github. Our project makes use of mailing lists for patch submission and review. For more details please see https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842172/Create+and+Submit+a+Patch ================================================ FILE: .gitignore ================================================ *~ ================================================ FILE: RM/data/RM.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver RM OPTION supported_peripherals = (RM); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = RM; PARAMETER name = dev_type, default = fpga_region, type = string; DTGPARAM name = compatible, default = "fpga-region", type = stringlist; DTGPARAM name = "#address-cells", default = 1, type = int; DTGPARAM name = "#size-cells", default = 1, type = int; DTGPARAM name = ranges, type = boolean; END driver ================================================ FILE: RM/data/RM.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { set val [get_property FAMILY [get_hw_designs]] switch -glob $val { "zynq" { hsi::utils::add_new_property $drv_handle "fpga-mgr" string "<&devcfg>" } } } ================================================ FILE: ai_engine/data/ai_engine.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ai_engine OPTION supported_peripherals = (ai_engine); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ai_engine; END driver ================================================ FILE: ai_engine/data/ai_engine.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # variable aie_array_cols_start variable aie_array_cols_num proc generate_aie_array_device_info {node drv_handle bus_node} { set aie_array_id 0 set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,ai-engine-v2.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist #set default values for S80 device set hw_gen "AIE" set aie_rows_start 1 set aie_rows_num 8 set mem_rows_start 0 set mem_rows_num 0 set shim_rows_start 0 set shim_rows_num 1 set ::aie_array_cols_start 0 set ::aie_array_cols_num 50 # override the above default values if AIE primitives are available in # xsa set CommandExists [ namespace which hsi::get_hw_primitives] if {$CommandExists != ""} { set aie_prop [hsi::get_hw_primitives aie] if {$aie_prop != ""} { puts "INFO: Reading AIE hardware properties from XSA." set hw_gen [get_property HWGEN [hsi::get_hw_primitives aie]] set aie_rows [get_property AIETILEROWS [hsi::get_hw_primitives aie]] set mem_rows [get_property MEMTILEROW [hsi::get_hw_primitives aie]] set shim_rows [get_property SHIMROW [hsi::get_hw_primitives aie]] set ::aie_array_cols_num [get_property AIEARRAYCOLUMNS [hsi::get_hw_primitives aie]] set aie_rows_start [lindex [split $aie_rows ":"] 0] set aie_rows_num [lindex [split $aie_rows ":"] 1] set mem_rows_start [lindex [split $mem_rows ":"] 0] if {$mem_rows_start==-1} { set mem_rows_start 0 } set mem_rows_num [lindex [split $mem_rows ":"] 1] set shim_rows_start [lindex [split $shim_rows ":"] 0] set shim_rows_num [lindex [split $shim_rows ":"] 1] } else { dtg_warning "$drv_handle: AIE hardware properties are not available in XSA, using defaults." } } else { dtg_warning "$drv_handle: AIE hardware properties are not available in XSA, using defaults." } if {$hw_gen=="AIE"} { append aiegen "/bits/ 8 <0x1>" } elseif {$hw_gen=="AIEML"} { append aiegen "/bits/ 8 <0x2>" } hsi::utils::add_new_dts_param "${node}" "xlnx,aie-gen" $aiegen noformating append shimrows "/bits/ 8 <${shim_rows_start} ${shim_rows_num}>" hsi::utils::add_new_dts_param "${node}" "xlnx,shim-rows" $shimrows noformating append corerows "/bits/ 8 <${aie_rows_start} ${aie_rows_num}>" hsi::utils::add_new_dts_param "${node}" "xlnx,core-rows" $corerows noformating append memrows "/bits/ 8 <$mem_rows_start $mem_rows_num>" hsi::utils::add_new_dts_param "${node}" "xlnx,mem-rows" $memrows noformating set name [get_property NAME [get_current_part $drv_handle]] set part_num [string range $name 0 7] if {$part_num == "xcvp2502"} { #s100 set power_domain "&versal_firmware 0x18225072" } elseif {$part_num == "xcvp2802"} { #s200 set power_domain "&versal_firmware 0x18227072" } else { set power_domain "&versal_firmware 0x18224072" } hsi::utils::add_new_dts_param "${node}" "power-domains" $power_domain intlist hsi::utils::add_new_dts_param "${node}" "#address-cells" "2" intlist hsi::utils::add_new_dts_param "${node}" "#size-cells" "2" intlist hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean set ai_clk_node [add_or_get_dt_node -n "aie_core_ref_clk_0" -l "aie_core_ref_clk_0" -p ${bus_node}] set clk_freq [get_property CONFIG.AIE_CORE_REF_CTRL_FREQMHZ [get_cells -hier $drv_handle]] set clk_freq [expr ${clk_freq} * 1000000] hsi::utils::add_new_dts_param "${ai_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${ai_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${ai_clk_node}" "clock-frequency" $clk_freq int set clocks "aie_core_ref_clk_0" set_drv_prop $drv_handle clocks "$clocks" reference hsi::utils::add_new_dts_param "${node}" "clock-names" "aclk0" stringlist return ${node} } proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set RpRm [hsi::utils::get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm "" RpRm set bus_node "amba" } else { set bus_node "amba_pl" } generate_aie_array_device_info ${node} ${drv_handle} ${bus_node} set ip [get_cells -hier $drv_handle] set unit_addr [get_baseaddr ${ip} no_prefix] set aperture_id 0 set aperture_node [add_or_get_dt_node -n "aie_aperture" -u "${unit_addr}" -l "aie_aperture_${aperture_id}" -p ${node}] set reg [get_property CONFIG.reg ${drv_handle}] hsi::utils::add_new_dts_param "${aperture_node}" "reg" $reg noformat set name [get_property NAME [get_current_part $drv_handle]] set part_num [string range $name 0 7] set part_num_v70 [string range $name 0 4] if {$part_num == "xcvp2502"} { #s100 set power_domain "&versal_firmware 0x18225072" hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "100" int set aperture_nodeid 0x18801000 } elseif {$part_num == "xcvp2802"} { #s200 set power_domain "&versal_firmware 0x18227072" hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "200" int set aperture_nodeid 0x18803000 } elseif {$part_num_v70 == "xcv70"} { #v70 set power_domain "&versal_firmware 0x18224072" hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "0" int set aperture_nodeid 0x18800000 } else { #NON SSIT devices set intr_names "interrupt1" lappend intr_names "interrupt2" lappend intr_names "interrupt3" set intr_num "0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4" set power_domain "&versal_firmware 0x18224072" hsi::utils::add_new_dts_param "${aperture_node}" "interrupt-names" $intr_names stringlist hsi::utils::add_new_dts_param "${aperture_node}" "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${aperture_node}" "interrupt-parent" gic reference hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "0" int set aperture_nodeid 0x18800000 } hsi::utils::add_new_dts_param "${aperture_node}" "power-domains" $power_domain intlist hsi::utils::add_new_dts_param "${aperture_node}" "#address-cells" "2" intlist hsi::utils::add_new_dts_param "${aperture_node}" "#size-cells" "2" intlist hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,columns" "$::aie_array_cols_start $::aie_array_cols_num" intlist hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,node-id" "${aperture_nodeid}" intlist } ================================================ FILE: ams/data/ams.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ams OPTION supported_peripherals = (psu_ams); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ams; END driver ================================================ FILE: ams/data/ams.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { set ams_list "ams_ps ams_pl" set dts_file [get_property CONFIG.pcw_dts [get_os]] foreach ams_name ${ams_list} { set ams_node [add_or_get_dt_node -n "&${ams_name}" -d $dts_file] hsi::utils::add_new_dts_param "${ams_node}" "status" "okay" string } } } ================================================ FILE: apmps/data/apmps.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver apmps OPTION supported_peripherals = (psu_apm psv_apm psx_apm); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = apmps; END driver ================================================ FILE: apmps/data/apmps.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: audio_embed/data/audio_embed.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver audio_embed OPTION supported_peripherals = (v_uhdsdi_audio); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = audio_embed; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: audio_embed/data/audio_embed.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-uhdsdi-audio-2.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set connected_embed_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "SDI_EMBED_ANC_DS_IN"] if {[llength $connected_embed_ip] != 0} { set connected_embed_ip_type [get_property IP_NAME $connected_embed_ip] if {[string match -nocase $connected_embed_ip_type "v_smpte_uhdsdi_tx_ss"]} { set sdi_av_port [add_or_get_dt_node -n "port" -l sdi_av_port -u 0 -p $node] hsi::utils::add_new_dts_param "$sdi_av_port" "reg" 0 int set sdi_embed_node [add_or_get_dt_node -n "endpoint" -l sditx_audio_embed_src -p $sdi_av_port] hsi::utils::add_new_dts_param "$sdi_embed_node" "remote-endpoint" sdi_audio_sink_port reference } } else { dtg_warning "$drv_handle connected_ip is NULL for the pin SDI_EMBED_ANC_DS_IN" } set connected_extract_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "SDI_EXTRACT_ANC_DS_IN"] if {[llength $connected_extract_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,sdi-rx-video" $connected_extract_ip reference } else { dtg_warning "$drv_handle connected_extract_ip is NULL for the pin SDI_EXTRACT_ANC_DS_IN" } set connected_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_DATA"] if {[llength $connected_ip] != 0} { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connected_ip] if {$index != -1 } { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference } } else { dtg_warning "$drv_handle connected ip is NULL for the pin S_AXIS_DATA" } set connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "M_AXIS_DATA"] if {[llength $connect_ip] != 0} { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connect_ip] if {$index != -1 } { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connect_ip reference } } else { dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_DATA" } } ================================================ FILE: audio_formatter/data/audio_formatter.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver audio_formatter OPTION supported_peripherals = (audio_formatter); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = audio_formatter; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: audio_formatter/data/audio_formatter.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,audio-formatter-1.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set tx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_mm2s"] if {[llength $tx_connect_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,tx" $tx_connect_ip reference } else { dtg_warning "$drv_handle pin m_axis_mm2s is not connected... check your design" } set rx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_s2mm"] if {[llength $rx_connect_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,rx" $rx_connect_ip reference } else { dtg_warning "$drv_handle pin s_axis_s2mm is not connected... check your design" } } ================================================ FILE: audio_spdif/data/audio_spdif.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver audio_spdif OPTION supported_peripherals = (spdif); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = audio_spdif; END driver ================================================ FILE: audio_spdif/data/audio_spdif.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,spdif-2.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set spdif_mode [get_property CONFIG.SPDIF_Mode [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,spdif-mode" $spdif_mode int set cstatus_reg [get_property CONFIG.CSTATUS_REG [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,chstatus-reg" $cstatus_reg int set userdata_reg [get_property CONFIG.USERDATA_REG [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,userdata-reg" $userdata_reg int set axi_buffer_size [get_property CONFIG.AXI_BUFFER_Size [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,fifo-depth" $axi_buffer_size int set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "aud_clk_i"] if {[llength $clk_freq] != 0} { hsi::utils::add_new_dts_param "${node}" "clock-frequency" $clk_freq int } } ================================================ FILE: axi_can/data/axi_can.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_can OPTION supported_peripherals = (can canfd); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_can; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-can-1.00.a"; END driver ================================================ FILE: axi_can/data/axi_can.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-can-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]] set ecc [get_property CONFIG.ENABLE_ECC [get_cells -hier $drv_handle]] if { [llength $ecc] } { hsi::utils::add_new_dts_param $node "xlnx,has-ecc" "" boolean } set version [string tolower [common::get_property VLNV $drv_handle]] if {[string match -nocase $ip_name "canfd"]} { if {[string compare -nocase "xilinx.com:ip:canfd:1.0" $version] == 0} { hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,canfd-1.0" } else { hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,canfd-2.0" } set_drv_conf_prop $drv_handle NUM_OF_TX_BUF tx-mailbox-count hexint set_drv_conf_prop $drv_handle NUM_OF_TX_BUF rx-fifo-depth hexint } else { set_drv_conf_prop $drv_handle c_can_tx_dpth tx-fifo-depth hexint set_drv_conf_prop $drv_handle c_can_rx_dpth rx-fifo-depth hexint } set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_aclk" } } } ================================================ FILE: axi_cdma/data/axi_cdma.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_cdma OPTION supported_peripherals = (axi_cdma); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_cdma; DTGPARAM name = dev_type, default = dma , type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-cdma-1.00.a"; DTGPARAM name = "#dma-cells", type = int, default = 1; END driver ================================================ FILE: axi_cdma/data/axi_cdma.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean set_drv_conf_prop $drv_handle C_NUM_FSTORES xlnx,num-fstores set_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync set_drv_conf_prop $drv_handle C_ADDR_WIDTH xlnx,addrwidth set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-cdma-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dma_ip [get_cells -hier $drv_handle] set cdma_count [hsi::utils::get_os_parameter_value "cdma_count"] if { [llength $cdma_count] == 0 } { set cdma_count 0 } set baseaddr [get_baseaddr $dma_ip no_prefix] set tx_chan [add_dma_channel $drv_handle $node "axi-cdma" $baseaddr "MM2S" $cdma_count ] incr cdma_count hsi::utils::set_os_parameter_value "cdma_count" $cdma_count set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk" set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist } } } else { generate_clk_nodes $drv_handle } } proc add_dma_channel {drv_handle parent_node xdma addr mode devid} { #set ip [get_cells -hier $drv_handle] set modellow [string tolower $mode] set modeIndex [string index $mode 0] #set node_name [format "dma-channel@%x" $addr] set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node] hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-channel" $xdma] stringlist hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint add_cross_property_to_dtnode $drv_handle "CONFIG.C_INCLUDE_DRE" $dma_channel "xlnx,include-dre" boolean add_cross_property_to_dtnode $drv_handle "CONFIG.C_M_AXI_DATA_WIDTH" $dma_channel "xlnx,datawidth" add_cross_property_to_dtnode $drv_handle "CONFIG.C_USE_DATAMOVER_LITE" $dma_channel "xlnx,lite-mode" boolean add_cross_property_to_dtnode $drv_handle "CONFIG.C_M_AXI_MAX_BURST_LEN" $dma_channel "xlnx,max-burst-len" set intr_info [get_intr_id $drv_handle "cdma_introut" ] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $dma_channel "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: cdma_introut port is not connected" } return $dma_channel } proc generate_clk_nodes {drv_handle} { set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "ps7_cortexa9" { set_drv_prop_if_empty $drv_handle "clocks" "clkc 15>, <&clkc 15" reference set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist } "psu_cortexa53" { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set dts_file [current_dt_tree] set bus_node [add_or_get_bus_node $drv_handle $dts_file] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set_drv_prop_if_empty $drv_handle "clocks" "$clk_refs>, <&$clk_refs" reference set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist } "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk" set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist } default { error "Unknown arch" } } } ================================================ FILE: axi_clk_wiz/data/axi_clk_wiz.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_clk_wiz OPTION supported_peripherals = (clk_wiz clk_wizard); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_clk_wiz; #DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = compatible, type = stringlist, default = "xlnx,clocking-wizard"; DTGPARAM name = clock-output-names, type = stringlist, default = ""; DTGPARAM name = "#clock-cells", type = int, default = 1; END driver ================================================ FILE: axi_clk_wiz/data/axi_clk_wiz.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,clocking-wizard"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] gen_speedgrade $drv_handle set j 0 set output_names "" for {set i 1} {$i < 8} {incr i} { if {[get_property CONFIG.C_CLKOUT${i}_USED $ip] != 0} { set freq [get_property CONFIG.C_CLKOUT${i}_OUT_FREQ $ip] set pin_name [get_property CONFIG.C_CLK_OUT${i}_PORT $ip] set basefrq [string tolower [get_property CONFIG.C_BASEADDR $ip]] set pin_name "$basefrq-$pin_name" lappend output_names $pin_name incr j } } if {![string_is_empty $output_names]} { set_property CONFIG.clock-output-names $output_names $drv_handle hsi::utils::add_new_property $drv_handle "xlnx,nr-outputs" int $j } gen_dev_ccf_binding $drv_handle "clk_in1 s_axi_aclk" "clocks clock-names" set sw_proc [get_sw_processor] set proc_ip [get_cells -hier $sw_proc] set proctype [get_property IP_NAME $proc_ip] if {[string match -nocase $proctype "microblaze"] } { gen_dev_ccf_binding $drv_handle "clk_in1 s_axi_aclk" "clocks clock-names" } } proc gen_speedgrade {drv_handle} { set speedgrade [get_property SPEEDGRADE [get_hw_designs]] set num [regexp -all -inline -- {[0-9]} $speedgrade] if {![string equal $num ""]} { hsi::utils::add_new_property $drv_handle "xlnx,speed-grade" int $num } } ================================================ FILE: axi_dma/data/axi_dma.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_dma OPTION supported_peripherals = (axi_dma); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_dma; DTGPARAM name = dev_type, default = dma , type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-dma-1.00.a"; DTGPARAM name = "#dma-cells", type = int, default = 1; END driver ================================================ FILE: axi_dma/data/axi_dma.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # set connected_ip 0 proc generate {drv_handle} { global connected_ip # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-dma-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dma_ip [get_cells -hier $drv_handle] set dma_count [hsi::utils::get_os_parameter_value "dma_count"] if { [llength $dma_count] == 0 } { set dma_count 0 } set axiethernetfound 0 set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"] if { [llength $connected_ip] } { set connected_ip_type [get_property IP_NAME $connected_ip] if { [string match -nocase $connected_ip_type axi_ethernet ] || [string match -nocase $connected_ip_type axi_ethernet_buffer ] } { set axiethernetfound 1 } } else { dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_MM2S" } set is_xxv [get_connected_ip $drv_handle "M_AXIS_MM2S"] if { $axiethernetfound || $is_xxv == 1} { set compatstring "xlnx,eth-dma" set_property compatible "$compatstring" $drv_handle } set tx_chan 0 set rx_chan 0 if { $axiethernetfound != 1 && $is_xxv != 1} { set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean set_drv_conf_prop $drv_handle C_SG_INCLUDE_STSCNTRL_STRM xlnx,sg-include-stscntrl-strm boolean set_drv_conf_prop $drv_handle c_enable_multi_channel xlnx,multichannel-dma boolean set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth set_drv_conf_prop $drv_handle c_sg_length_width xlnx,sg-length-width set baseaddr [get_baseaddr $dma_ip no_prefix] set tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S] if { $tx_chan == 1 } { set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"] set tx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $baseaddr "MM2S" $dma_count ] set intr_info [get_intr_id $drv_handle "mm2s_introut"] #set intc [hsi::utils::get_interrupt_parent $dma_ip "mm2s_introut"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected" } add_dma_coherent_prop $drv_handle "M_AXI_MM2S" } set rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM] if { $rx_chan ==1 } { set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "S_AXIS_S2MM"] set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]] set rx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $rx_bassaddr "S2MM" $dma_count] set intr_info [get_intr_id $drv_handle "s2mm_introut"] #set intc [hsi::utils::get_interrupt_parent $dma_ip "s2mm_introut"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected" } add_dma_coherent_prop $drv_handle "M_AXI_S2MM" } } else { set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"] } { set_drv_property $drv_handle axistream-connected "$connected_ip" reference set_drv_property $drv_handle axistream-control-connected "$connected_ip" reference } set ip_prop CONFIG.c_include_mm2s_dre add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean set addr_width [get_property CONFIG.c_addr_width $dma_ip] set inhex [format %x $addr_width] append addrwidth "/bits/ 8 <0x$inhex>" hsi::utils::add_new_dts_param "$node" "xlnx,addrwidth" $addrwidth noformating set num_queues [get_property CONFIG.c_num_mm2s_channels $dma_ip] set inhex [format %x $num_queues] append numqueues "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating } incr dma_count hsi::utils::set_os_parameter_value "dma_count" $dma_count set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "microblaze"]} { generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan } } else { generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan } } proc add_dma_channel {drv_handle parent_node xdma addr mode devid} { set modellow [string tolower $mode] set modeIndex [string index $mode 0] set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node] hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean if {[string match -nocase $mode "MM2S"]} { set datawidth [get_property CONFIG.C_M_AXI_MM2S_DATA_WIDTH [get_cells -hier $drv_handle]] } if {[string match -nocase $mode "S2MM"]} { set datawidth [get_property CONFIG.C_S_AXIS_S2MM_TDATA_WIDTH [get_cells -hier $drv_handle]] } hsi::utils::add_new_dts_param $dma_channel "xlnx,datawidth" $datawidth hexint set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param $dma_channel "dma-channels" $num_channles hexint return $dma_channel } proc add_dma_coherent_prop {drv_handle intf} { set ip_name [::hsi::get_cells -hier -filter "NAME==$drv_handle"] set connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf] if {[llength $connectedip] == 0} { return } set intrconnect [get_property IP_NAME [get_cells -hier $connectedip]] set num_master [get_property CONFIG.NUM_MI $connectedip] set done 0 # check whether dma connected to interconnect ip, loop until you get the # port name ACP or HP while {[string match -nocase $intrconnect "axi_interconnect"]} { # loop over number of master interfaces set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}] if {[llength $master_intf] == 0} { break } foreach interface ${master_intf} { set intf_port [hsi::utils::get_connected_intf $connectedip $interface] set intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface] if {![string_is_empty $intf_port] && [string match -nocase $intf_port "S_AXI_ACP"]} { hsi::utils::add_new_property $drv_handle "dma-coherent" boolean "" # here dma connected to ACP port set done 1 break; } if {$done} { break } } } } proc generate_clk_nodes {drv_handle axiethernetfound tx_chan rx_chan} { set proc_type [get_sw_proc_prop IP_NAME] set clocknames "s_axi_lite_aclk" switch $proc_type { "ps7_cortexa9" { set clocks "clkc 15" if { $axiethernetfound != 1 } { append clocknames " " "m_axi_sg_aclk" append clocks "" ">, <&clkc 15" } if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocks "" ">, <&clkc 15" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocks "" ">, <&clkc 15" } set_drv_prop_if_empty $drv_handle "clocks" $clocks reference set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist } "psu_cortexa53" { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set dts_file [current_dt_tree] set bus_node [add_or_get_bus_node $drv_handle $dts_file] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set clocks "$clk_refs" if { $axiethernetfound != 1 } { append clocknames " " "m_axi_sg_aclk" append clocks "" ">, <&$clk_refs" } if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocks "" ">, <&$clk_refs" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocks "" ">, <&$clk_refs" } set_drv_prop_if_empty $drv_handle "clocks" "$clocks" reference set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist } "microblaze" { if { $axiethernetfound != 1 } { append clocknames " " "m_axi_sg_aclk" } if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" } gen_dev_ccf_binding $drv_handle "$clocknames" set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist } default { error "Unknown arch" } } } proc get_connected_ip {drv_handle dma_pin} { global connected_ip # Check whether dma is connected to 10G/25G MAC # currently we are handling only data fifo set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin] set valid_eth_list "xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g" if {[string_is_empty ${intf}]} { return 0 } set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf] if {[string_is_empty ${connected_ip}]} { dtg_warning "$drv_handle connected ip is NULL for the pin $intf" return 0 } set iptype [get_property IP_NAME [get_cells -hier $connected_ip]] if {[string match -nocase $iptype "axis_data_fifo"] } { # here dma connected to data fifo set dma_pin "M_AXIS" get_connected_ip $connected_ip $dma_pin } elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } { # dma connected to 10G/25G MAC, 1G or 10G return 1 } elseif {[string match -nocase $iptype "axis_add_tuser"]|| [string match -nocase $iptype "axis_duplicate_master_out"]} { set dma_pin "mas_0" get_connected_ip $connected_ip $dma_pin } elseif {[string match -nocase $iptype "axis_switch"]} { set dma_pin "M00_AXIS" get_connected_ip $connected_ip $dma_pin } else { # dma connected via interconnects set dma_pin "M_AXIS" get_connected_ip $connected_ip $dma_pin } } ================================================ FILE: axi_emc/data/axi_emc.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_emc OPTION supported_peripherals = (axi_emc); OPTION driver_state = ACTIVE; OPTION NAME = axi_emc; OPTION supported_os_types = (DTS); DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = dev_type, default = flash , type = string; DTGPARAM name = compatible, type =stringlist, default = "cfi-flash"; DTGPARAM name = bank-width, type = int; END driver ================================================ FILE: axi_emc/data/axi_emc.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ip [get_cells -hier $drv_handle] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "cfi-flash"] set_drv_prop $drv_handle compatible "$compatible" stringlist set count [hsi::utils::get_ip_param_value $ip "C_NUM_BANKS_MEM"] if { [llength $count] == 0 } { set count 1 } for {set x 0} { $x < $count} {incr x} { set datawidth [hsi::utils::get_ip_param_value $ip [format "C_MEM%d_WIDTH" $x]] set_property bank-width "[expr ($datawidth/8)]" $drv_handle } } ================================================ FILE: axi_ethernet/data/axi_ethernet.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_ethernet OPTION supported_peripherals = (axi_ethernet axi_ethernet_buffer axi_10g_ethernet xxv_ethernet usxgmii ethernet_1_10_25g); OPTION driver_state = ACTIVE; OPTION NAME = axi_ethernet; OPTION supported_os_types = (DTS); PARAMETER name = dev_type, default = ethernet, type = string; DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = dtg.alias , type = reference, default = ethernet; DTGPARAM name = axistream-connected , type = reference; DTGPARAM name = axistream-control-connected, type = reference; DTGPARAM name = clock-frequency, type = int, default = 100000000; DTGPARAM name = compatible, type =stringlist, default = "xlnx,axi-ethernet-1.00.a"; DTGPARAM name = device_type, type = string, default = network; DTGPARAM name = xlnx,txcsum, type = hex, default = 0x0; DTGPARAM name = xlnx,rxcsum, type = hex, default = 0x0; DTGPARAM name = xlnx,rxmem, type = hex, default = 0x8000; DTGPARAM name = xlnx,phyaddr, type = hex, default = 0x0; DTGPARAM name = phy-mode, default = gmii END driver ================================================ FILE: axi_ethernet/data/axi_ethernet.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # set rxethmem 0 proc generate {drv_handle} { global rxethmem set rxethmem 0 global ddrv_handle set ddrv_handle $drv_handle foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set node [gen_peripheral_nodes $drv_handle] set hw_design [hsi::current_hw_design] set board_name "" if {[llength $hw_design]} { set board [split [get_property BOARD $hw_design] ":"] set board_name [lindex $board 1] } update_eth_mac_addr $drv_handle set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-ethernet-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set default_dts [set_drv_def_dts $drv_handle] #adding stream connectivity set eth_ip [get_cells -hier $drv_handle] # search for a valid bus interface name # This is required to work with Vivado 2015.1 due to IP PIN naming change set hasbuf [get_property CONFIG.processor_mode $eth_ip] set ip_name [get_property IP_NAME $eth_ip] set num_cores 1 if {($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]] set num 0 set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $num]]] set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $num]]] set reg [generate_reg_property $base $high] hsi::utils::add_new_dts_param "${node}" "reg" $reg inthexlist set num_cores [get_property CONFIG.NUM_OF_CORES [get_cells -hier $drv_handle]] } set new_label "" set clk_label "" set connected_ip "" set eth_node "" for {set core 0} {$core < $num_cores} {incr core} { if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} { if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set dts_file [current_dt_tree] set ipmem_len [llength $ip_mem_handles] if {$ipmem_len > 1} { set base_addr [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]] regsub -all {^0x} $base_addr {} base_addr append new_label $drv_handle "_" $core append clk_label $drv_handle "_" $core set eth_node [add_or_get_dt_node -n "ethernet" -l "$new_label" -u $base_addr -d $dts_file -p $bus_node] set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]] set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $core]]] set reg [generate_reg_property $base $high] hsi::utils::add_new_dts_param "${eth_node}" "reg" $reg inthexlist } } if {(($hasbuf == "true") || ($hasbuf == "")) && ($ip_name != "axi_10g_ethernet") && ($ip_name != "ten_gig_eth_mac") && ($ip_name != "xxv_ethernet") && ($ip_name != "usxgmii") && ($ip_name != "ethernet_1_10_25g")} { foreach n "AXI_STR_RXD m_axis_rxd" { set intf [get_intf_pins -of_objects $eth_ip ${n}] if {[string_is_empty ${intf}] != 1} { break } } if { [llength $intf] } { set intf_net [get_intf_nets -of_objects $intf ] if { [llength $intf_net] } { set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf] if { [llength $target_intf] } { set connected_ip [get_connectedip $intf] if {[llength $connected_ip]} { set_property axistream-connected "$connected_ip" $drv_handle set_property axistream-control-connected "$connected_ip" $drv_handle set ip_prop CONFIG.c_include_mm2s_dre add_cross_property $connected_ip $ip_prop $drv_handle "xlnx,include-dre" boolean } else { dtg_warning "$drv_handle connected ip is NULL for the interface $intf" } set ip_prop CONFIG.Enable_1588 add_cross_property $eth_ip $ip_prop $drv_handle "xlnx,eth-hasptp" boolean } } } foreach n "AXI_STR_RXD m_axis_tx_ts" { set intf [get_intf_pins -of_objects $eth_ip ${n}] if {[string_is_empty ${intf}] != 1} { break } } if {[string_is_empty ${intf}] != 1} { set tx_tsip [get_connectedip $intf] set_drv_prop $drv_handle axififo-connected "$tx_tsip" reference } } else { foreach n "AXI_STR_RXD m_axis_rx" { set intf [get_intf_pins -of_objects $eth_ip ${n}] if {[string_is_empty ${intf}] != 1} { break } } if {($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g") || ($ip_name == "usxgmii")} { foreach n "AXI_STR_RXD axis_rx_0" { set intf [get_intf_pins -of_objects $eth_ip ${n}] if {[string_is_empty ${intf}] != 1} { break } } } if { [llength $intf] } { set connected_ip [get_connectedip $intf] } foreach n "AXI_STR_RXD m_axis_tx_ts" { set intf [get_intf_pins -of_objects $eth_ip ${n}] if {[string_is_empty ${intf}] != 1} { break } } if {[string_is_empty ${intf}] != 1} { set tx_tsip [get_connectedip $intf] if {[llength $tx_tsip]} { set_drv_prop $drv_handle axififo-connected "$tx_tsip" reference } } else { set port_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $eth_ip] "tx_ptp_tag_field_in_0"]] if {[llength $port_pins]} { set periph [::hsi::get_cells -of_objects $port_pins] if {[llength $periph]} { if {[string match -nocase [get_property IP_NAME $periph] "xlslice"]} { set intf "Din" set in1_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]] if {[llength $sink_pins]} { set per [::hsi::get_cells -of_objects $sink_pins] if {[llength $per] && [string match -nocase [get_property IP_NAME $per] "axis_clock_converter"]} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $per] "s_axis_tdata"]] if {[llength $pins]} { set txfifo [get_cells -of_objects $pins] if {[llength $txfifo]} { set_drv_prop $drv_handle axififo-connected "$txfifo" reference } } } } } } } } set rxfifo_port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $eth_ip] "rx_ptp_tstamp_out_0"]] if {[llength $rxfifo_port_pins]} { set periph [::hsi::get_cells -of_objects $rxfifo_port_pins] if {[llength $periph]} { if {[string match -nocase [get_property IP_NAME $periph] "xlconcat"]} { set intf "dout" set in1_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]] if {[llength $sink_pins]} { set per [::hsi::get_cells -of_objects $sink_pins] if {[llength $per] && [string match -nocase [get_property IP_NAME $per] "axis_dwidth_converter"]} { set con_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $per] "M_AXIS"] if {[llength $con_ip]} { if {[string match -nocase [get_property IP_NAME $con_ip] "axis_clock_converter"]} { set rxtsfifo_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $con_ip] "M_AXIS"] if {[llength $rxtsfifo_ip]} { set_drv_prop $drv_handle xlnx,rxtsfifo "$rxtsfifo_ip" reference } } } } } } } } if {![string_is_empty $connected_ip]} { set_property axistream-connected "$connected_ip" $drv_handle set_property axistream-control-connected "$connected_ip" $drv_handle set ip_prop CONFIG.c_include_mm2s_dre add_cross_property $connected_ip $ip_prop $drv_handle "xlnx,include-dre" boolean } set_property xlnx,rxmem "$rxethmem" $drv_handle if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} { set intf [get_intf_pins -of_objects $eth_ip "axis_rx_${core}"] if {[llength $intf] && [llength $eth_node]} { set connected_ip [get_connectedip $intf] if {![string_is_empty $connected_ip]} { hsi::utils::add_new_dts_param $eth_node "axistream-connected" "$connected_ip" reference hsi::utils::add_new_dts_param $eth_node "axistream-control-connected" "$connected_ip" reference } hsi::utils::add_new_dts_param $eth_node "xlnx,include-dre" "" boolean hsi::utils::add_new_dts_param $eth_node "xlnx,rxmem" "$rxethmem" hex } } } if {$ip_name == "axi_ethernet"} { set txcsum [get_property CONFIG.TXCSUM $eth_ip] set txcsum [get_checksum $txcsum] set rxcsum [get_property CONFIG.RXCSUM $eth_ip] set rxcsum [get_checksum $rxcsum] set phytype [get_property CONFIG.PHY_TYPE $eth_ip] set phytype [get_phytype $phytype] set phyaddr [get_property CONFIG.PHYADDR $eth_ip] set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr] set rxmem [get_property CONFIG.RXMEM $eth_ip] set rxmem [get_memrange $rxmem] set_property xlnx,txcsum "$txcsum" $drv_handle set_property xlnx,rxcsum "$rxcsum" $drv_handle set_property xlnx,phyaddr "$phyaddr" $drv_handle set_property xlnx,rxmem "$rxmem" $drv_handle } set is_nobuf 0 if {$ip_name == "axi_ethernet"} { set avail_param [list_property [get_cells -hier $drv_handle]] if {[lsearch -nocase $avail_param "CONFIG.speed_1_2p5"] >= 0} { if {[get_property CONFIG.speed_1_2p5 [get_cells -hier $drv_handle]] == "2p5G"} { set is_nobuf 1 set_property compatible "xlnx,axi-2_5-gig-ethernet-1.0" $drv_handle } } } if { $hasbuf == "false" && $is_nobuf == 0} { set ip_prop CONFIG.processor_mode add_cross_property $eth_ip $ip_prop $drv_handle "xlnx,eth-hasnobuf" boolean } #adding clock frequency set clk [get_pins -of_objects $eth_ip "S_AXI_ACLK"] if {[llength $clk] } { set freq [get_property CLK_FREQ $clk] set_property clock-frequency "$freq" $drv_handle if {$ip_name == "xxv_ethernet" && [llength $eth_node]} { hsi::utils::add_new_dts_param $eth_node "clock-frequency" "$freq" int } } # node must be created before child node set node [gen_peripheral_nodes $drv_handle] if {$ip_name == "axi_ethernet"} { set hier_params [gen_hierip_params $drv_handle] } set mdio_node [gen_mdio_node $drv_handle $node] set phytype [string tolower [get_property CONFIG.PHY_TYPE $eth_ip]] if {$phytype == "rgmii" && $board_name == "kc705"} { set phytype "rgmii-rxid" } elseif {$phytype == "1000basex"} { set phytype "1000base-x" } set_property phy-mode "$phytype" $drv_handle if {$phytype == "sgmii" || $phytype == "1000base-x"} { set_property phy-mode "$phytype" $drv_handle set phynode [pcspma_phy_node $eth_ip] set phya [lindex $phynode 0] if { $phya != "-1"} { set phy_name "[lindex $phynode 1]" set_drv_prop $drv_handle pcs-handle "$drv_handle$phy_name" reference gen_phy_node $mdio_node $phy_name $phya $drv_handle if {[llength $node]} { hsi::utils::add_new_dts_param $node "managed" "in-band-status" string hsi::utils::add_new_dts_param $node "xlnx,switch-x-sgmii" "" boolean } } } if {$ip_name == "xxv_ethernet" && $core != 0 && [llength $eth_node]} { append new_label "_" mdio set mdionode [add_or_get_dt_node -l "$new_label" -n mdio -p $eth_node] hsi::utils::add_new_dts_param "${mdionode}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${mdionode}" "#size-cells" 0 int "" set new_label "" } if {$ip_name == "axi_10g_ethernet"} { set phytype [string tolower [get_property CONFIG.base_kr $eth_ip]] set_property phy-mode "$phytype" $drv_handle set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,ten-gig-eth-mac"] set_property compatible "$compatible" $drv_handle } if {$ip_name == "xxv_ethernet"} { set phytype [string tolower [get_property CONFIG.BASE_R_KR $eth_ip]] set linerate [get_property CONFIG.LINE_RATE $eth_ip] set_property phy-mode "${linerate}g${phytype}" $drv_handle set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xxv-ethernet-1.0"] set_property compatible "$compatible" $drv_handle set_property "managed" "in-band-status" $drv_handle if { $core!= 0 && [llength $eth_node]} { hsi::utils::add_new_dts_param $eth_node "compatible" $compatible stringlist hsi::utils::add_new_dts_param $eth_node "phy-mode" "${linerate}g${phytype}" string hsi::utils::add_new_dts_param $eth_node "managed" "in-band-status" string } } if {$ip_name == "usxgmii"} { set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xxv-usxgmii-ethernet-1.0"] set_property compatible $compatible $drv_handle # phy-mode is usxgmii in this case ip_name also same set_property phy-mode "$ip_name" $drv_handle hsi::utils::add_new_dts_param $node "xlnx,usxgmii-rate" 1000 int } set ips [get_cells -hier $drv_handle] foreach ip [get_drivers] { if {[string compare -nocase $ip $connected_ip] == 0} { set target_handle $ip } } set hsi_version [get_hsi_version] set ver [split $hsi_version "."] set version [lindex $ver 0] if {![string_is_empty $connected_ip]} { set connected_ipname [get_property IP_NAME $connected_ip] if {$connected_ipname == "axi_mcdma" || $connected_ipname == "axi_dma"} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set num_queues [get_property CONFIG.c_num_mm2s_channels $connected_ip] set inhex [format %x $num_queues] set numqueues "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating if {$version < 2018} { dtg_warning "quotes to be removed or use 2018.1 version for $node param xlnx,num-queues" } set id 1 for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%x" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } set_drv_prop $drv_handle "xlnx,channel-ids" $id stringlist if {$ip_name == "xxv_ethernet" && $core!= 0 && [llength $eth_node]} { hsi::utils::add_new_dts_param $eth_node "xlnx,num-queues" $numqueues noformating hsi::utils::add_new_dts_param $eth_node "xlnx,channel-ids" $id stringlist } set intr_val [get_property CONFIG.interrupts $target_handle] set intr_parent [get_property CONFIG.interrupt-parent $target_handle] set int_names [get_property CONFIG.interrupt-names $target_handle] if { $hasbuf == "true" && $ip_name == "axi_ethernet"} { set intr_val1 [get_property CONFIG.interrupts $drv_handle] lappend intr_val1 $intr_val set intr_name [get_property CONFIG.interrupt-names $drv_handle] append intr_names " " $intr_name " " $int_names if {![string match -nocase $proctype "microblaze"]} { set null "" set_property "interrupt-names" $null $drv_handle set_property "interrupts" $null $drv_handle } } else { set intr_names $int_names } if {![string_is_empty $intr_parent]} { if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core!= 0) && [llength $eth_node]} { hsi::utils::add_new_dts_param "${eth_node}" "interrupts" $intr_val int hsi::utils::add_new_dts_param "${eth_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${eth_node}" "interrupt-names" $intr_names stringlist } else { if { $hasbuf == "true" && $ip_name == "axi_ethernet"} { regsub -all "\{||\t" $intr_val1 {} intr_val1 regsub -all "\}||\t" $intr_val1 {} intr_val1 if {![string match -nocase $proctype "microblaze"]} { set_property "interrupts" $intr_val1 $drv_handle set_property "interrupt-names" $intr_names $drv_handle } hsi::utils::add_new_dts_param "${node}" "interrupts" $intr_val1 int } else { hsi::utils::add_new_dts_param "${node}" "interrupts" $intr_val int } hsi::utils::add_new_dts_param "${node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${node}" "interrupt-names" $intr_names stringlist } } } if {$connected_ipname == "axi_dma" || $connected_ipname == "axi_mcdma"} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {![string match -nocase $proctype "microblaze"]} { set eth_clk_names [get_property CONFIG.clock-names $drv_handle] set eth_clks [get_property CONFIG.clocks $drv_handle] if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 0)} { set_property "zclocks" $eth_clks $drv_handle set_drv_prop $drv_handle "zclock-names" $eth_clk_names stringlist } if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} { set eth_clks [get_property CONFIG.zclocks $drv_handle] set eth_clk_names [get_property CONFIG.zclock-names $drv_handle] } set eth_clkname_len [llength $eth_clk_names] set i 0 set dclk "" while {$i < $eth_clkname_len} { set clkname [lindex $eth_clk_names $i] for {set corenum 0} {$corenum < $num_cores} {incr corenum} { if {[string match -nocase $clkname "rx_core_clk_$corenum"]} { set core_clk_$corenum "rx_core_clk" set index_$corenum $i } if {[string match -nocase $clkname "s_axi_aclk_$corenum"]} { set axi_aclk_$corenum "s_axi_aclk" set axi_index_$corenum $i } if {[string match -nocase $clkname "dclk"]} { set dclk "dclk" set dclk_index $i } } incr i } set eth_clk_len [expr {[llength [split $eth_clks ","]]}] set clk_list [split $eth_clks ","] set clk_names [get_property CONFIG.clock-names $target_handle] set clks [get_property CONFIG.clocks $target_handle] append names "$eth_clk_names" "$clk_names" set names "" append clk "$eth_clks>," "<&$clks" set null "" set_property "clock-names" $null $drv_handle set_property "clocks" $null $drv_handle if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core== 0)} { if {[llength $dclk]} { lappend clknames "$core_clk_0" "$dclk" "$axi_aclk_0" } else { lappend clknames "$core_clk_0" "$axi_aclk_0" } append clknames1 "$clknames" "$clk_names" set index0 [lindex $clk_list $axi_index_0] regsub -all "\>||\t" $index0 {} index0 set ini0 [lindex $clk_list $index_0] regsub -all " " $ini0 "" ini0 regsub -all "\<&||\t" $ini0 {} ini0 if {[llength $dclk]} { set dclk_ini [lindex $clk_list $dclk_index] set dclk_ini [string trim $dclk_ini] if {![string match -nocase "<&*" "$dclk_ini"]} { set dclk_ini "<&$dclk_ini" } append clkvals "$ini0, $dclk_ini, $index0>, <&$clks" } else { append clkvals "$ini0, $index0>, <&$clks" } set_property "clocks" $clkvals $drv_handle set_property "clock-names" $clknames1 $drv_handle set clknames1 "" } if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 1) && [llength $eth_node]} { if {[llength $dclk]} { lappend clknames1 "$core_clk_1" "$dclk" "$axi_aclk_1" } else { lappend clknames1 "$core_clk_1" "$axi_aclk_1" } append clk_names1 "$clknames1" "$clk_names" set index1 [lindex $clk_list $axi_index_1] regsub -all "\>||\t" $index1 {} index1 set ini1 [lindex $clk_list $index_1] regsub -all " " $ini1 "" ini1 regsub -all "\<&||\t" $ini1 {} ini1 if {[llength $dclk]} { set dclk_ini1 [lindex $clk_list $dclk_index] set dclk_ini1 [string trim $dclk_ini1] if {![string match -nocase "<&*" "$dclk_ini1"]} { set dclk_ini1 "<&$dclk_ini1" } append clkvals1 "$ini1, $dclk_ini1, $index1>, <&$clks" } else { append clkvals1 "$ini1, $index1>, <&$clks" } hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals1 reference hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names1 stringlist set clk_names1 "" set clkvals1 "" } if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 2) && [llength $eth_node]} { if {[llength $dclk]} { lappend clknames2 "$core_clk_2" "$dclk" "$axi_aclk_2" } else { lappend clknames2 "$core_clk_2" "$axi_aclk_2" } append clk_names2 "$clknames2" "$clk_names" set index2 [lindex $clk_list $axi_index_2] regsub -all "\>||\t" $index2 {} index2 set ini2 [lindex $clk_list $index_2] regsub -all " " $ini2 "" ini2 regsub -all "\<&||\t" $ini2 {} ini2 if {[llength $dclk]} { set dclk_ini2 [lindex $clk_list $dclk_index] set dclk_ini2 [string trim $dclk_ini2] if {![string match -nocase "<&*" "$dclk_ini2"]} { set dclk_ini2 "<&$dclk_ini2" } append clkvals2 "$ini2, $dclk_ini2, $index2>, <&$clks" } else { append clkvals2 "$ini2, $index2>, <&$clks" } append clk_label2 $drv_handle "_" $core hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals2 reference hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names2 stringlist set clk_names2 "" set clkvals2 "" } if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 3) && [llength $eth_node]} { if {[llength $dclk]} { lappend clknames3 "$core_clk_3" "$dclk" "$axi_aclk_3" } else { lappend clknames3 "$core_clk_3" "$axi_aclk_3" } append clk_names3 "$clknames3" "$clk_names" set index3 [lindex $clk_list $axi_index_3] regsub -all "\>||\t" $index3 {} index3 set ini [lindex $clk_list $index_3] regsub -all " " $ini "" ini regsub -all "\<&||\t" $ini {} ini if {[llength $dclk]} { set dclk_ini3 [lindex $clk_list $dclk_index] set dclk_ini3 [string trim $dclk_ini3] if {![string match -nocase "<&*" "$dclk_ini3"]} { set dclk_ini3 "<&$dclk_ini3" } append clkvals3 "$ini, $dclk_ini3, $index3>, <&$clks" } else { append clkvals3 "$ini, $index3>, <&$clks" } append clk_label3 $drv_handle "_" $core hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals3 reference hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names3 stringlist set clk_names3 "" set clkvals3 "" } } } } if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core!= 0) && [llength $eth_node]} { gen_drv_prop_eth_ip $drv_handle $eth_node } gen_dev_ccf_binding $drv_handle "s_axi_aclk" } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {![string match -nocase $proctype "microblaze"]} { set null "NULL" set_property "zclock-names" $null $drv_handle set_property "zclocks" "$null" $drv_handle } } proc pcspma_phy_node {slave} { set phyaddr [get_property CONFIG.PHYADDR $slave] set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr] set phymode "phy$phyaddr" return "$phyaddr $phymode" } proc get_checksum {value} { if {[string compare -nocase $value "None"] == 0} { set value 0 } elseif {[string compare -nocase $value "Partial"] == 0} { set value 1 } else { set value 2 } return $value } proc get_memrange {value} { set values [split $value "k"] lassign $values value1 value2 return [expr $value1 * 1024] } proc get_phytype {value} { if {[string compare -nocase $value "MII"] == 0} { set value 0 } elseif {[string compare -nocase $value "GMII"] == 0} { set value 1 } elseif {[string compare -nocase $value "RGMII"] == 0} { set value 3 } elseif {[string compare -nocase $value "SGMII"] == 0} { set value 4 } else { set value 5 } return $value } proc gen_hierip_params {drv_handle} { set prop_name_list [deault_parameters $drv_handle] foreach prop_name ${prop_name_list} { ip2drv_prop $drv_handle $prop_name } } proc deault_parameters {ip_handle {dont_generate ""}} { set par_handles [get_ip_conf_prop_list $ip_handle "CONFIG.*"] set valid_prop_names {} foreach par $par_handles { regsub -all {CONFIG.} $par {} tmp_par # Ignore some parameters that are always handled specially switch -glob $tmp_par { $dont_generate - \ "Component_Name" - \ "DIFFCLK_BOARD_INTERFACE" - \ "EDK_IPTYPE" - \ "ETHERNET_BOARD_INTERFACE" - \ "Include_IO" - \ "PHY_TYPE" - \ "RXCSUM" - \ "TXCSUM" - \ "TXMEM" - \ "RXMEM" - \ "PHYADDR" - \ "C_BASEADDR" - \ "C_HIGHADDR" - \ "processor_mode" - \ "ENABLE_AVB" - \ "ENABLE_LVDS" - \ "Enable_1588_1step" - \ "Enable_1588" - \ "speed_1_2p5" - \ "lvdsclkrate" - \ "gtrefclkrate" - \ "drpclkrate" - \ "Enable_Pfc" - \ "Frame_Filter" - \ "MCAST_EXTEND" - \ "MDIO_BOARD_INTERFACE" - \ "Number_of_Table_Entries" - \ "PHYRST_BOARD_INTERFACE" - \ "RXVLAN_STRP" - \ "RXVLAN_TAG" - \ "RXVLAN_TRAN" - \ "TXVLAN_STRP" - \ "TXVLAN_TAG" - \ "TXVLAN_TRAN" - \ "SIMULATION_MODE" - \ "Statistics_Counters" - \ "Statistics_Reset" - \ "Statistics_Width" - \ "SupportLevel" - \ "TIMER_CLK_PERIOD" - \ "Timer_Format" - \ "SupportLevel" - \ "TransceiverControl" - \ "USE_BOARD_FLOW" - \ "HW_VER" { } \ default { lappend valid_prop_names $par } } } return $valid_prop_names } proc gen_phy_node args { set mdio_node [lindex $args 0] set phy_name [lindex $args 1] set phya [lindex $args 2] set drv [lindex $args 3] set phy_node [add_or_get_dt_node -l $drv$phy_name -n phy -u $phya -p $mdio_node] hsi::utils::add_new_dts_param "${phy_node}" "reg" $phya int hsi::utils::add_new_dts_param "${phy_node}" "device_type" "ethernet-phy" string return $phy_node } proc is_ethsupported_target {connected_ip} { set connected_ipname [get_property IP_NAME $connected_ip] if {$connected_ipname == "axi_dma" || $connected_ipname == "axi_fifo_mm_s" || $connected_ipname == "axi_mcdma"} { return "true" } else { return "false" } } proc get_targetip {ip} { global ddrv_handle if {[string_is_empty $ip] != 0} { return } set p2p_busifs_i [get_intf_pins -of_objects $ip -filter "TYPE==INITIATOR || TYPE==MASTER"] set target_periph "" foreach p2p_busif $p2p_busifs_i { set busif_name [string toupper [get_property NAME $p2p_busif]] set conn_busif_handle [::hsi::utils::get_connected_intf $ip $busif_name] if {[string_is_empty $conn_busif_handle] != 0} { continue } set target_periph [get_cells -of_objects $conn_busif_handle] set cell_name [get_cells -hier $target_periph] set target_name [get_property IP_NAME [get_cells -hier $target_periph]] if {$target_name == "axis_data_fifo" || $target_name == "Ethernet_filter"} { #set target_periph [get_cells -of_objects $conn_busif_handle] set master_slaves [get_intf_pins -of [get_cells -hier $cell_name]] if {[llength $master_slaves] == 0} { return } set master_intf "" foreach periph_intf $master_slaves { set prop [get_property TYPE $periph_intf] if {$prop == "INITIATOR"} { set master_intf $periph_intf } } if {[llength $master_intf] == 0} { return } set intf [get_intf_pins -of_objects $cell_name $master_intf] set intf_net [get_intf_nets -of_objects $intf] set intf_pins [::hsi::utils::get_other_intf_pin $intf_net $intf] foreach intf $intf_pins { set target_intf [get_intf_pins -of_objects $intf_net -filter "TYPE==TARGET" $intf] if {[llength $target_intf]} { set connected_ip [get_cells -of_objects $target_intf] if {[llength $connected_ip]} { set cell [get_cells -hier $connected_ip] set target_name [get_property IP_NAME [get_cells -hier $cell]] if {$target_name == "axis_data_fifo"} { return [get_targetip $connected_ip] } if {![string_is_empty $connected_ip] && [is_ethsupported_target $connected_ip] == "true"} { return $connected_ip } } else { dtg_warning "$ddrv_handle connected ip is NULL for the target intf $target_intf" } } else { dtg_warning "$ddrv_handle target interface is NULL for the intf pin $intf" } } } } return $target_periph } proc get_connectedip {intf} { global rxethmem if { [llength $intf]} { set connected_ip "" set intf_net [get_intf_nets -of_objects $intf ] if { [llength $intf_net] } { set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf] if { [llength $target_intf] } { set connected_ip [get_cells -of_objects $target_intf] if {[llength $connected_ip]} { set target_ipname [get_property IP_NAME $connected_ip] if {$target_ipname == "ila"} { return } if {$target_ipname == "axis_data_fifo"} { set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $connected_ip] if {[string_is_empty $fifo_width_bytes]} { set fifo_width_bytes 1 } set rxethmem [get_property CONFIG.FIFO_DEPTH $connected_ip] # FIFO can be other than 8 bits, and we need the rxmem in bytes set rxethmem [expr $rxethmem * $fifo_width_bytes] } else { # In 10G MAC case if the rx_stream interface is not connected to # a Stream-fifo set the rxethmem value to a default jumbo MTU size set rxethmem 9600 } } else { dtg_warning "$drv_handle connected_ip is NULL for the target_intf $target_intf" } } if {[string_is_empty $connected_ip]} { return "" } set target_ip [is_ethsupported_target $connected_ip] if { $target_ip == "true"} { return $connected_ip } else { set i 0 set retries 5 # When AXI Ethernet Configured in Non-Buf mode or In case of 10G MAC # The Ethernet MAC won't directly got connected to fifo or dma # We need to traverse through stream data fifo's and axi interconnects # Inorder to find the target IP(AXI DMA or AXI FIFO) while {$i < $retries} { set target_ip "false" set target_periph [get_targetip $connected_ip] if {[string_is_empty $target_periph] == 0} { set target_ip [is_ethsupported_target $target_periph] } if { $target_ip == "true"} { return $target_periph } set connected_ip $target_periph incr i } dtg_warning "Couldn't find a valid target_ip Please cross check hw design" } } } } proc gen_drv_prop_eth_ip {drv_handle ipname} { set prop_name_list [default_parameters $drv_handle] foreach prop_name ${prop_name_list} { ip2_prop $ipname $prop_name $drv_handle } } proc ip2_prop {ip_name ip_prop_name drv_handle} { set drv_prop_name $ip_prop_name regsub -all {CONFIG.C_} $drv_prop_name {xlnx,} drv_prop_name regsub -all {_} $drv_prop_name {-} drv_prop_name set drv_prop_name [string tolower $drv_prop_name] set value [get_property ${ip_prop_name} [get_cells -hier $drv_handle]] if {[llength $value]} { if {$value != "-1" && [llength $value] !=0} { set type "hex" if {[string equal -nocase $type "boolean"]} { if {[expr $value < 1]} { return 0 } set value "" } if {[regexp "(int|hex).*" $type match]} { regsub -all {"} $value "" value } hsi::utils::add_new_dts_param "$ip_name" "$drv_prop_name" $value $type return 0 } } } ================================================ FILE: axi_gpio/data/gpio.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver gpio OPTION supported_peripherals = (axi_gpio); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = gpio; PARAMETER name = dev_type, default = gpio, type = string; DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = gpio-controller, type = boolean; DTGPARAM name = compatible, default = "xlnx,xps-gpio-1.00.a", type = stringlist; DTGPARAM name = "#gpio-cells", default = 2, type = int; DTGPARAM name = dtg.device_type, default = gpio, type = string; END driver ================================================ FILE: axi_gpio/data/gpio.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-gpio-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set intr_present [get_property CONFIG.C_INTERRUPT_PRESENT [get_cells -hier $drv_handle]] if {[string match $intr_present "1"]} { set node [gen_peripheral_nodes $drv_handle] if {$node != 0} { hsi::utils::add_new_dts_param "${node}" "#interrupt-cells" 2 int "" } hsi::utils::add_new_property $drv_handle "interrupt-controller" boolean "" } set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_aclk" set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_aclk" stringlist } } #Workaround: There is no unique way to differentiate the gt_ctrl, so hardcoding the size #for the address 0xa4010000 to 0x40000 set ips [get_cells -hier -filter {IP_NAME == "mrmac"}] if {[llength $ips]} { set mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]] foreach mem_range $mem_ranges { set base_addr [string tolower [get_property BASE_VALUE $mem_range]] set high_addr [string tolower [get_property HIGH_VALUE $mem_range]] if {[string match -nocase $base_addr "0xa4010000"]} { set reg "0x0 0xa4010000 0x0 0x40000" hsi::utils::add_new_dts_param "${node}" "reg" $reg inthexlist } } } } ================================================ FILE: axi_iic/data/axi_iic.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_iic OPTION supported_peripherals = (axi_iic); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_iic; PARAMETER name = dev_type, default = i2c, type = string; DTGPARAM name = dtg.alias , type = reference, default = i2c; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-iic-2.00.a"; DTGPARAM name = "#address-cells", default = 1, type = int; DTGPARAM name = "#size-cells", default = 0, type = int; END driver ================================================ FILE: axi_iic/data/axi_iic.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-iic-2.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"] } { gen_dev_ccf_binding $drv_handle "s_axi_aclk" } } ================================================ FILE: axi_mcdma/data/axi_mcdma.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_mcdma OPTION supported_peripherals = (axi_mcdma); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_mcdma; DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-mcdma-1.00.a"; DTGPARAM name = "#dma-cells", type = int, default = 1; END driver ================================================ FILE: axi_mcdma/data/axi_mcdma.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-mcdma-1.00.a xlnx,eth-dma"] set_drv_prop $drv_handle compatible "$compatible" stringlist set mcdma_ip [get_cells -hier $drv_handle] set dma_count [hsi::utils::get_os_parameter_value "dma_count"] if { [llength $dma_count] == 0 } { set dma_count 0 } set axiethernetfound 0 set connected_ip [hsi::utils::get_connected_stream_ip $mcdma_ip "M_AXIS_MM2S"] if { [llength $connected_ip] } { set connected_ip_type [get_property IP_NAME $connected_ip] if { [string match -nocase $connected_ip_type axi_ethernet ] || [string match -nocase $connected_ip_type axi_ethernet_buffer ] } { set axiethernetfound 1 } } else { dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_MM2S" } set is_xxv [get_connected_ip $drv_handle "M_AXIS_MM2S"] set is_mrmac [is_mrmac_connected $drv_handle "M_AXIS_MM2S"] # if tsn ip exists in the design then it is through mcdma so changing the compatible string set tsn_inst_name [get_cells -filter {IP_NAME =~ "*tsn*"}] if { $axiethernetfound || $is_xxv == 1 || $is_mrmac == 1 || [llength $tsn_inst_name] } { set compatstring "xlnx,eth-dma" set_property compatible "$compatstring" $drv_handle } if { $axiethernetfound != 1 && $is_xxv != 1 && $is_mrmac != 1} { set ip_prop CONFIG.c_include_mm2s_dre add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth set baseaddr [get_baseaddr $mcdma_ip no_prefix] set tx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_MM2S] if { $tx_chan == 1 } { set tx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $baseaddr "MM2S" $dma_count ] set num_mm2s_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]] set intr_info [get_interrupt_info $drv_handle "MM2S"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected" } set intr_parent [get_property CONFIG.interrupt-parent $drv_handle] if {[llength $intr_parent]} { hsi::utils::add_new_dts_param "${tx_chan_node}" "interrupt-parent" $intr_parent reference } add_dma_coherent_prop $drv_handle "M_AXI_MM2S" } set rx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_S2MM] if { $rx_chan ==1 } { set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]] set rx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $rx_bassaddr "S2MM" $dma_count] set intr_info [get_interrupt_info $drv_handle "S2MM"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected" } set intr_parent [get_property CONFIG.interrupt-parent $drv_handle] if {[llength $intr_parent]} { hsi::utils::add_new_dts_param "${rx_chan_node}" "interrupt-parent" $intr_parent reference } add_dma_coherent_prop $drv_handle "M_AXI_S2MM" } } else { set ip_prop CONFIG.c_include_mm2s_dre add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean set addr_width [get_property CONFIG.c_addr_width $mcdma_ip] set inhex [format %x $addr_width] append addrwidth "/bits/ 8 <0x$inhex>" hsi::utils::add_new_dts_param "$node" "xlnx,addrwidth" $addrwidth noformating } incr dma_count hsi::utils::set_os_parameter_value "dma_count" $dma_count } proc get_interrupt_info {drv_handle chan_name} { if {[string match -nocase $chan_name "MM2S"]} { set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]] } else { set num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]] } set intr_info "" for {set i 1} {$i <= $num_channles} {incr i} { set intr_pin_name [format "%s_%s_introut" [string tolower $chan_name] ch$i] set intr1_info [get_intr_id $drv_handle $intr_pin_name] if {[string match -nocase $intr1_info "-1"]} { continue } lappend intr_info $intr1_info } if {[llength $intr_info]} { regsub -all "\{||\t" $intr_info {} intr_info regsub -all "\}||\t" $intr_info {} intr_info return $intr_info } } proc get_connected_ip {drv_handle dma_pin} { global connected_ip # Check whether dma is connected to 10G/25G MAC # currently we are handling only data fifo set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin] set valid_eth_list "xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g" if {[string_is_empty ${intf}]} { return 0 } set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf] if {[string_is_empty ${connected_ip}]} { dtg_warning "$drv_handle connected ip is NULL for the pin $intf" return 0 } set iptype [get_property IP_NAME [get_cells -hier $connected_ip]] if {[string match -nocase $iptype "axis_data_fifo"] } { # here dma connected to data fifo set dma_pin "M_AXIS" get_connected_ip $connected_ip $dma_pin } elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } { # dma connected to 10G/25G MAC, 1G or 10G return 1 } else { # dma connected via interconnects set dma_pin "M_AXIS" get_connected_ip $connected_ip $dma_pin } } proc is_mrmac_connected {drv_handle dma_pin} { set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin] if {[llength $intf]} { set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf] if {[llength $connected_ip]} { if {[string match -nocase [get_property IP_NAME $connected_ip] "axis_data_fifo"]} { set mux_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $connected_ip] "M_AXIS"] if {[llength $mux_ip]} { if {[string match -nocase [get_property IP_NAME $mux_ip] "mrmac_10g_mux"]} { set data_fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_ip] "tx_m_axis_tdata"]] set data_fifo_per [::hsi::get_cells -of_objects $data_fifo_pin] if {[string match -nocase [get_property IP_NAME $data_fifo_per] "axis_data_fifo"]} { set fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per] "m_axis_tdata"]] set mrmac_per [::hsi::get_cells -of_objects $fifo_pin] if {[string match -nocase [get_property IP_NAME $mrmac_per] "mrmac"]} { return 1 } } } } } } } } proc add_dma_channel {drv_handle parent_node xdma addr mode devid} { set modellow [string tolower $mode] set modeIndex [string index $mode 0] set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node] hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean # detection based on two property set datawidth_list "[format "CONFIG.C_%s_AXIS_%s_DATA_WIDTH" $modeIndex $mode] [format "CONFIG.C_%s_AXIS_%s_TDATA_WIDTH" $modeIndex $mode]" add_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel "xlnx,datawidth" if {[string match -nocase $mode "MM2S"]} { set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]] } else { set num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]] } hsi::utils::add_new_dts_param $dma_channel "dma-channels" $num_channles hexint return $dma_channel } proc add_dma_coherent_prop {drv_handle intf} { set ip_name [::hsi::get_cells -hier -filter "NAME==$drv_handle"] set connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf] if {[llength $connectedip] == 0} { return } set intrconnect [get_property IP_NAME [get_cells -hier $connectedip]] set num_master [get_property CONFIG.NUM_MI $connectedip] set done 0 # check whether dma connected to interconnect ip, loop until you get the # port name ACP or HP while {[string match -nocase $intrconnect "axi_interconnect"]} { # loop over number of master interfaces set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}] if {[llength $master_intf] == 0} { break } foreach interface ${master_intf} { set intf_port [hsi::utils::get_connected_intf $connectedip $interface] set intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface] if {![string_is_empty $intf_port] && [string match -nocase $intf_port "S_AXI_ACP"]} { hsi::utils::add_new_property $drv_handle "dma-coherent" boolean "" # here dma connected to ACP port set done 1 break; } if {$done} { break } } } } ================================================ FILE: axi_pcie/data/axi_pcie.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_pcie OPTION supported_peripherals = (axi_pcie axi_pcie3 qdma xdma pcie_dma_versal); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_pcie; PARAMETER name = dev_type, default = axi-pcie, type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-pcie-host-1.00.a"; DTGPARAM name = "#address-cells", default = 3, type = int; DTGPARAM name = "#size-cells", default = 2 , type = int; DTGPARAM name = "#interrupt-cells", default = 1 , type = int; DTGPARAM name = device_type, type = string, default = pci; END driver ================================================ FILE: axi_pcie/data/axi_pcie.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc set_pcie_ranges {drv_handle proctype} { if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"]} { set axibar_num [get_ip_property $drv_handle "CONFIG.axibar_num"] } else { set axibar_num [get_ip_property $drv_handle "CONFIG.AXIBAR_NUM"] } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} { set axibar_num [get_ip_property $drv_handle "CONFIG.C_AXIBAR_NUM"] } set range_type 0x02000000 # 64-bit high address. set high_64bit 0x00000000 set ranges "" for {set x 0} {$x < $axibar_num} {incr x} { if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "axi_pcie3"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"] \ } { set axi_baseaddr [get_ip_property $drv_handle [format "CONFIG.axibar_%d" $x]] set pcie_baseaddr [get_ip_property $drv_handle [format "CONFIG.axibar2pciebar_%d" $x]] set axi_highaddr [get_ip_property $drv_handle [format "CONFIG.axibar_highaddr_%d" $x]] } else { set axi_baseaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR_%d" $x]] set pcie_baseaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR2PCIEBAR_%d" $x]] set axi_highaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR_HIGHADDR_%d" $x]] } set size [expr $axi_highaddr -$axi_baseaddr + 1] # Check the size of pci memory region is 4GB or not,if # yes then split the size to MSB and LSB. if {[regexp -nocase {([0-9a-f]{9})} "$size" match]} { set size [format 0x%016x [expr $axi_highaddr -$axi_baseaddr + 1]] set low_size [string range $size 0 9] set high_size "0x[string range $size 10 17]" set size "$low_size $high_size" } else { set size [format 0x%08x [expr $axi_highaddr - $axi_baseaddr + 1]] set size "$high_64bit $size" } if {[regexp -nocase {([0-9a-f]{9})} "$axi_baseaddr" match] || [regexp -nocase {([0-9a-f]{9})} "$axi_highaddr" match]} { set range_type 0x43000000 } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} { if {[regexp -nocase {([0-9a-f]{9})} "$pcie_baseaddr" match]} { set temp $pcie_baseaddr set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set pcie_baseaddr "$low_base $high_base" } else { set pcie_baseaddr "$high_64bit $pcie_baseaddr" } if {[regexp -nocase {([0-9a-f]{9})} "$axi_baseaddr" match]} { set temp $axi_baseaddr set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set axi_baseaddr "$low_base $high_base" } else { if {[string match -nocase $proctype "microblaze"] } { set axi_baseaddr "$axi_baseaddr" } else { set axi_baseaddr "0x0 $axi_baseaddr" } } set value "<$range_type $pcie_baseaddr $axi_baseaddr $size>" } else { set value "<$range_type $high_64bit $pcie_baseaddr $axi_baseaddr $size>" } if {[string match "" $ranges]} { set ranges $value } else { append ranges ", " $value } } set_property CONFIG.ranges $ranges $drv_handle } proc get_reg_prop {highaddr baseaddr proctype} { set reg "" set size [format 0x%X [expr $highaddr -$baseaddr + 1]] if {[regexp -nocase {0x([0-9a-f]{9})} "$baseaddr" match]} { set temp $baseaddr set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set reg "$low_base $high_base 0x0 $size" } else { if {[string match -nocase $proctype "microblaze"] } { set reg "$baseaddr $size" } else { set reg "0x0 $baseaddr 0x0 $size" } } return $reg } proc set_pcie_reg {drv_handle proctype} { if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "axi_pcie3"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} { set baseaddr [get_ip_property $drv_handle CONFIG.baseaddr] set highaddr [get_ip_property $drv_handle CONFIG.highaddr] set reg [get_reg_prop $highaddr $baseaddr $proctype] if {[llength $reg]} { set_property CONFIG.reg $reg $drv_handle } } elseif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"]} { set mem_ranges [hsi::utils::get_ip_mem_ranges $drv_handle] set reg "" set reg_names "" foreach mem_range $mem_ranges { set baseaddr [string tolower [get_property BASE_VALUE $mem_range]] set highaddr [string tolower [get_property HIGH_VALUE $mem_range]] set slave_intf [string tolower [get_property SLAVE_INTERFACE $mem_range]] dtg_verbose "slave_intf:$slave_intf" set reg_prop "" if {[string match -nocase $slave_intf "s_axi_lite"]} { set reg_prop [get_reg_prop $highaddr $baseaddr $proctype] append reg_names " " "cfg" } elseif {[string match -nocase $slave_intf "s_axi_lite_csr"]} { set reg_prop [get_reg_prop $highaddr $baseaddr $proctype] append reg_names " " "breg" } if {[llength $reg_prop]} { if {![llength $reg]} { set reg "$reg_prop" } else { append reg ">, <" "$reg_prop" } } } if {[llength $reg]} { set_property CONFIG.reg $reg $drv_handle } if {[llength $reg_names]} { hsi::utils::add_new_property $drv_handle "reg-names" stringlist "$reg_names" } } else { set baseaddr [get_ip_property $drv_handle CONFIG.BASEADDR] set highaddr [get_ip_property $drv_handle CONFIG.HIGHADDR] set size [format 0x%X [expr $highaddr -$baseaddr + 1]] set_property CONFIG.reg "$baseaddr $size" $drv_handle } } proc axibar_num_workaround {drv_handle} { # this required to workaround 2014.2_web tag kernel # must have both xlnx,pciebar2axibar-0 and xlnx,pciebar2axibar-1 generated set axibar_num [get_ip_property $drv_handle "CONFIG.AXIBAR_NUM"] if {[expr $axibar_num <= 1]} { set axibar_num 2 } return $axibar_num } proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set compatible [get_comp_str $drv_handle] if {![string match -nocase $proctype "psv_cortexa72"]} { set compatible [append compatible " " "xlnx,axi-pcie-host-1.00.a"] } set_drv_prop $drv_handle compatible "$compatible" stringlist if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"]} { hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,xdma-host-3.00" set msi_rx_pin_en [get_property CONFIG.msi_rx_pin_en [get_cells -hier $drv_handle]] if {[string match -nocase $msi_rx_pin_en "true"]} { set intr_names "misc msi0 msi1" set_drv_prop $drv_handle "interrupt-names" $intr_names stringlist } } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"]} { hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,qdma-host-3.00" } set_pcie_reg $drv_handle $proctype set_pcie_ranges $drv_handle $proctype set_drv_prop $drv_handle interrupt-map-mask "0 0 0 7" intlist if {[string match -nocase $proctype "microblaze"] } { set_drv_prop $drv_handle bus-range "0x0 0xff" hexint } # Add Interrupt controller child node if {[string match -nocase $proctype "psv_cortexa72"]} { set psv_pcieintc_cnt [get_os_dev_count "psv_pci_intc_cnt"] set pcie_child_intc_node [add_or_get_dt_node -l "psv_pcie_intc_${psv_pcieintc_cnt}" -n interrupt-controller -p $node] set int_map "0 0 0 1 &psv_pcie_intc_${psv_pcieintc_cnt} 1>, <0 0 0 2 &psv_pcie_intc_${psv_pcieintc_cnt} 2>, <0 0 0 3 &psv_pcie_intc_${psv_pcieintc_cnt} 3>,\ <0 0 0 4 &psv_pcie_intc_${psv_pcieintc_cnt} 4" incr psv_pcieintc_cnt hsi::utils::set_os_parameter_value "psv_pci_intc_cnt" $psv_pcieintc_cnt set intr_names "misc msi0 msi1" set_drv_prop $drv_handle "interrupt-names" $intr_names stringlist } else { set pcieintc_cnt [get_os_dev_count "pci_intc_cnt"] set pcie_child_intc_node [add_or_get_dt_node -l "pcie_intc_${pcieintc_cnt}" -n interrupt-controller -p $node] set int_map "0 0 0 1 &pcie_intc_${pcieintc_cnt} 1>, <0 0 0 2 &pcie_intc_${pcieintc_cnt} 2>, <0 0 0 3 &pcie_intc_${pcieintc_cnt} 3>,\ <0 0 0 4 &pcie_intc_${pcieintc_cnt} 4" incr pcieintc_cnt hsi::utils::set_os_parameter_value "pci_intc_cnt" $pcieintc_cnt } set_drv_prop $drv_handle interrupt-map $int_map int hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "interrupt-controller" "" boolean hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "#address-cells" 0 int hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "#interrupt-cells" 1 int } ================================================ FILE: axi_perf_mon/data/axi_perf_mon.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_perf_mon OPTION supported_peripherals = (axi_perf_mon); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_perf_mon; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-perf-monitor"; END driver ================================================ FILE: axi_perf_mon/data/axi_perf_mon.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-perf-monitor"] set_drv_prop $drv_handle compatible "$compatible" stringlist set check_list "enable-profile enable-trace num-monitor-slots enable-event-count enable-event-log have-sampled-metric-cnt num-of-counters metric-count-width metrics-sample-count-width global-count-width metric-count-scale" foreach p ${check_list} { set ip_conf [string toupper "c_${p}"] regsub -all {\-} $ip_conf {_} ip_conf set_drv_conf_prop $drv_handle ${ip_conf} xlnx,${p} hexint } } ================================================ FILE: axi_qspi/data/axi_qspi.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_qspi OPTION supported_peripherals = (axi_quad_spi); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_qspi; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-spi-2.00.a"; DTGPARAM name = dtg.alias , default = spi; END driver ================================================ FILE: axi_qspi/data/axi_qspi.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-spi-2.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set_drv_conf_prop $drv_handle "C_NUM_SS_BITS" "xlnx,num-ss-bits" set_drv_conf_prop $drv_handle "C_NUM_SS_BITS" "num-cs" set_drv_conf_prop $drv_handle "C_NUM_TRANSFER_BITS" "bits-per-word" int set_drv_conf_prop $drv_handle "C_FIFO_DEPTH" "fifo-size" int set_drv_conf_prop $drv_handle "C_SPI_MODE" "xlnx,spi-mode" int set_drv_conf_prop $drv_handle "C_USE_STARTUP" "xlnx,startup-block" boolean } ================================================ FILE: axi_sysace/data/axi_sysace.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_sysace OPTION supported_peripherals = (axi_sysace); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_sysace; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-sysace-1.00.a"; DTGPARAM name = port-number, type = int, default = 0; END driver ================================================ FILE: axi_sysace/data/axi_sysace.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: axi_tft/data/axi_tft.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_tft OPTION supported_peripherals = (axi_tft); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_tft; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-tft-1.00.a"; END driver ================================================ FILE: axi_tft/data/axi_tft.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: axi_timebase_wdt/data/axi_timebase_wdt.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_timebase_wdt OPTION supported_peripherals = (axi_timebase_wdt); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_timebase_wdt; DTGPARAM name = dev_type, default = watchdog , type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-timebase-wdt-1.00.a"; END driver ================================================ FILE: axi_timebase_wdt/data/axi_timebase_wdt.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-timebase-wdt-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist # get bus clock frequency set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "S_AXI_ACLK"] if {![string equal $clk_freq ""]} { set_property CONFIG.clock-frequency $clk_freq $drv_handle } set_drv_conf_prop $drv_handle "C_WDT_ENABLE_ONCE" "xlnx,wdt-enable-once" set_drv_conf_prop $drv_handle "C_WDT_INTERVAL" "xlnx,wdt-interval" } ================================================ FILE: axi_traffic_gen/data/axi_traffic_gen.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_traffic_gen OPTION supported_peripherals = (axi_traffic_gen); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_traffic_gen; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-traffic-gen"; DTGPARAM name = "xlnx,device-id", type = int, default = 0; END driver ================================================ FILE: axi_traffic_gen/data/axi_traffic_gen.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-traffic-gen"] set_drv_prop $drv_handle compatible "$compatible" stringlist # the interrupt related setting is only required for AXI4 protocol only set atg_mode [get_property "CONFIG.C_ATG_MODE" [get_cells -hier $drv_handle]] if { ![string match -nocase $atg_mode "AXI4"] } { return 0 } set proc_type [get_sw_proc_prop IP_NAME] # set up interrupt-names set intr_list "irq_out err_out" set interrupts "" set interrupt_names "" foreach irq ${intr_list} { set intr_info [get_intr_id $drv_handle $irq] if { [string match -nocase $intr_info "-1"] } { if {[string match -nocase $proc_type "psv_cortexa72"] || [string match -nocase $proc_type "psx_cortexa78"]} { continue } else { error "ERROR: ${drv_handle}: $irq port is not connected" } } if { [string match -nocase $interrupt_names ""] } { if {[string match -nocase $irq "irq_out"]} { set irq "irq-out" } if {[string match -nocase $irq "err_out"]} { set irq "err-out" } set interrupt_names "$irq" set interrupts "$intr_info" } else { if {[string match -nocase $irq "irq_out"]} { set irq "irq-out" } if {[string match -nocase $irq "err_out"]} { set irq "err-out" } append interrupt_names " " "$irq" append interrupts " " "$intr_info" } } hsi::utils::add_new_property $drv_handle "interrupts" int $interrupts hsi::utils::add_new_property $drv_handle "interrupt-names" stringlist $interrupt_names } ================================================ FILE: axi_usb2_device/data/axi_usb2_device.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_usb2_device OPTION supported_peripherals = (axi_usb2_device); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_usb2_device; DTGPARAM name = compatible, type = stringlist, default = "xlnx,usb2-device-4.00.a"; END driver ================================================ FILE: axi_usb2_device/data/axi_usb2_device.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,usb2-device-4.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set include_dma [get_property CONFIG.C_INCLUDE_DMA $ip] if { $include_dma eq "1"} { set_drv_conf_prop $drv_handle C_INCLUDE_DMA xlnx,has-builtin-dma boolean } } ================================================ FILE: axi_vcu/data/axi_vcu.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_vcu OPTION supported_peripherals = (vcu); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_vcu; END driver ================================================ FILE: axi_vcu/data/axi_vcu.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # Generate properties required for vcu node set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } hsi::utils::add_new_dts_param "${node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${node}" "#size-cells" 2 int hsi::utils::add_new_dts_param "${node}" "#clock-cells" 1 int set vcu_ip [get_cells -hier $drv_handle] set baseaddr [get_baseaddr $vcu_ip no_prefix] set slcr_offset 0x40000 set logicore_offset 0x41000 set vcu_slcr_reg [format %08x [expr 0x$baseaddr + $slcr_offset]] set logicore_reg [format %08x [expr 0x$baseaddr + $logicore_offset]] set reg "0x0 0x$vcu_slcr_reg 0x0 0x1000>, <0x0 0x$logicore_reg 0x0 0x1000" set_drv_prop $drv_handle reg $reg int set intr_val [get_property CONFIG.interrupts $drv_handle] set intr_parent [get_property CONFIG.interrupt-parent $drv_handle] set clock-names "pll_ref" set clock-names [append clock-names " aclk"] hsi::utils::add_new_dts_param "${node}" "clock-names" ${clock-names} stringlist zynq_gen_pl_clk_binding $drv_handle set first_reg_name "vcu_slcr" set second_reg_name " logicore" set reg_name [append first_reg_name $second_reg_name] hsi::utils::add_new_dts_param "${node}" "reg-names" ${reg_name} stringlist hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean set compatible [get_ipdetails $drv_handle "compatible"] set vcu_comp " xlnx,vcu" set compatible [append compatible $vcu_comp] set_drv_prop $drv_handle compatible "$compatible" stringlist hsi::utils::add_new_dts_param "${node}" "compatible" ${compatible} stringlist # Generate child encoder set ver [get_ipdetails $drv_handle "ver"] set encoder_enable [get_property CONFIG.ENABLE_ENCODER [get_cells -hier $drv_handle]] if {[string match -nocase $encoder_enable "TRUE"]} { set encoder_node [add_or_get_dt_node -l "encoder" -n "al5e@$baseaddr" -p $node] set encoder_comp "al,al5e-${ver}" set encoder_comp [append encoder_comp " al,al5e"] hsi::utils::add_new_dts_param "${encoder_node}" "compatible" $encoder_comp stringlist set encoder_reg "0x0 0x$baseaddr 0x0 0x10000" hsi::utils::add_new_dts_param "${encoder_node}" "reg" $encoder_reg int hsi::utils::add_new_dts_param "${encoder_node}" "interrupts" $intr_val int hsi::utils::add_new_dts_param "${encoder_node}" "interrupt-parent" $intr_parent reference } # Fenerate child decoder set decoder_enable [get_property CONFIG.ENABLE_DECODER [get_cells -hier $drv_handle]] if {[string match -nocase $decoder_enable "TRUE"]} { set decoder_offset 0x20000 set decoder_reg [format %08x [expr 0x$baseaddr + $decoder_offset]] set decoder_node [add_or_get_dt_node -l "decoder" -n "al5d@$decoder_reg" -p $node] set decoder_comp "al,al5d-${ver}" set decoder_comp [append decoder_comp " al,al5d"] hsi::utils::add_new_dts_param "${decoder_node}" "compatible" $decoder_comp stringlist set decoder_reg "0x0 0x$decoder_reg 0x0 0x10000" hsi::utils::add_new_dts_param "${decoder_node}" "reg" $decoder_reg int hsi::utils::add_new_dts_param "${decoder_node}" "interrupts" $intr_val int hsi::utils::add_new_dts_param "${decoder_node}" "interrupt-parent" $intr_parent reference } set clknames "pll_ref aclk vcu_core_enc vcu_mcu_enc vcu_core_dec vcu_mcu_dec" overwrite_clknames $clknames $drv_handle set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] "vcu_resetn"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As in versal there is only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 0" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 0" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference } } else { dtg_warning "periph for the pin:$pin is NULL $periph...check the design" } } } } else { dtg_warning "peripheral for the pin:$pin is NULL $sink_periph...check the design" } } } proc get_ipdetails {drv_handle arg} { set slave [get_cells -hier ${drv_handle}] set vlnv [split [get_property VLNV $slave] ":"] set ver [lindex $vlnv 3] set name [lindex $vlnv 2] set ver [lindex $vlnv 3] set comp_prop "xlnx,${name}-${ver}" regsub -all {_} $comp_prop {-} comp_prop if {[string match -nocase $arg "ver"]} { return $ver } else { return $comp_prop } } ================================================ FILE: axi_vdma/data/axi_vdma.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_vdma OPTION supported_peripherals = (axi_vdma); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_vdma; PARAMETER name = dev_type, default = dma, type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-vdma-1.00.a"; DTGPARAM name = "#dma-cells", type = int, default = 1; END driver ================================================ FILE: axi_vdma/data/axi_vdma.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-vdma-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dma_ip [get_cells -hier $drv_handle] set vdma_count [hsi::utils::get_os_parameter_value "vdma_count"] if { [llength $vdma_count] == 0 } { set vdma_count 0 } # check for C_ENABLE_DEBUG parameters # C_ENABLE_DEBUG_INFO_15 - Enable S2MM Frame Count Interrupt bit # C_ENABLE_DEBUG_INFO_14 - Enable S2MM Delay Counter Interrupt bit # C_ENABLE_DEBUG_INFO_7 - Enable MM2S Frame Count Interrupt bit # C_ENABLE_DEBUG_INFO_6 - Enable MM2S Delay Counter Interrupt bit set dbg15 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_15] set dbg14 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_14] set dbg07 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_7] set dbg06 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_6] if { $dbg15 != 1 || $dbg14 != 1 || $dbg07 != 1 || $dbg06 != 1 } { puts "ERROR: Failed to generate AXI VDMA node," puts "ERROR: Essential VDMA Debug parameters for driver are not enabled in IP" return; } set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean set_drv_conf_prop $drv_handle c_num_fstores xlnx,num-fstores set_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth set baseaddr [get_baseaddr $dma_ip no_prefix] set tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S] if { $tx_chan == 1 } { set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"] set tx_chan_node [add_dma_channel $drv_handle $node "axi-vdma" $baseaddr "MM2S" $vdma_count ] set intr_info [get_intr_id $drv_handle "mm2s_introut"] #set intc [hsi::utils::get_interrupt_parent $dma_ip "mm2s_introut"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected" } } set rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM] if { $rx_chan ==1 } { set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "S_AXIS_S2MM"] set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]] set rx_chan_node [add_dma_channel $drv_handle $node "axi-vdma" $rx_bassaddr "S2MM" $vdma_count] set intr_info [get_intr_id $drv_handle "s2mm_introut"] #set intc [hsi::utils::get_interrupt_parent $dma_ip "s2mm_introut"] if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } { hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist } else { dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected" } } incr vdma_count hsi::utils::set_os_parameter_value "vdma_count" $vdma_count set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { set proc_type [get_sw_proc_prop IP_NAME] set clocknames "s_axi_lite_aclk" if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocknames " " "m_axi_mm2s_aclk" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocknames " " "m_axi_s2mm_aclk" } switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "$clocknames" set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist } } } else { generate_clk_nodes $drv_handle $tx_chan $rx_chan } } proc add_dma_channel {drv_handle parent_node xdma addr mode devid} { set ip [get_cells -hier $drv_handle] set modellow [string tolower $mode] set modeIndex [string index $mode 0] set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node] hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint if {[string match -nocase $mode "S2MM"]} { set vert_flip [hsi::utils::get_ip_param_value $ip C_ENABLE_VERT_FLIP] if {$vert_flip == 1} { hsi::utils::add_new_dts_param $dma_channel "xlnx,enable-vert-flip" "" boolean } } add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean # detection based on two property set datawidth_list "[format "CONFIG.C_%s_AXIS_%s_DATA_WIDTH" $modeIndex $mode] [format "CONFIG.C_%s_AXIS_%s_TDATA_WIDTH" $modeIndex $mode]" add_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel "xlnx,datawidth" add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_%s_GENLOCK_MODE" $mode] $dma_channel "xlnx,genlock-mode" boolean return $dma_channel } proc generate_clk_nodes {drv_handle tx_chan rx_chan} { set proc_type [get_sw_proc_prop IP_NAME] set clocknames "s_axi_lite_aclk" switch $proc_type { "ps7_cortexa9" { set clocks "clkc 15" if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocknames " " "m_axi_mm2s_aclk" append clocks "" ">, <&clkc 15" append clocks "" ">, <&clkc 15" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocknames " " "m_axi_s2mm_aclk" append clocks "" ">, <&clkc 15" append clocks "" ">, <&clkc 15" } set_drv_prop_if_empty $drv_handle "clocks" $clocks reference set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist } "psu_cortexa53" { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set dts_file [current_dt_tree] set bus_node [add_or_get_bus_node $drv_handle $dts_file] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int # create the node and assuming reg 0 is taken by cpu set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set clocks "$clk_refs" if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocknames " " "m_axi_mm2s_aclk" append clocks "" ">, <&$clk_refs" append clocks "" ">, <&$clk_refs" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocknames " " "m_axi_s2mm_aclk" append clocks "" ">, <&$clk_refs" append clocks "" ">, <&$clk_refs" } set_drv_prop_if_empty $drv_handle "clocks" $clocks reference set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist } "microblaze" { if { $tx_chan ==1 } { append clocknames " " "m_axi_mm2s_aclk" append clocknames " " "m_axi_mm2s_aclk" } if { $rx_chan ==1 } { append clocknames " " "m_axi_s2mm_aclk" append clocknames " " "m_axi_s2mm_aclk" } gen_dev_ccf_binding $drv_handle "$clocknames" set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist } default { error "Unknown arch" } } } ================================================ FILE: axi_vdu/data/axi_vdu.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_vdu OPTION supported_peripherals = (vdu); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_vdu; END driver ================================================ FILE: axi_vdu/data/axi_vdu.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc gen_reset_gpio {drv_handle node} { set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] "vdu_resetn"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$sink_periph 0 1" reference } if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As in versal there is only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 0" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 0" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference } } else { dtg_warning "periph for the pin:$pin is NULL $periph...check the design" } } } } else { dtg_warning "peripheral for the pin:$pin is NULL $sink_periph...check the design" } } } proc get_intr_width {intr_parent} { set intr_width "" if { [string match -nocase $intr_parent "gic"] } { set intr_width "3" } else { set intr_width "2" } return $intr_width } proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # Generate properties required for vdu node set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set drv_label [ps_node_mapping $drv_handle label] set default_dts [set_drv_def_dts $drv_handle] set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vdu_ip [get_cells -hier $drv_handle] set core_clk [get_property CONFIG.Actual_CORE_CLK [get_cells -hier $drv_handle]] if {[llength $core_clk]} { hsi::utils::add_new_dts_param "${node}" "xlnx,core_clk" ${core_clk} int } set mcu_clk [get_property CONFIG.Actual_MCU_CLK [get_cells -hier $drv_handle]] if {[llength $mcu_clk]} { hsi::utils::add_new_dts_param "${node}" "xlnx,mcu_clk" ${mcu_clk} int } set ref_clk [get_property CONFIG.REF_CLK [get_cells -hier $drv_handle]] if {[llength $ref_clk]} { hsi::utils::add_new_dts_param "${node}" "xlnx,ref_clk" ${ref_clk} int } gen_reset_gpio "$drv_handle" "$node" set intr_val "" set intr_parent "" set intr_names "" global drv_handlers_mapping if {[info exists drv_handlers_mapping] && [dict exists $drv_handlers_mapping $drv_handle]} { if {[dict exists $drv_handlers_mapping $drv_handle "interrupts"]} { set intr_val [dict get $drv_handlers_mapping $drv_handle "interrupts"] } if {[dict exists $drv_handlers_mapping $drv_handle "interrupt-parent"]} { set intr_parent [dict get $drv_handlers_mapping $drv_handle "interrupt-parent"] } if {[dict exists $drv_handlers_mapping $drv_handle "interrupt-names"]} { set intr_names [dict get $drv_handlers_mapping $drv_handle "interrupt-names"] } } set intrnames_List "" if {[llength $intr_names]} { set intrnames_List [regexp -inline -all -- {\S+} $intr_names] } set baseaddr [get_baseaddr $vdu_ip no_prefix] set num_decoders [get_property CONFIG.NUM_DECODER_INSTANCES [get_cells -hier $drv_handle]] set al5d_baseoffset "0x20000" set al5d_baseaddr [format %08x [expr 0x$baseaddr + $al5d_baseoffset]] set al5d_offset "0x100000" set intr_width "" for {set inst 0} {$inst < $num_decoders} {incr inst} { set al5d_node [add_or_get_dt_node -n al5d@$al5d_baseaddr -d $default_dts -p $bus_node] hsi::utils::add_new_dts_param $al5d_node "compatible" "al,al5d" string hsi::utils::add_new_dts_param $al5d_node "al,devicename" "allegroDecodeIP$inst" string hsi::utils::add_new_dts_param $al5d_node "xlnx,vdu" "$drv_label" reference hsi::utils::add_new_dts_param $al5d_node \ "/*To be filled by user depending on design else CMA region will be used */" "" comment hsi::utils::add_new_dts_param $al5d_node "/*memory-region = <&mem_reg_0> */" "" comment # check if base address is 64bit and split it as MSB and LSB if {[regexp -nocase {0x([0-9a-f]{9})} "0x$al5d_baseaddr" match]} { set temp $al5d_baseaddr set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$al5d_offset" match]} { set temp $al5d_offset set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $al5d_offset" } } else { set reg "0x0 0x$al5d_baseaddr 0x0 $al5d_offset" } hsi::utils::add_new_dts_param $al5d_node "reg" "$reg" int if {[llength $intr_parent]} { set intr_width [get_intr_width $intr_parent] hsi::utils::add_new_dts_param $al5d_node "interrupt-parent" "$intr_parent" reference } if {[llength $intr_width] && [llength $intr_val]} { set intrs_List [regexp -inline -all -- {\S+} $intr_val] set intrs_cnt [llength $intrs_List] set start "[expr {${inst} * $intr_width}]" set end "[expr {$start + $intr_width - 1}]" if { $intrs_cnt > $intr_width } { hsi::utils::add_new_dts_param $al5d_node "interrupts" "[lrange $intrs_List $start $end]" intlist } else { hsi::utils::add_new_dts_param $al5d_node "interrupts" "$intrs_List" intlist } } if {[llength $intrnames_List]} { set intrnames_cnt [llength $intrnames_List] if { $intrnames_cnt > 1 } { hsi::utils::add_new_dts_param $al5d_node "interrupt-names" "[lindex $intrnames_List $inst]" string } else { hsi::utils::add_new_dts_param $al5d_node "interrupt-names" "[lindex $intrnames_List 0]" string } } set al5d_baseaddr [format %08x [expr 0x$al5d_baseaddr + $al5d_offset]] } } ================================================ FILE: axi_xadc/data/axi_xadc.mdd ================================================ # # (C) Copyright 2015-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axi_xadc OPTION supported_peripherals = (xadc_wiz); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axi_xadc; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: axi_xadc/data/axi_xadc.tcl ================================================ # # (C) Copyright 2015-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } gen_xadc_driver_prop $drv_handle } proc gen_xadc_driver_prop {drv_handle} { gen_drv_prop_from_ip $drv_handle gen_dev_ccf_binding $drv_handle "s_axi_aclk" set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-xadc-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set adc_ip [get_cells -hier $drv_handle] set has_dma [get_property CONFIG.C_HAS_EXTERNAL_MUX $adc_ip] if {$has_dma == 0} { set has_dma_str "none" } elseif {$has_dma == 1} { set has_dma_str "single" } hsi::utils::add_new_property $drv_handle "xlnx,external-mux" string $has_dma_str if {$has_dma != 0} { set ext_mux_chan [get_property CONFIG.EXTERNAL_MUX_CHANNEL $adc_ip] if {[string match -nocase $ext_mux_chan "VP_VN"] } { set chan_nr 0 } else { for {set i 0} { $i < 16 } { incr i} { if {[string match -nocase $ext_mux_chan "VAUXP${i}_VAUXN${i}"]} { set chan_nr [expr $i + 1] } } } hsi::utils::add_new_property $drv_handle "xlnx,external-mux-channel" int $chan_nr } } ================================================ FILE: axis_switch/data/axis_switch.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver axis_switch OPTION supported_peripherals = (axis_switch); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = axis_switch; END driver ================================================ FILE: axis_switch/data/axis_switch.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] #set compatible [append compatible " " "xlnx,axis-switch"] set_drv_prop $drv_handle compatible "$compatible" stringlist set routing_mode [get_property CONFIG.ROUTING_MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,routing-mode" $routing_mode int set num_si [get_property CONFIG.NUM_SI [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,num-si-slots" $num_si int set num_mi [get_property CONFIG.NUM_MI [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,num-mi-slots" $num_mi int set ports_node [add_or_get_dt_node -n "ports" -l axis_switch_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l axis_switch_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int set count 0 set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip [get_cells -hier $drv_handle] foreach intf $master_intf { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] if {[llength $connectip]} { set outipname [get_property IP_NAME $connectip] set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_uhdsdi_audio i2s_receiver mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange" if {[lsearch -nocase $valid_mmip_list $outipname] >= 0} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] incr count } if {$count ==1} { if {[llength $connectip]} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port1$ip -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 1 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out1$ip -p $port_node] gen_axis_switch_port1_endpoint $ip "axis_switch_out1$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_switch_port1_remote_endpoint $ip $connectip$ip } } if {$count == 2} { if {[llength $connectip]} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port2$ip -u 2 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 2 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out2$ip -p $port_node] gen_axis_switch_port2_endpoint $ip "axis_switch_out2$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_switch_port2_remote_endpoint $ip $connectip$ip } } } } } ================================================ FILE: canfdps/data/canfdps.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver canfdps OPTION supported_peripherals = (psu_canfd psv_canfd psx_canfd); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = canfdps; END driver ================================================ FILE: canfdps/data/canfdps.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: canps/data/canps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver canps OPTION supported_peripherals = (ps7_can psu_can psv_can); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = canps; END driver ================================================ FILE: canps/data/canps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: cpu/data/cpu.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver cpu OPTION driver_state = ACTIVE; OPTION supported_peripherals = (microblaze); OPTION supported_os_types = (DTS); OPTION NAME = cpu; DTGPARAM name = dev_type, default = cpu , type = string; DTGPARAM name = device_type, default = cpu , type = string; DTGPARAM name = clock-frequency, type = int , default = 1000000 ; DTGPARAM name = clocks, type = int, default = &clk_cpu; DTGPARAM name = timebase-frequency, type = int , default = 1000000 ; DTGPARAM name = d-cache-baseaddr, type = hexint ; DTGPARAM name = d-cache-highaddr, type = hexint ; DTGPARAM name = d-cache-line-size, type = hexint ; DTGPARAM name = d-cache-size, type = hexint ; DTGPARAM name = i-cache-baseaddr, type = hexint ; DTGPARAM name = i-cache-highaddr, type = hexint ; DTGPARAM name = i-cache-line-size, type = hexint ; DTGPARAM name = i-cache-size, type = hexint ; DTGPARAM name = model, type = string; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: cpu/data/cpu.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ip [get_cells -hier $drv_handle] set clk "" set clkhandle [get_pins -of_objects $ip "CLK"] if { [string compare -nocase $clkhandle ""] != 0 } { set clk [get_property CLK_FREQ $clkhandle] } if { [llength $ip] } { set_property CONFIG.clock-frequency "$clk" $drv_handle set_property CONFIG.timebase-frequency "$clk" $drv_handle } set icache_size [hsi::utils::get_ip_param_value $ip "C_CACHE_BYTE_SIZE"] set isize [check_64bit $icache_size] set icache_base [hsi::utils::get_ip_param_value $ip "C_ICACHE_BASEADDR"] set ibase [check_64bit $icache_base] set icache_high [hsi::utils::get_ip_param_value $ip "C_ICACHE_HIGHADDR"] set ihigh_base [check_64bit $icache_high] set dcache_size [hsi::utils::get_ip_param_value $ip "C_DCACHE_BYTE_SIZE"] set dsize [check_64bit $dcache_size] set dcache_base [hsi::utils::get_ip_param_value $ip "C_DCACHE_BASEADDR"] set dbase [check_64bit $dcache_base] set dcache_high [hsi::utils::get_ip_param_value $ip "C_DCACHE_HIGHADDR"] set dhigh_base [check_64bit $dcache_high] set icache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip "C_ICACHE_LINE_LEN"]] set dcache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip "C_DCACHE_LINE_LEN"]] if { [llength $icache_size] != 0 } { set_property CONFIG.i-cache-baseaddr "$ibase" $drv_handle set_property CONFIG.i-cache-highaddr "$ihigh_base" $drv_handle set_property CONFIG.i-cache-size "$isize" $drv_handle set_property CONFIG.i-cache-line-size "$icache_line_size" $drv_handle } if { [llength $dcache_size] != 0 } { set_property CONFIG.d-cache-baseaddr "$dbase" $drv_handle set_property CONFIG.d-cache-highaddr "$dhigh_base" $drv_handle set_property CONFIG.d-cache-size "$dsize" $drv_handle set_property CONFIG.d-cache-line-size "$dcache_line_size" $drv_handle } set model "[get_property IP_NAME $ip],[hsi::utils::get_ip_version $ip]" set_property CONFIG.model $model $drv_handle # create root node set master_root_node [gen_root_node $drv_handle] set nodes [gen_cpu_nodes $drv_handle] } proc check_64bit {base} { if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {$low_base == 0x0} { set reg "$high_base" } else { set reg "$low_base $high_base" } } else { set reg "$base" } return $reg } ================================================ FILE: cpu_cortexa53/data/cpu_cortexa53.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver cpu_cortexa53 OPTION driver_state = ACTIVE; OPTION supported_peripherals = (psu_cortexa53); OPTION supported_os_types = (DTS); OPTION NAME = cpu_cortexa53; END driver ================================================ FILE: cpu_cortexa53/data/cpu_cortexa53.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { global dtsi_fname set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { set dtsi_fname "zynqmp/zynqmp.dtsi" } else { set dtsi_fname "zynqmp/zynqmp.dtsi" } foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # create root node set master_root_node [gen_root_node $drv_handle] set nodes [gen_cpu_nodes $drv_handle] } ================================================ FILE: cpu_cortexa72/data/cpu_cortexa72.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver cpu_cortexa72 OPTION driver_state = ACTIVE; OPTION supported_peripherals = (psv_cortexa72); OPTION supported_os_types = (DTS); OPTION NAME = cpu_cortexa72; END driver ================================================ FILE: cpu_cortexa72/data/cpu_cortexa72.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { global dtsi_fname set dtsi_fname "versal/versal.dtsi" foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # create root node set master_root_node [gen_root_node $drv_handle] set nodes [gen_cpu_nodes $drv_handle] } ================================================ FILE: cpu_cortexa78/data/cpu_cortexa78.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver cpu_cortexa78 OPTION driver_state = ACTIVE; OPTION supported_peripherals = (psx_cortexa78); OPTION supported_os_types = (DTS); OPTION NAME = cpu_cortexa78; END driver ================================================ FILE: cpu_cortexa78/data/cpu_cortexa78.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { global dtsi_fname set board_dtsi_file "" set overrides [get_property CONFIG.periph_type_overrides [get_os]] foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set board_dtsi_file [lindex $override 1] } } #TMP fix to support ipp fixed clocks if {[string match -nocase $board_dtsi_file "versal-net-ipp-rev1.9"]} { set dtsi_fname "versal-net/versal-net-ipp-rev1.9.dtsi" } else { set dtsi_fname "versal-net/versal-net.dtsi" } foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # create root node set master_root_node [gen_root_node $drv_handle] set nodes [gen_cpu_nodes $drv_handle] } ================================================ FILE: cpu_cortexa9/data/cpu_cortexa9.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver cpu_cortexa9 OPTION driver_state = ACTIVE; OPTION supported_peripherals = (ps7_cortexa9); OPTION supported_os_types = (DTS); OPTION NAME = cpu_cortexa9; END driver ================================================ FILE: cpu_cortexa9/data/cpu_cortexa9.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { global dtsi_fname set dtsi_fname "zynq/zynq-7000.dtsi" foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # create root node set master_root_node [gen_root_node $drv_handle] set nodes [gen_cpu_nodes $drv_handle] } ================================================ FILE: dccps/data/dccps.mdd ================================================ # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dccps OPTION supported_peripherals = (psu_coresight_0 psv_coresight psx_coresight); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dccps; DTGPARAM name = device_type , type = string, default = serial; DTGPARAM name = dtg.alias, type = string, default = serial; DTGPARAM name = port-number, type = int, default = 0; END driver ================================================ FILE: dccps/data/dccps.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ip [get_cells -hier $drv_handle] set def_dts [get_property CONFIG.pcw_dts [get_os]] set dcc_node [add_or_get_dt_node -n "&dcc" -d $def_dts] hsi::utils::add_new_dts_param "${dcc_node}" "status" "okay" string } ================================================ FILE: ddrcps/data/ddrcps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ddrcps OPTION supported_peripherals = (ps7_ddrc psu_ddrc psv_ddrc); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ddrcps; END driver ================================================ FILE: ddrcps/data/ddrcps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: ddrps/data/ddrps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ddrps OPTION supported_peripherals = (ps7_ddr psu_ddr psv_ddr); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ddrps; END driver ================================================ FILE: ddrps/data/ddrps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # workaround for ps7 ddrc has none zero start address proc gen_ps7_ddr_reg_property {drv_handle} { proc_called_by set regprop [ hsi::utils::get_os_parameter_value "regp"] set psu_cortexa53 "" set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "ps7_cortexa9"]} { set value 0 } else { set value [generate_secure_memory $drv_handle] } if { $value !=0} { hsi::utils::set_os_parameter_value "regp" $value set_drv_prop_if_empty $drv_handle reg $value intlist } else { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] foreach mem_handle ${ip_mem_handles} { #set base [get_property BASE_VALUE $mem_handle] set base 0x0 set high [get_property HIGH_VALUE $mem_handle] set mem_size [format 0x%x [expr {${high} - ${base} + 1}]] if {[string match -nocase $proctype "psu_cortexa53"]} { # Check if memory crossing 4GB map, then split 2GB below 32 bit limit # and remaining above 32 bit limit if { [expr {${mem_size} + ${base}}] >= [expr 0x100000000] } { set low_mem_size [expr {0x80000000 - ${base}}] set high_mem_size [expr {${mem_size} - ${low_mem_size}}] set low_mem_size [format "0x%x" ${low_mem_size}] set high_mem_size [get_high_mem_size $high_mem_size] set regval "0x0 ${base} 0x0 $low_mem_size>, <0x8 0x00000000 $high_mem_size" } else { set regval "0x0 ${base} 0x0 ${mem_size}" } } else { set regval "$base $mem_size" } if {[string_is_empty $regprop]} { set regprop $regval } else { # ensure no duplication if {![regexp ".*${regprop}.*" "$regval" matched]} { set regprop "$regval" } } } hsi::utils::set_os_parameter_value "regp" $regprop set_drv_prop_if_empty $drv_handle reg $regprop intlist } } proc generate_secure_memory {drv_handle} { set regprop [ hsi::utils::get_os_parameter_value "regp"] set psu_cortexa53 "" set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] set firstelement [lindex $ip_mem_handles 0] set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] [get_cells $firstelement]] set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] set addr_64 "0" set size_64 "0" if {[lsearch -nocase $avail_param "TRUSTZONE"] >= 0} { foreach bank ${ip_mem_handles} { set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] if {[string match -nocase $state "NonSecure"]} { set index [lsearch -start $index [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] [get_cells -hier $bank]] set base [get_property BASE_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] set high [get_property HIGH_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] set mem_size [format 0x%x [expr {${high} - ${base} + 1}]] if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set addr_64 "1" set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] } if {[regexp -nocase {0x([0-9a-f]{9})} "$mem_size" match]} { set size_64 "1" set temp $mem_size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] } if {[string match $regprop ""]} { if {[string match $addr_64 "1"] && [string match $size_64 "1"]} { set regprop "$low_base $high_base $low_size $high_size" } elseif {[string match $addr_64 "1"] && [string match $size_64 "0"]} { set regprop "${low_base} ${high_base} 0x0 ${mem_size}" } elseif {[string match $addr_64 "0"] && [string match $size_64 "1"]} { set regprop "0x0 ${base} 0x0 ${mem_size}" } else { set regprop "0x0 ${base} 0x0 ${mem_size}" } } else { if {[string match $addr_64 "1"] && [string match $size_64 "1"]} { append regprop ">, " "<$low_base $high_base $low_size $high_size" } elseif {[string match $addr_64 "1"] && [string match $size_64 "0"]} { append regprop ">, " "<${low_base} ${high_base} 0x0 ${mem_size}" } elseif {[string match $addr_64 "0"] && [string match $size_64 "1"]} { append regprop ">, " "<0x0 ${base} 0x0 ${mem_size}" } else { append regprop ">, " "<0x0 ${base} 0x0 ${mem_size}" } } } set addr_64 "0" set size_64 "0" set index [expr $index + 1] } return $regprop } else { return 0 } } proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } gen_ps7_ddr_reg_property $drv_handle set value [get_property CONFIG.reg $drv_handle] if {![string match $value ""]} { add_memory_node $drv_handle } } proc get_high_mem_size {high_mem_size} { set size "0x0 0x0" set high_mem_size [format "0x%x" ${high_mem_size}] if {[regexp -nocase {0x([0-9a-f]{9})} "$high_mem_size" match]} { set temp $high_mem_size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_mem "0x[string range $temp $rem $len]" set low_mem "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_mem [format 0x%08x $low_mem] set size "$low_mem $high_mem" } else { set size "0x0 $high_mem_size" } return $size } ================================================ FILE: ddrpsv/data/ddrpsv.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ddrpsv OPTION supported_peripherals = (axi_noc axi_noc2 noc_mc_ddr4 noc_mc_ddr5); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ddrpsv; END driver ================================================ FILE: ddrpsv/data/ddrpsv.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set master_dts [get_property CONFIG.master_dts [get_os]] set cur_dts [current_dt_tree] set master_dts_obj [get_dt_trees ${master_dts}] set_cur_working_dts $master_dts set parent_node [add_or_get_dt_node -n / -d ${master_dts}] set sw_proc [hsi::get_sw_processor] set periph [get_cells -hier $drv_handle] set interface_block_names [get_property ADDRESS_BLOCK [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph]] set Supported_channels { \ "C*_DDR_LOW0*" "C*_DDR_LOW1*" "C*_DDR_LOW2*" "C*_DDR_LOW3*" "C*_DDR_CH0*" "C*_DDR_CH1*" "C*_DDR_CH2*" "C*_DDR_CH3*" \ "HBM0_*PC0*" "HBM0_*PC1*" "HBM1_*PC0*" "HBM1_*PC1*" "HBM2_*PC0*" "HBM2_*PC1*" "HBM3_*PC0*" "HBM3_*PC1*" "HBM4_*PC0*" \ "HBM4_*PC1*" "HBM5_*PC0*" "HBM5_*PC1*" "HBM6_*PC0*" "HBM6_*PC1*" "HBM7_*PC0*" "HBM7_*PC1*" "HBM8_*PC0*" "HBM8_*PC1*" \ "HBM9_*PC0*" "HBM9_*PC1*" "HBM10_*PC0*" "HBM10_*PC1*" "HBM11_*PC0*" "HBM11_*PC1*" "HBM12_*PC0*" "HBM12_*PC1*" "HBM13_*PC0*" \ "HBM13_*PC1*" "HBM14_*PC0*" "HBM14_*PC1*" "HBM15_*PC0*" "HBM15_*PC1*" \ } set Configured_channels [dict create] set i 0 foreach block_name $interface_block_names { foreach channel $Supported_channels { if {[string match $channel $block_name]} { # Remove C* for ddr case for unique dict key regsub -all {^C[0-9]_} $block_name {} trim_blockname set memlabel "ddr" if {[string match -nocase "*HBM*" $block_name]} { set memlabel "hbm" } set base_addr [common::get_property BASE_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph] $i]] if {[dict exists $Configured_channels $memlabel] && [dict exists $Configured_channels $memlabel $trim_blockname]} { set base_addrtmp [dict get $Configured_channels $memlabel $trim_blockname "base_addr"] if {[string compare $base_addrtmp $base_addr] < 0 } { set base_addr $base_addrtmp } } set high_addr [common::get_property HIGH_VALUE [lindex [get_mem_ranges -of_objects [get_cells -hier $sw_proc] $periph] $i]] dict set Configured_channels $memlabel $trim_blockname "base_addr" $base_addr dict set Configured_channels $memlabel $trim_blockname "high_addr" $high_addr } } incr i } foreach memlabel [dict keys $Configured_channels] { set Reg_values "" foreach chkey [dict keys [dict get $Configured_channels $memlabel]] { set base_addr [dict get $Configured_channels $memlabel $chkey "base_addr"] set high_addr [dict get $Configured_channels $memlabel $chkey "high_addr"] set Reg_values [lappend Reg_values [generate_reg_property $base_addr $high_addr]] } if {[llength $Reg_values]} { set Reg_values [join $Reg_values ">, <"] generate_mem_node $Reg_values $parent_node $memlabel $drv_handle } } } proc generate_mem_node {reg_val parent_node mem_label drv_handle} { if {[llength $reg_val]} { set higheraddr [expr [lindex $reg_val 0] << 32] set loweraddr [lindex $reg_val 1] set baseaddr [format 0x%x [expr {${higheraddr} + ${loweraddr}}]] regsub -all {^0x} $baseaddr {} baseaddr set memory_node [add_or_get_dt_node -n memory -l "memory$drv_handle\_$mem_label" -u $baseaddr -p $parent_node] if {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} { set dev_type memory } if {[string_is_empty $dev_type]} {set dev_type memory} hsi::utils::add_new_dts_param "${memory_node}" "device_type" $dev_type string hsi::utils::add_new_dts_param "${memory_node}" "reg" $reg_val inthexlist } } ================================================ FILE: debug_bridge/data/debug_bridge.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver debug_bridge OPTION supported_peripherals = (debug_bridge); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = debug_bridge; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: debug_bridge/data/debug_bridge.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "generic-uio"] set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: demosaic/data/demosaic.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver demosaic OPTION supported_peripherals = (v_demosaic); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = demosaic; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: demosaic/data/demosaic.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-demosaic"] set_drv_prop $drv_handle compatible "$compatible" stringlist set s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-addr-width" $s_axi_ctrl_addr_width int set s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-data-width" $s_axi_ctrl_data_width int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-height" $max_rows int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-width" $max_cols int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] set ports_node [add_or_get_dt_node -n "ports" -l demosaic_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l demosaic_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int set outip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_video"] set outipname [get_property IP_NAME $outip] set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange" if {[lsearch -nocase $valid_mmip_list $outipname] >= 0} { foreach ip $outip { if {[llength $ip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set demonode [add_or_get_dt_node -n "endpoint" -l demo_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "demo_out$drv_handle" hsi::utils::add_new_dts_param "$demonode" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle "$ip$drv_handle" if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $ip $drv_handle } } else { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set connectip [get_connect_ip $ip $master_intf] if {[llength $connectip]} { set demonode [add_or_get_dt_node -n "endpoint" -l demo_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "demo_out$drv_handle" hsi::utils::add_new_dts_param "$demonode" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $connectip $drv_handle } } } } else { dtg_warning "$drv_handle pin m_axis_video is not connected..check your design" } } } gen_gpio_reset $drv_handle $node } proc gen_frmbuf_wr_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] gen_endpoint $drv_handle "demo_out$drv_handle" hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" demo_out$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] set proc_type [get_sw_proc_prop IP_NAME] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference } } else { dtg_warning "$drv_handle: peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle: peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: devcfg/data/devcfg.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver devcfg OPTION supported_peripherals = (ps7_dev_cfg); OPTION supported_os_types = (DTS) OPTION driver_state = ACTIVE; OPTION NAME = devcfg; END driver ================================================ FILE: devcfg/data/devcfg.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: device_tree/data/common_proc.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024-2023 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # # common procedures # # global variables global def_string zynq_soc_dt_tree bus_clk_list pl_ps_irq1 pl_ps_irq0 intrpin_width set pl_ps_irq1 0 set pl_ps_irq0 0 set intrpin_width 0 set def_string "__def_none" set zynq_soc_dt_tree "dummy.dtsi" set bus_clk_list "" global or_id global or_cnt set or_id 0 set or_cnt 0 global set drv_handlers_mapping [dict create] global set end_mappings [dict create] global set remote_mappings [dict create] global set port1_end_mappings [dict create] global set port2_end_mappings [dict create] global set port3_end_mappings [dict create] global set port4_end_mappings [dict create] global set axis_port1_remo_mappings [dict create] global set axis_port2_remo_mappings [dict create] global set axis_port3_remo_mappings [dict create] global set axis_port4_remo_mappings [dict create] global set port1_broad_end_mappings [dict create] global set port2_broad_end_mappings [dict create] global set port3_broad_end_mappings [dict create] global set port4_broad_end_mappings [dict create] global set port5_broad_end_mappings [dict create] global set port6_broad_end_mappings [dict create] global set port7_broad_end_mappings [dict create] global set broad_port1_remo_mappings [dict create] global set broad_port2_remo_mappings [dict create] global set broad_port3_remo_mappings [dict create] global set broad_port4_remo_mappings [dict create] global set broad_port5_remo_mappings [dict create] global set broad_port6_remo_mappings [dict create] global set broad_port7_remo_mappings [dict create] global set axis_switch_in_end_mappings [dict create] global set axis_switch_port1_end_mappings [dict create] global set axis_switch_port2_end_mappings [dict create] global set axis_switch_port3_end_mappings [dict create] global set axis_switch_port4_end_mappings [dict create] global set axis_switch_in_remo_mappings [dict create] global set axis_switch_port1_remo_mappings [dict create] global set axis_switch_port2_remo_mappings [dict create] global set axis_switch_port3_remo_mappings [dict create] global set axis_switch_port4_remo_mappings [dict create] proc get_clock_frequency {ip_handle portname} { set clk "" set clkhandle [get_pins -of_objects $ip_handle $portname] if {[string compare -nocase $clkhandle ""] != 0} { set width [::hsi::utils::get_port_width $clkhandle] if {$width >= 2} { set clk [get_property CLK_FREQ $clkhandle ] regsub -all ":" $clk { } clk set clklen [llength $clk] if {$clklen > 1} { set clk [lindex $clk 0] } } else { set clk [get_property CLK_FREQ $clkhandle ] } } return $clk } proc set_drv_property args { set drv_handle [lindex $args 0] set conf_prop [lindex $args 1] set value [lindex $args 2] if {[llength $value] !=0} { if {$value != "-1" && [llength $value] !=0} { set type "hexint" if {[llength $args] >= 4} { set type [lindex $args 3] if {[string equal -nocase $type "boolean"]} { if {[expr $value < 1]} { return 0 } set value "" } } # remove CONFIG. as add_new_property does not work with CONFIG. regsub -all {^CONFIG.} $conf_prop {} conf_prop hsi::utils::add_new_property $drv_handle $conf_prop $type $value } } } # set driver property based on IP property proc set_drv_conf_prop args { set drv_handle [lindex $args 0] set pram [lindex $args 1] set conf_prop [lindex $args 2] set ip [get_cells -hier $drv_handle] set value [get_property CONFIG.${pram} $ip] if {[llength $value] !=0} { regsub -all "MIO( |)" $value "" value if {$value != "-1" && [llength $value] !=0} { set type "hexint" if {[llength $args] >= 4} { set type [lindex $args 3] if {[string equal -nocase $type "boolean"]} { if {[expr $value < 1]} { return 0 } set value "" } } regsub -all {^CONFIG.} $conf_prop {} conf_prop hsi::utils::add_new_property $drv_handle $conf_prop $type $value } } } # set driver property based on other IP's property proc add_cross_property args { set src_handle [lindex $args 0] set src_prams [lindex $args 1] set dest_handle [lindex $args 2] set dest_prop [lindex $args 3] set ip [get_cells -hier $src_handle] set ipname [get_property IP_NAME $ip] foreach conf_prop $src_prams { set value [get_property ${conf_prop} $ip] if {$conf_prop == "CONFIG.processor_mode"} { set value "true" } if {$ipname == "axi_ethernet"} { set value [is_property_set $value] } if {[llength $value]} { if {$value != "-1" && [llength $value] !=0} { set type "hexint" if {[llength $args] >= 5} { set type [lindex $args 4] } if {[string equal -nocase $type "boolean"]} { if {[expr $value < 1]} { return 0 } set value "" } if {[regexp "(int|hex).*" $type match]} { regsub -all {"} $value "" value } set ipname [get_property IP_NAME [get_cells -hier $ip]] if {[string match -nocase $ipname "axi_mcdma"] && [string match -nocase $dest_prop "xlnx,include-sg"] } { set type "boolean" set value "" } if {[regexp -nocase {0x([0-9a-f]{9})} "$value" match]} { set temp $value set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set value "$low_base $high_base" } hsi::utils::add_new_property $dest_handle $dest_prop $type $value return 0 } } } } # TODO: merge to add_cross_property by detecting if dest_node is dt node or driver proc add_cross_property_to_dtnode args { set src_handle [lindex $args 0] set src_prams [lindex $args 1] set dest_node [lindex $args 2] set dest_prop [lindex $args 3] set ip [get_cells -hier $src_handle] foreach conf_prop $src_prams { set value [get_property ${conf_prop} $ip] if {[llength $value]} { if {$value != "-1" && [llength $value] !=0} { set type "hexint" if {[llength $args] >= 5} { set type [lindex $args 4] } if {[string equal -nocase $type "boolean"]} { if {[expr $value < 1]} { return 0 } set value "" } if {[regexp "(int|hex).*" $type match]} { regsub -all {"} $value "" value } hsi::utils::add_new_dts_param $dest_node $dest_prop $value $type return 0 } } } } proc get_ip_property {drv_handle parameter} { set ip [get_cells -hier $drv_handle] return [get_property ${parameter} $ip] } proc is_it_in_pl {ip} { # FIXME: This is a workaround to check if IP that's in PL however, # this is not entirely correct, it is a hack and only works for # IP_NAME that does not matches ps7_* # better detection is required # handles interrupt that coming from get_drivers only if {[llength [get_drivers $ip]] < 1} { return -1 } set ip_type [get_property IP_NAME $ip] if {![regexp "ps*" "$ip_type" match]} { return 1 } return -1 } proc get_intr_id {drv_handle intr_port_name} { set slave [get_cells -hier $drv_handle] set intr_info "" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] foreach pin ${intr_port_name} { set intc [::hsi::utils::get_interrupt_parent $drv_handle $pin] if {[string_is_empty $intc] == 1} {continue} if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { if {[llength $intc] > 1} { foreach intr_cntr $intc { if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } { set intc $intr_cntr } } } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psu_cortexa53"] && [string match -nocase $intc "axi_intc"] } { set intc [::hsi::utils::get_interrupt_parent $drv_handle $pin] } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psv_cortexa72"] && [string match -nocase $intc "axi_intc"] } { set intc [::hsi::utils::get_interrupt_parent $drv_handle $pin] } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psx_cortexa78"] && [string match -nocase $intc "axi_intc"] } { set intc [::hsi::utils::get_interrupt_parent $drv_handle $pin] } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set intr_id [get_psu_interrupt_id $drv_handle $pin] } else { set intr_id [::hsi::utils::get_interrupt_id $drv_handle $pin] } if {[string match -nocase $intr_id "-1"]} {continue} set intr_type [get_intr_type $intc $slave $pin] if {[string match -nocase $intr_type "-1"]} { continue } set cur_intr_info "" if { [string match -nocase $proctype "ps7_cortexa9"] } { if {[string match "[get_property IP_NAME $intc]" "ps7_scugic"] } { if {$intr_id > 32} { set intr_id [expr $intr_id - 32] } set cur_intr_info "0 $intr_id $intr_type" } elseif {[string match "[get_property IP_NAME $intc]" "axi_intc"] } { set cur_intr_info "$intr_id $intr_type" } } elseif {[string match -nocase $intc "psu_acpu_gic"] \ || [string match -nocase [get_property IP_NAME $intc] "psv_acpu_gic"] \ || [string match -nocase [get_property IP_NAME $intc] "psx_acpu_gic"]} { set cur_intr_info "0 $intr_id $intr_type" } else { set cur_intr_info "$intr_id $intr_type" } if {[string_is_empty $intr_info]} { set intr_info "$cur_intr_info" } else { append intr_info " " $cur_intr_info } } if {[string_is_empty $intr_info]} { set intr_info -1 } return $intr_info } proc dtg_debug msg { return puts "# [lindex [info level -1] 0] #>> $msg" } proc dtg_verbose msg { set verbose [get_property CONFIG.dt_verbose [get_os]] if {$verbose} { puts "VERBOSE: $msg" } } proc dtg_warning msg { puts "WARNING: $msg" } proc proc_called_by {} { return puts "# [lindex [info level -1] 0] #>> called by [lindex [info level -2] 0]" } proc Pop {varname {nth 0}} { upvar $varname args set r [lindex $args $nth] set args [lreplace $args $nth $nth] return $r } proc string_is_empty {input} { if {[string compare -nocase $input ""] != 0} { return 0 } return 1 } proc gen_dt_node_search_pattern args { proc_called_by # generates device tree node search pattern and return it global def_string foreach var {node_name node_label node_unit_addr} { set ${var} ${def_string} } while {[string match -* [lindex $args 0]]} { switch -glob -- [lindex $args 0] { -n* {set node_name [Pop args 1]} -l* {set node_label [Pop args 1]} -u* {set node_unit_addr [Pop args 1]} -- {Pop args ; break} default { error "gen_dt_node_search_pattern bad option - [lindex $args 0]" } } Pop args } set pattern "" # TODO: is these search patterns correct # TODO: check if pattern in the list or not if {![string equal -nocase ${node_label} ${def_string}] && \ ![string equal -nocase ${node_name} ${def_string}] && \ ![string equal -nocase ${node_unit_addr} ${def_string}]} { lappend pattern "^${node_label}:${node_name}@${node_unit_addr}$" lappend pattern "^${node_name}@${node_unit_addr}$" } if {![string equal -nocase ${node_label} ${def_string}] && \ ![string equal -nocase ${node_name} ${def_string}]} { lappend pattern "^${node_label}:${node_name}" } if {![string equal -nocase ${node_name} ${def_string}] && \ ![string equal -nocase ${node_unit_addr} ${def_string}]} { lappend pattern "^${node_name}@${node_unit_addr}$" } if {![string equal -nocase ${node_label} ${def_string}]} { lappend pattern "^&${node_label}$" lappend pattern "^${node_label}:" } return $pattern } proc set_cur_working_dts {{dts_file ""}} { # set current working device tree # return the tree object proc_called_by if {[string_is_empty ${dts_file}] == 1} { return [current_dt_tree] } set dt_idx [lsearch [get_dt_trees] ${dts_file}] if {$dt_idx >= 0} { set dt_tree_obj [current_dt_tree [lindex [get_dt_trees] $dt_idx]] } else { set dt_tree_obj [create_dt_tree -dts_file $dts_file] } return $dt_tree_obj } proc get_baseaddr {slave_ip {no_prefix ""}} { # only returns the first addr set ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave_ip]] 0] if { [string_is_empty $ip_mem_handle] } { return -1 } set addr [string tolower [get_property BASE_VALUE $ip_mem_handle]] if {![string_is_empty $no_prefix]} { regsub -all {^0x} $addr {} addr } return $addr } proc get_highaddr {slave_ip {no_prefix ""}} { set ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave_ip]] 0] set addr [string tolower [get_property HIGH_VALUE $ip_mem_handle]] if {![string_is_empty $no_prefix]} { regsub -all {^0x} $addr {} addr } return $addr } proc get_all_tree_nodes {dts_file} { # Workaround for -hier not working with -of_objects # get all the nodes presented in a dt_tree and return node list proc_called_by set cur_dts [current_dt_tree] current_dt_tree $dts_file set all_nodes [get_dt_nodes -hier] current_dt_tree $cur_dts return $all_nodes } proc check_node_in_dts {node_name dts_file_list} { # check if the node is in the device-tree file # return 1 if found # return 0 if not found proc_called_by foreach tmp_dts_file ${dts_file_list} { set dts_nodes [get_all_tree_nodes $tmp_dts_file] # TODO: better detection here foreach pattern ${node_name} { foreach node ${dts_nodes} { if {[regexp $pattern $node match]} { dtg_debug "Node $node ($pattern) found in $tmp_dts_file" return 1 } } } } return 0 } proc get_node_object {lu_node {dts_files ""} {error_out "yes"}} { # get the node object based on the args # returns the dt node object proc_called_by if [string_is_empty $dts_files] { set dts_files [get_dt_trees] } set cur_dts [current_dt_tree] foreach dts_file ${dts_files} { set dts_nodes [get_all_tree_nodes $dts_file] foreach node ${dts_nodes} { if {[regexp $lu_node $node match]} { set node_data [split $node ":"] set node_label [lindex $node_data 0] set lu_node_data [split $lu_node ":"] set lu_node_label [lindex $lu_node_data 0] if {![string match -nocase "$node_label" "$lu_node_label"]} { continue } # workaround for -hier not working with -of_objects current_dt_tree $dts_file set node_obj [get_dt_nodes -hier $node] current_dt_tree $cur_dts return $node_obj } } } if {[string_is_empty $error_out]} { return "" } else { error "Failed to find $lu_node node !!!" } } proc update_dt_parent args { # update device tree node's parent # return the node name proc_called_by global def_string set node [lindex $args 0] set new_parent [lindex $args 1] if {[llength $args] >= 3} { set dts_file [lindex $args 2] } else { set dts_file [current_dt_tree] } set node [get_node_object $node $dts_file] # Skip if node is a reference node (start with &) or amba if {[regexp "^&.*" "$node" match] || [regexp "amba_apu" "$node" match] || [regexp "amba" "$node" match]} { return $node } if {[string_is_empty $new_parent] || \ [string equal ${def_string} "$new_parent"]} { return $node } # Currently the PARENT node must within the same dt tree if {![check_node_in_dts $new_parent $dts_file]} { error "Node '$node' is not in $dts_file tree" } set cur_parent [get_property PARENT $node] # set new parent if required if {![string equal -nocase ${cur_parent} ${new_parent}] && [string_is_empty ${new_parent}] == 0} { dtg_debug "Update parent to $new_parent" set_property PARENT "${new_parent}" $node } return $node } proc get_all_dt_labels {{dts_files ""}} { # get all dt node labels set cur_dts [current_dt_tree] set labels "" if [string_is_empty $dts_files] { set dts_files [get_dt_trees] } foreach dts_file ${dts_files} { set dts_nodes [get_all_tree_nodes $dts_file] foreach node ${dts_nodes} { set node_label [get_property "NODE_LABEL" $node] if {[string_is_empty $node_label]} { continue } lappend labels $node_label } } current_dt_tree $cur_dts return $labels } proc list_remove_element {cur_list elements} { foreach e ${elements} { set rm_idx [lsearch $cur_list $e] set cur_list [lreplace $cur_list $rm_idx $rm_idx] } return $cur_list } proc update_overlay_custom_dts_include {include_file overlay_custom_dts} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set overlay_custom_dts_obj [get_dt_trees ${overlay_custom_dts}] if {[string_is_empty $overlay_custom_dts_obj] == 1} { set overlay_custom_dts_obj [set_cur_working_dts ${overlay_custom_dts}] } if {[string equal ${include_file} ${overlay_custom_dts_obj}]} { return 0 } set cur_inc_list [get_property INCLUDE_FILES $overlay_custom_dts_obj] set tmp_list [split $cur_inc_list ","] if { [lsearch $tmp_list $include_file] < 0} { if {[string_is_empty $cur_inc_list]} { set cur_inc_list $include_file } else { append cur_inc_list "," $include_file } set_property INCLUDE_FILES ${cur_inc_list} $overlay_custom_dts_obj } } proc update_system_dts_include {include_file} { # where should we get master_dts data set master_dts [get_property CONFIG.master_dts [get_os]] set cur_dts [current_dt_tree] set master_dts_obj [get_dt_trees ${master_dts}] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set overrides [get_property CONFIG.periph_type_overrides [get_os]] set dtsi_file " " foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set dtsi_file [lindex $override 1] } } if {[string_is_empty $master_dts_obj] == 1} { set master_dts_obj [set_cur_working_dts ${master_dts}] } if {[string equal ${include_file} ${master_dts_obj}]} { return 0 } set cur_inc_list [get_property INCLUDE_FILES $master_dts_obj] set tmp_list [split $cur_inc_list ","] if { [lsearch $tmp_list $include_file] < 0} { if {[string_is_empty $cur_inc_list]} { set cur_inc_list $include_file } else { if {[string match -nocase $proctype "microblaze"]} { append cur_inc_list "," $include_file set field [split $cur_inc_list ","] if {[regexp $dtsi_file $include_file match]} { } else { set cur_inc_list [lsort -decreasing $field] set cur_inc_list [join $cur_inc_list ","] } } else { # -decreasing order doens not works for versal when boardfile specified as versal-vc-p-a2197-00-... # Make sure the board file always after versal-net.dtsi or versal-net-clk-ccf.dtsi if exists set pclk_index -1 foreach pfile {"versal-clk.dtsi" "versal-net-clk-ccf.dtsi"} { set tmp_pclk_index [lsearch -exact [split $cur_inc_list ","] "$pfile"] if {$tmp_pclk_index >= 0} { set pclk_index $tmp_pclk_index } } if {[regexp $dtsi_file $include_file match] && $pclk_index >= 0} { set field [split $cur_inc_list ","] set cur_inc_list [linsert $field [expr $pclk_index + 1] $include_file] set cur_inc_list [join $cur_inc_list ","] } else { append cur_inc_list "," $include_file set field [split $cur_inc_list ","] set cur_inc_list [lsort -decreasing $field] set cur_inc_list [join $cur_inc_list ","] } } } set_property INCLUDE_FILES ${cur_inc_list} $master_dts_obj } # set dts version set dts_ver [get_property DTS_VERSION $master_dts_obj] if {[string_is_empty $dts_ver]} { set_property DTS_VERSION "/dts-v1/" $master_dts_obj } set_cur_working_dts $cur_dts } proc get_rp_rm_for_drv {drv_handle} { set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] set rmName "" foreach pr_region $pr_regions { set is_dfx [get_property CONFIG.ENABLE_DFX [hsi::get_cells -hier $pr_region]] if {[llength $is_dfx] && $is_dfx == 0} { return "" } set rmName [get_property RECONFIG_MODULE_NAME [hsi::get_cells -hier $pr_region]] set inst [hsi::current_hw_instance [hsi::get_cells -hier $pr_region]] set drv [hsi::get_cells $drv_handle] ::hsi::current_hw_instance if {[llength $drv] != 0} { append rpName "$inst" "_" "$rmName" return $rpName } } } proc get_rm_names {pr} { set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] set rm_names {} foreach pr_region $pr_regions { if {[regexp $pr $pr_region match]} { set rm_name [get_property RECONFIG_MODULE_NAME [hsi::get_cells -hier $pr_region]] } } return $rm_name } proc set_drv_def_dts {drv_handle} { # optional dts control by adding the following line in mdd file # PARAMETER name = def_dts, default = ps.dtsi, type = string; set default_dts [get_property CONFIG.def_dts $drv_handle] set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set remove_pl [get_property CONFIG.remove_pl [get_os]] set partial_image [get_property CONFIG.partial_image [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return } global bus_clk_list if {[string_is_empty $default_dts]} { if {[is_pl_ip $drv_handle]} { set RpRm [get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm "" RpRm if {[llength $RpRm]} { set default_dts "pl-partial-$RpRm.dtsi" } else { set default_dts "pl.dtsi" } } else { # PS IP, read pcw_dts property set default_dts [get_property CONFIG.pcw_dts [get_os]] } } set default_dts [set_cur_working_dts $default_dts] if {$dt_overlay } { set RpRm [get_rp_rm_for_drv $drv_handle] if {[llength $RpRm]} { if {$partial_image} { regsub -all { } $RpRm "" RpRm set partial_imag imag append RpRm1 $RpRm $partial_imag set defaultdts1 "pl-partial-$RpRm1.dtsi" set defdt [create_dt_tree -dts_file $defaultdts1] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set_property DTS_VERSION "/dts-v1/;\n/plugin/" $defdt if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set targets "fpga" } else { set targets "fpga_full" } set fpga_node [add_or_get_dt_node -n "&$targets" -d ${defdt}] set child_node1 "$fpga_node" set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr1 [lindex $pr_regions $pr] if {[regexp $pr1 $RpRm match]} { set targets "fpga_PR$pr" hsi::utils::add_new_dts_param $fpga_node target "$targets" reference break } } } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] hsi::utils::add_new_dts_param "${child_node1}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${child_node1}" "#size-cells" 2 int if {[string match -nocase $proctype "psu_cortexa53"]} { set hw_name [::hsi::get_hw_files -filter "TYPE == partial_bit"] } else { set hw_name [::hsi::get_hw_files -filter "TYPE == partial_pdi"] } if {[string match -nocase $proctype "psu_cortexa53"]} { hsi::utils::add_new_dts_param "${child_node1}" "firmware-name" "$hw_name.bin" string } else { hsi::utils::add_new_dts_param "${child_node1}" "firmware-name" "$hw_name.pdi" string } if {[string match -nocase $default_dts "pl-partial-$RpRm.dtsi"]} { set_property DTS_VERSION "/dts-v1/;\n/plugin/" $default_dts set child_node " " } } } if {![llength $RpRm] && [is_pl_ip $drv_handle]} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set default_dt "pl.dtsi" set defaultdts [set_cur_working_dts $default_dt] set master_dts [get_dt_trees ${defaultdts}] set_property DTS_VERSION "/dts-v1/;\n/plugin/" $master_dts if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set targets "fpga" } else { set targets "fpga_full" } set fpga_node [add_or_get_dt_node -n "&$targets" -d ${defaultdts}] set child_node $fpga_node set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] set classic_soc [get_property CONFIG.classic_soc [get_os]] if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr_node [add_or_get_dt_node -l "fpga_PR$pr" -n "fpga-PR$pr" -p $child_node] hsi::utils::add_new_dts_param "${pr_node}" "compatible" "fpga-region" string hsi::utils::add_new_dts_param "${pr_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${pr_node}" "#size-cells" 2 int hsi::utils::add_new_dts_param "${pr_node}" "ranges" "" boolean } } set hw_name [get_property CONFIG.firmware_name [get_os]] if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "ps7_cortexa9"]} { if {![llength $hw_name]} { set hw_name [::hsi::get_hw_files -filter "TYPE == bit"] } hsi::utils::add_new_dts_param "${child_node}" "firmware-name" "$hw_name.bin" string } set UID [get_property HW_DESIGN_ID [hsi::current_hw_design]] set PID [get_property HW_PARENT_ID [hsi::current_hw_design]] if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { if {![llength $pr_regions]} { #fpga node required to add non-reg nodes for versal{-net} hsi::utils::add_new_dts_param "${child_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${child_node}" "#size-cells" 2 int } if {![llength $hw_name]} { set hw_name [::hsi::get_hw_files -filter "TYPE == pdi"] } #external-fpga-config is required only in dfx case if {!$classic_soc && [llength $pr_regions]} { hsi::utils::add_new_dts_param "${child_node}" "external-fpga-config" "" boolean } } if {[llength $UID]} { hsi::utils::add_new_dts_param "${child_node}" "uid" $UID int } if {[llength $PID]} { hsi::utils::add_new_dts_param "${child_node}" "pid" $PID int } } } if {[is_pl_ip $drv_handle] && $dt_overlay} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set targets "fpga" } else { set targets "fpga_full" } #fpga node for new soc boot flow. set new_soc_hw_name [::hsi::get_hw_files -filter "TYPE == pl_pdi"] if {[llength $new_soc_hw_name]} { set fpga_node [add_or_get_dt_node -n "&$targets" -d ${default_dts}] set child_node "$fpga_node" #if configured firmware name exists set hw_name [get_property CONFIG.firmware_name [get_os]] if {![llength $hw_name]} { set hw_name $new_soc_hw_name } hsi::utils::add_new_dts_param "${child_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${child_node}" "#size-cells" 2 int if {[regexp ".*.pdi" $hw_name matched]} { hsi::utils::add_new_dts_param "${child_node}" "firmware-name" "$hw_name" string } else { hsi::utils::add_new_dts_param "${child_node}" "firmware-name" "$hw_name.pdi" string } } set RpRm [get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm "" RpRm set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[llength $RpRm]} { if {$partial_image} { puts "frag0 ret" } else { set default_dts "pl-partial-$RpRm.dtsi" set master_dts_obj [get_dt_trees ${default_dts}] set_property DTS_VERSION "/dts-v1/;\n/plugin/" $master_dts_obj set fpga_node [add_or_get_dt_node -n "&$targets" -d ${default_dts}] set child_node2 "$fpga_node" set classic_soc [get_property CONFIG.classic_soc [get_os]] if {$classic_soc} { hsi::utils::add_new_dts_param "${child_node2}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${child_node2}" "#size-cells" 2 int } set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr1 [lindex $pr_regions $pr] if {[regexp $pr1 $RpRm match]} { set targets "fpga_PR$pr" if {$classic_soc} { set targets "fpga" } break } } } if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr0 [lindex $pr_regions $pr] if {[regexp $pr0 $RpRm match]} { set targets "fpga_PR$pr" if {$classic_soc} { set targets "fpga" } set fpga_node [add_or_get_dt_node -n "&$targets" -d ${default_dts}] set child_node2 "$fpga_node" set intf_pins [::hsi::get_intf_pins -of_objects $pr0] foreach intf $intf_pins { set connectip [get_connected_stream_ip [get_cells -hier $pr0] $intf] if {[llength $connectip]} { if { [get_property IP_NAME $connectip] in { "dfx_decoupler" "dfx_axi_shutdown_manager" } } { hsi::utils::add_new_dts_param $child_node2 "fpga-bridges" "$connectip" reference } } } } } } if {!$classic_soc} { hsi::utils::add_new_dts_param $child_node2 "partial-fpga-config" "" boolean } set hw_name [get_property CONFIG.firmware_name [get_os]] set rprmpartial $hw_name if {![llength $hw_name]} { if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr0 [lindex $pr_regions $pr] if {[regexp $pr0 $RpRm match]} { set RmName_prop [get_rm_names $pr0] if {[string match -nocase $proctype "psu_cortexa53"]} { append pdi_name ${RmName_prop} "_" "BIT_FILE" } else { append pdi_name ${RmName_prop} "_" "PDI_FILE" } set rprmpartial [file tail [get_property $pdi_name [hsi::current_hw_design]]] if {[llength $rprmpartial]} { if {[string match -nocase $proctype "psu_cortexa53"]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial.bin" string } else { if {[regexp ".*.pdi" $rprmpartial matched]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial" string } else { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial.pdi" string } } } append uid_prop ${RmName_prop} "_" "HW_DESIGN_ID" set UID [get_property $uid_prop [hsi::current_hw_design]] append pid_prop ${RmName_prop} "_" "HW_PARENT_ID" set PID [get_property $pid_prop [hsi::current_hw_design]] if {[llength $UID]} { hsi::utils::add_new_dts_param "${child_node2}" "uid" $UID int } if {[llength $PID]} { hsi::utils::add_new_dts_param "${child_node2}" "pid" $PID int } } } } set RpRm1 [get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm1 "_" RpRm if {[llength $RpRm]} { set bitfiles_len [llength $hw_name] for {set i 0} {$i < $bitfiles_len} {incr i} { set rprm_bit_file_name [lindex $hw_name $i] if {[regexp [lindex $RpRm1 1] $rprm_bit_file_name match]} { set rprmpartial [lindex $hw_name $i] if {[string match -nocase $proctype "psu_cortexa53"]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial.bin" string } else { if {[regexp ".*.pdi" $rprmpartial matched]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial" string } else { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$rprmpartial.pdi" string } } break } } } } if {[llength $hw_name]} { puts "rprmpartial:$hw_name" if {[string match -nocase $proctype "psu_cortexa53"]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$hw_name.bin" string } else { if {[regexp ".*.pdi" $hw_name matched]} { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$hw_name" string } else { hsi::utils::add_new_dts_param "${child_node2}" "firmware-name" "$hw_name.pdi" string } } } } } else { set child_node $fpga_node set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psv_cortexa72"]} { set targets "fpga" } if {[string match -nocase $proctype "psu_cortexa53"]} { set targets "fpga_full" } set pr_regions [hsi::get_cells -hier -filter BD_TYPE==BLOCK_CONTAINER] if {[llength $pr_regions]} { set pr_len [llength $pr_regions] for {set pr 0} {$pr < $pr_len} {incr pr} { set pr_node [add_or_get_dt_node -l "fpga_PR$pr" -n "fpga-PR$pr" -p $child_node] hsi::utils::add_new_dts_param "${pr_node}" "compatible" "fpga-region" string hsi::utils::add_new_dts_param "${pr_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${pr_node}" "#size-cells" 2 int hsi::utils::add_new_dts_param "${pr_node}" "ranges" "" boolean } } } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set avail_param [list_property [get_cells -hier $zynq_periph]] if {![llength $RpRm]} { if {[lsearch -nocase $avail_param "CONFIG.PSU__USE__FABRIC__RST"] >= 0} { set val [get_property CONFIG.PSU__USE__FABRIC__RST [get_cells -hier $zynq_periph]] if {$val == 1} { if {[lsearch -nocase $avail_param "CONFIG.C_NUM_FABRIC_RESETS"] >= 0} { set val [get_property CONFIG.C_NUM_FABRIC_RESETS [get_cells -hier $zynq_periph]] switch $val { "1" { set resets "zynqmp_reset 116" } "2" { set resets "zynqmp_reset 116>,<&zynqmp_reset 117" } "3" { set resets "zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118" } "4" { set resets "zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119" } } if {$val != 0} { hsi::utils::add_new_dts_param "${child_node}" "resets" "$resets" reference } } } } } } set overlay_custom_dts [get_property CONFIG.overlay_custom_dts [get_os]] if {[llength $overlay_custom_dts] && ![llength $RpRm]} { update_overlay_custom_dts_include $default_dts $overlay_custom_dts set dts_file pl-custom.dtsi set root_node [add_or_get_dt_node -n / -d ${dts_file}] update_overlay_custom_dts_include $dts_file $overlay_custom_dts } set partial_overlay_custom_dts [get_property CONFIG.partial_overlay_custom_dts [get_os]] if {[llength $partial_overlay_custom_dts] && [llength $RpRm]} { append partial_overlay_dts $partial_overlay_custom_dts "-" $RpRm ".dts" update_overlay_custom_dts_include $default_dts $partial_overlay_dts set dts_file pl-partial-custom-$RpRm.dtsi set root_node [add_or_get_dt_node -n / -d ${dts_file}] update_overlay_custom_dts_include $dts_file $partial_overlay_dts } } else { update_system_dts_include $default_dts } return $default_dts } proc dt_node_def_checking {node_label node_name node_ua node_obj} { # check if the node_object has matching label, name and unit_address properties global def_string if {[string equal -nocase $node_label $def_string]} { set node_label "" } if {[string equal -nocase $node_ua $def_string]} { set node_ua "" } if {[string match -nocase "data_source" $node_label]} { return 1 } # ignore reference node as it does not have label and unit_addr if {![regexp "^&.*" "$node_obj" match]} { set old_label [get_property "NODE_LABEL" $node_obj] set old_name [get_property "NODE_NAME" $node_obj] set old_ua [get_property "UNIT_ADDRESS" $node_obj] set config_prop [list_property -regexp $node_obj "CONFIG.*"] if {[string_is_empty $old_ua]} { return 1 } if {![string equal -nocase -length [string length $node_label] $node_label $old_label] || \ ![string equal -nocase $node_ua $old_ua] || \ ![string equal -nocase -length [string length $node_name] $node_name $old_name]} { if {[string compare -nocase $config_prop ""]} { dtg_debug "dt_node_def_checking($node_obj): label: ${node_label} - ${old_label}, name: ${node_name} - ${old_name}, unit addr: ${node_ua} - ${old_ua}" return 0 } } } return 1 } proc add_or_get_dt_node args { # Creates the dt node or the parent node if required # return dt node proc_called_by global def_string foreach var {node_name node_label node_unit_addr parent_obj dts_file} { set ${var} ${def_string} } set auto_ref 1 set auto_ref_parent 0 set force_create 0 while {[string match -* [lindex $args 0]]} { switch -glob -- [lindex $args 0] { -force {set force_create 1} -disable_auto_ref {set auto_ref 0} -auto_ref_parent {set auto_ref_parent 1} -n* {set node_name [Pop args 1]} -l* {set node_label [Pop args 1]} -u* {set node_unit_addr [Pop args 1]} -p* {set parent_obj [Pop args 1]} -d* {set dts_file [Pop args 1]} -- {Pop args ; break} default { error "add_or_get_dt_node bad option - [lindex $args 0]" } } Pop args } # if no dts_file provided if {[string equal -nocase ${dts_file} ${def_string}]} { set dts_file [current_dt_tree] } # node_name sanity checking if {[string equal -nocase ${node_name} ${def_string}]} { error "Node name must be provided..." } # Generate unique label name to prevent issue caused by static dtsi # better way of handling this issue is required set label_list [get_all_dt_labels] # TODO: This only handle label duplication once. if multiple IP has # the same label, it will not work. Better handling required. if {[lsearch $label_list $node_label] >= 0} { set tmp_node [get_node_object ${node_label}] # rename if the node default properties differs if {[dt_node_def_checking $node_label $node_name $node_unit_addr $tmp_node] == 0} { dtg_warning "label '$node_label' found in existing tree" } } set search_pattern [gen_dt_node_search_pattern -n ${node_name} -l ${node_label} -u ${node_unit_addr}] dtg_debug "" dtg_debug "node_name: ${node_name}" dtg_debug "node_label: ${node_label}" dtg_debug "node_unit_addr: ${node_unit_addr}" dtg_debug "search_pattern: ${search_pattern}" dtg_debug "parent_obj: ${parent_obj}" dtg_debug "dts_file: ${dts_file}" # save the current working dt_tree first set cur_working_dts [current_dt_tree] # tree switch the target tree set_cur_working_dts ${dts_file} set parent_dts_file ${dts_file} # Set correct parent object # Check if the parent object in other dt_trees or not. If yes, update # parent node with reference node (&parent_obj). # Check if parent is / and see if it in the target dts file # if not /, then check if parent is created (FIXME: is right???) set tmp_dts_list [list_remove_element [get_dt_trees] ${dts_file}] set node_in_dts [check_node_in_dts ${parent_obj} ${tmp_dts_list}] if {${node_in_dts} == 1 && \ ![string equal ${parent_obj} "/" ]} { set parent_obj [get_node_object ${parent_obj} ${tmp_dts_list}] set parent_label [get_property "NODE_LABEL" $parent_obj] if {[string_is_empty $parent_label]} { set parent_label [get_property "NODE_NAME" $parent_obj] } if {[string_is_empty $parent_label]} { error "no parent node name/label" } if {[regexp "^&.*" "$parent_label" match]} { set ref_node "${parent_label}" } else { set ref_node "&${parent_label}" } set parent_ref_in_dts [check_node_in_dts "${ref_node}" ${dts_file}] if {${parent_ref_in_dts} != 1} { if {$auto_ref_parent} { set_cur_working_dts ${dts_file} set parent_obj [create_dt_node -n "${ref_node}"] } } else { set parent_obj [get_node_object ${ref_node} ${dts_file}] } } # if dt node in the target dts file # get the nodes in the current dts file set dts_nodes [get_all_tree_nodes $dts_file] foreach pattern ${search_pattern} { foreach node ${dts_nodes} { if {[regexp $pattern $node match]} { if {[dt_node_def_checking $node_label $node_name $node_unit_addr $node] == 0} { dtg_warning "$pattern :: $node_label : $node_name @ $node_unit_addr, is differ to the node object $node" } set node [update_dt_parent ${node} ${parent_obj} ${dts_file}] set_cur_working_dts ${cur_working_dts} return $node } } } # clean up required # special search pattern for name only node set_cur_working_dts ${dts_file} foreach pattern "^${node_name}$" { foreach node ${dts_nodes} { # As there was cpu timer node already in dtsi file skipping to add ttc timer # to pcw.dtsi even if ip available. This check will skip that. if {[regexp $pattern $node match] && ![string match -nocase ${node_name} "timer"]} { set_cur_working_dts ${dts_file} set node [update_dt_parent ${node} ${parent_obj} ${dts_file}] set_cur_working_dts ${cur_working_dts} return $node } } } # if dt node in other target dts files # create a reference node if required set found_node 0 set tmp_dts_list [list_remove_element [get_dt_trees] ${dts_file}] foreach tmp_dts_file ${tmp_dts_list} { set dts_nodes [get_all_tree_nodes $tmp_dts_file] # TODO: better detection here foreach pattern ${search_pattern} { foreach node ${dts_nodes} { if {[regexp $pattern $node match]} { if {[string match -nocase $node "port@0"] || [string match -nocase $node "port@1"] || [string match -nocase $node "port@2"]} { continue } # create reference node set found_node 1 set found_node_obj [get_node_object ${node} $tmp_dts_file] break } } } } if {$found_node == 1 && $force_create == 0} { if {$auto_ref == 0} { # return the object found on other dts files set_cur_working_dts ${cur_working_dts} return $found_node_obj } dtg_debug "INFO: Found node and create it as reference node &${node_label}" if {[string equal -nocase ${node_label} ${def_string}]} { error "Unable to create reference node as reference label is not provided" } set node [create_dt_node -n "&${node_label}"] set_cur_working_dts ${cur_working_dts} return $node } # Others - create the dt node set cmd "" if {![string equal -nocase ${node_name} ${def_string}]} { set cmd "${cmd} -name ${node_name}" } if {![string equal -nocase ${node_label} ${def_string}]} { if {[regexp "pl-partial-.*.dtsi" $parent_dts_file match] && \ [get_property CONFIG.no_labels [get_os]]} { # CONFIG.no_lables set to true and RpRm dtsi. # skip adding labels for Partial dt files. set cmd "${cmd}" } else { set cmd "${cmd} -label ${node_label}" } } if {![string equal -nocase ${node_unit_addr} ${def_string}]} { set cmd "${cmd} -unit_addr ${node_unit_addr}" } if {![string equal -nocase ${parent_obj} ${def_string}] && \ ![string_is_empty ${parent_obj}]} { # temp solution for getting the right node object #set cmd "${cmd} -objects \[get_node_object ${parent_obj} $dts_file\]" #report_property [get_node_object ${parent_obj} $dts_file] set cmd "${cmd} -objects \[get_node_object ${parent_obj} $parent_dts_file\]" } dtg_debug "create node command: create_dt_node ${cmd}" # FIXME: create_dt_node fail detection here set node [eval "create_dt_node ${cmd}"] set_cur_working_dts ${cur_working_dts} return $node } proc is_pl_ip {ip_inst} { # check if the IP is a soft IP (not PS7) # return 1 if it is soft ip # return 0 if not set ip_obj [get_cells -hier $ip_inst] if {[llength [get_cells -hier $ip_inst]] < 1} { return 0 } set ip_name [get_property IP_NAME $ip_obj] set nochk_list "ai_engine noc_mc_ddr4" if {[lsearch $nochk_list $ip_name] >= 0} { return 1 } if {[catch {set proplist [list_property [hsi::get_cells -hier $ip_inst]]} msg]} { } else { if {[lsearch -nocase $proplist "IS_PL"] >= 0} { set prop [get_property IS_PL [hsi::get_cells -hier $ip_inst]] if {$prop} { return 1 } else { return 0 } } } set ip_name [get_property IP_NAME $ip_obj] if {![regexp "ps._*" "$ip_name" match]} { return 1 } return 0 } proc is_ps_ip {ip_inst} { # check if the IP is a soft IP (not PS7) # return 1 if it is soft ip # return 0 if not set ip_obj [hsi::get_cells -hier $ip_inst] if {[catch {set proplist [list_property [hsi::get_cells -hier $ip_inst]]} msg]} { } else { if {[lsearch -nocase $proplist "IS_PL"] >= 0} { set prop [get_property IS_PL [hsi::get_cells -hier $ip_inst]] if {$prop} { return 0 } } } if {[llength [hsi::get_cells -hier $ip_inst]] < 1} { return 0 } set ip_name [get_property IP_NAME $ip_obj] if {[string match -nocase $ip_name "axi_noc"] || [string match -nocase $ip_name "axi_noc2"]} { return 0 } if {[regexp "ps._*" "$ip_name" match]} { return 1 } return 0 } proc get_node_name {drv_handle} { # FIXME: handle node that is not an ip # what about it is a bus node set ip [get_cells -hier $drv_handle] # node that is not a ip if {[string_is_empty $ip]} { error "$drv_handle is not a valid IP" } set unit_addr [get_baseaddr ${ip}] set dev_type [get_property CONFIG.dev_type $drv_handle] if {[string_is_empty $dev_type] == 1} { set dev_type $drv_handle } set dt_node [add_or_get_dt_node -n ${dev_type} -l ${drv_handle} -u ${unit_addr}] return $dt_node } proc get_driver_conf_list {drv_handle} { # Assuming the driver property starts with CONFIG. # Returns all the property name that should be add to the node set dts_conf_list "" # handle no CONFIG parameter if {[catch {set rt [report_property -return_string -regexp $drv_handle "CONFIG\\..*"]} msg]} { return "" } foreach line [split $rt "\n"] { regsub -all {\s+} $line { } line if {[regexp "CONFIG\\..*\\.dts(i|)" $line matched]} { continue } if {[regexp "CONFIG\\..*" $line matched]} { lappend dts_conf_list [lindex [split $line " "] 0] } } # Remove config based properties # currently it is not possible to different by type: Pending on HSI implementation # this is currently hard coded to remove CONFIG.def_dts CONFIG.dev_type CONFIG.dtg.alias CONFIG.dtg.ip_params set dts_conf_list [list_remove_element $dts_conf_list "CONFIG.def_dts CONFIG.dev_type CONFIG.dtg.alias CONFIG.dtg.ip_params"] return $dts_conf_list } proc add_driver_prop {drv_handle dt_node prop} { # driver property to DT node set value [get_property ${prop} $drv_handle] if {[string_is_empty ${prop}] != 0} { return -1 } set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return } regsub -all {CONFIG.} $prop {} prop set conf_prop [lindex [get_comp_params ${prop} $drv_handle] 0 ] if {[string_is_empty ${conf_prop}] == 0} { set type [lindex [get_property CONFIG.TYPE $conf_prop] 0] } else { error "Unable to add the $prop property for $drv_handle due to missing valid type" } set ipname [get_property IP_NAME [get_cells -hier $drv_handle]] if {[string match -nocase $ipname "axi_mcdma"] && [string match -nocase $conf_prop "xlnx,sg-include-stscntrl-strm"]&& [string match -nocase $type "boolean"]} { set type "hexint" } dtg_debug "${dt_node} - ${prop} - ${value} - ${type}" # only boolean allows empty string if {[string_is_empty ${value}] == 1 && ![regexp {boolean*} ${type} matched]} { dtg_warning "Only boolean type can have empty value. Fail to add driver($drv_handle) property($prop) type($type) value($value)" dtg_warning "Please add the property manually" return 1 } # TODO: sanity check is missing hsi::utils::add_new_dts_param "${dt_node}" "${prop}" "${value}" "${type}" } proc create_dt_tree_from_dts_file {} { global def_string dtsi_fname set kernel_dtsi "" set mainline_dtsi "" set kernel_ver [get_property CONFIG.kernel_version [get_os]] set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { foreach i [get_sw_cores device_tree] { set mainline_dtsi [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${mainline_ker}/${dtsi_fname}"] if {[file exists $mainline_dtsi]} { foreach file [glob [file normalize [file dirname ${mainline_dtsi}]/*]] { # NOTE: ./ works only if we did not change our directory file copy -force $file ./ } break } } } else { foreach i [get_sw_cores device_tree] { set kernel_dtsi [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${kernel_ver}/${dtsi_fname}"] if {[file exists $kernel_dtsi]} { foreach file [glob [file normalize [file dirname ${kernel_dtsi}]/*]] { # NOTE: ./ works only if we did not change our directory file copy -force $file ./ } break } } if {![file exists $kernel_dtsi] || [string_is_empty $kernel_dtsi]} { error "Unable to find the dts file $kernel_dtsi" } } global zynq_soc_dt_tree set default_dts [create_dt_tree -dts_file $zynq_soc_dt_tree] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { set fp [open $mainline_dtsi r] set file_data [read $fp] set data [split $file_data "\n"] } else { set fp [open $kernel_dtsi r] set file_data [read $fp] set data [split $file_data "\n"] } set node_level -1 foreach line $data { set node_start_regexp "\{(\\s+|\\s|)$" set node_end_regexp "\}(\\s+|\\s|);(\\s+|\\s|)$" if {[regexp $node_start_regexp $line matched]} { regsub -all "\{| |\t" $line {} line incr node_level set cur_node [line_to_node $line $node_level $default_dts] } elseif {[regexp $node_end_regexp $line matched]} { set node_level [expr "$node_level - 1"] } # TODO (MAYBE): convert every property into dt node set status_regexp "status(|\\s+)=" set value "" if {[regexp $status_regexp $line matched]} { regsub -all "\{| |\t|;|\"" $line {} line set line_data [split $line "="] set value [lindex $line_data 1] hsi::utils::add_new_dts_param "${cur_node}" "status" $value string } set status_regexp "compatible(|\\s+)=" set value "" if {[regexp $status_regexp $line matched]} { regsub -all "\{| |\t|;|\"" $line {} line set line_data [split $line "="] set value [lindex $line_data 1] hsi::utils::add_new_dts_param "${cur_node}" "compatible" $value stringlist } } } proc line_to_node {line node_level default_dts} { # TODO: make dt_node_dict as global global dt_node_dict global def_string regsub -all "\{| |\t" $line {} line set parent_node $def_string set node_label $def_string set node_name $def_string set node_unit_addr $def_string set node_data [split $line ":"] set node_data_size [llength $node_data] if {$node_data_size == 2} { set node_label [lindex $node_data 0] set tmp_data [split [lindex $node_data 1] "@"] set node_name [lindex $tmp_data 0] if {[llength $tmp_data] >= 2} { set node_unit_addr [lindex $tmp_data 1] } } elseif {$node_data_size == 1} { set node_name [lindex $node_data 0] } else { error "invalid node found - $line" } if {$node_level > 0} { set parent_node [dict get $dt_node_dict [expr $node_level - 1] parent_node] } set cur_node [add_or_get_dt_node -n ${node_name} -l ${node_label} -u ${node_unit_addr} -d ${default_dts} -p ${parent_node}] dict set dt_node_dict $node_level parent_node $cur_node return $cur_node } proc gen_ps7_mapping {} { # TODO: check if it is target cpu is cortex a9 # TODO: remove def_ps7_mapping set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set def_ps_mapping [dict create] if {[string match -nocase $proctype "psv_cortexa72"]} { dict set def_ps_mapping f9000000 label gic dict set def_ps_mapping fd4b0000 label gpu dict set def_ps_mapping ffa80000 label adma0 dict set def_ps_mapping ffa90000 label adma1 dict set def_ps_mapping ffaa0000 label adma2 dict set def_ps_mapping ffab0000 label adma3 dict set def_ps_mapping ffac0000 label adma4 dict set def_ps_mapping ffad0000 label adma5 dict set def_ps_mapping ffae0000 label adma6 dict set def_ps_mapping ffaf0000 label adma7 dict set def_ps_mapping ff100000 label nand0 dict set def_ps_mapping ff0c0000 label gem0 dict set def_ps_mapping ff0d0000 label gem1 dict set def_ps_mapping ff0b0000 label gpio dict set def_ps_mapping ff020000 label i2c0 dict set def_ps_mapping ff030000 label i2c1 dict set def_ps_mapping f06f0000 label qspi dict set def_ps_mapping f1100000 label rtc dict set def_ps_mapping fd0c0000 label sata dict set def_ps_mapping f0760000 label sdhci0 dict set def_ps_mapping f0770000 label sdhci1 dict set def_ps_mapping fd800000 label smmu dict set def_ps_mapping ff040000 label spi0 dict set def_ps_mapping ff050000 label spi1 dict set def_ps_mapping ff0e0000 label ttc0 dict set def_ps_mapping ff0f0000 label ttc1 dict set def_ps_mapping ff100000 label ttc2 dict set def_ps_mapping ff110000 label ttc3 dict set def_ps_mapping ff000000 label uart0 dict set def_ps_mapping ff010000 label uart1 dict set def_ps_mapping fe200000 label usb0 dict set def_ps_mapping ff120000 label watchdog0 dict set def_ps_mapping fe5f0000 label dpdma dict set def_ps_mapping fd0e0000 label pcie dict set def_ps_mapping fca10000 label cpm_pciea dict set def_ps_mapping fcdd0000 label cpm5_pcie dict set def_ps_mapping ff060000 label can0 dict set def_ps_mapping ff070000 label can1 } elseif {[string match -nocase $proctype "psx_cortexa78"]} { dict set def_ps_mapping e2000000 label gic dict set def_ps_mapping ebd00000 label adma0 dict set def_ps_mapping ebd10000 label adma1 dict set def_ps_mapping ebd20000 label adma2 dict set def_ps_mapping ebd30000 label adma3 dict set def_ps_mapping ebd40000 label adma4 dict set def_ps_mapping ebd50000 label adma5 dict set def_ps_mapping ebd60000 label adma6 dict set def_ps_mapping ebd70000 label adma7 dict set def_ps_mapping f1980000 label can0 dict set def_ps_mapping f1990000 label can1 dict set def_ps_mapping f19e0000 label gem0 dict set def_ps_mapping f19f0000 label gem1 dict set def_ps_mapping f19d0000 label gpio0 dict set def_ps_mapping f1020000 label gpio1 dict set def_ps_mapping f1940000 label i2c0 dict set def_ps_mapping f1950000 label i2c1 dict set def_ps_mapping f1948000 label i3c0 dict set def_ps_mapping f1958000 label i3c1 dict set def_ps_mapping f1010000 label ospi dict set def_ps_mapping f1030000 label qspi dict set def_ps_mapping f12a0000 label rtc dict set def_ps_mapping f1040000 label sdhci0 dict set def_ps_mapping f1050000 label sdhci1 dict set def_ps_mapping f1920000 label serial0 dict set def_ps_mapping f1930000 label serial1 dict set def_ps_mapping ec000000 label smmu dict set def_ps_mapping f1960000 label spi0 dict set def_ps_mapping f1970000 label spi1 dict set def_ps_mapping f1dc0000 label ttc0 dict set def_ps_mapping f1dd0000 label ttc1 dict set def_ps_mapping f1de0000 label ttc2 dict set def_ps_mapping f1df0000 label ttc3 dict set def_ps_mapping f1e00000 label usb0 dict set def_ps_mapping f1e10000 label usb1 dict set def_ps_mapping ecc10000 label wwdt0 dict set def_ps_mapping ecd10000 label wwdt1 dict set def_ps_mapping ece10000 label wwdt2 dict set def_ps_mapping ecf10000 label wwdt3 } elseif {[string match -nocase $proctype "psu_cortexa53"]} { dict set def_ps_mapping f9010000 label gic dict set def_ps_mapping ff060000 label can0 dict set def_ps_mapping ff070000 label can1 dict set def_ps_mapping fd500000 label gdma0 dict set def_ps_mapping fd510000 label gdma1 dict set def_ps_mapping fd520000 label gdma2 dict set def_ps_mapping fd530000 label gdma3 dict set def_ps_mapping fd540000 label gdma4 dict set def_ps_mapping fd550000 label gdma5 dict set def_ps_mapping fd560000 label gdma6 dict set def_ps_mapping fd570000 label gdma7 dict set def_ps_mapping fd4b0000 label gpu dict set def_ps_mapping ffa80000 label adma0 dict set def_ps_mapping ffa90000 label adma0 dict set def_ps_mapping ffaa0000 label adma2 dict set def_ps_mapping ffab0000 label adma3 dict set def_ps_mapping ffac0000 label adma4 dict set def_ps_mapping ffad0000 label adma5 dict set def_ps_mapping ffae0000 label adma6 dict set def_ps_mapping ffaf0000 label adma7 dict set def_ps_mapping ff100000 label nand0 dict set def_ps_mapping ff0b0000 label gem0 dict set def_ps_mapping ff0c0000 label gem1 dict set def_ps_mapping ff0d0000 label gem2 dict set def_ps_mapping ff0e0000 label gem3 dict set def_ps_mapping ff0a0000 label gpio dict set def_ps_mapping ff020000 label i2c0 dict set def_ps_mapping ff030000 label i2c1 dict set def_ps_mapping ff0f0000 label qspi dict set def_ps_mapping ffa60000 label rtc dict set def_ps_mapping fd0c0000 label sata dict set def_ps_mapping ff160000 label sdhci0 dict set def_ps_mapping ff170000 label sdhci1 dict set def_ps_mapping fd800000 label smmu dict set def_ps_mapping ff040000 label spi0 dict set def_ps_mapping ff050000 label spi1 dict set def_ps_mapping ff110000 label ttc0 dict set def_ps_mapping ff120000 label ttc1 dict set def_ps_mapping ff130000 label ttc2 dict set def_ps_mapping ff140000 label ttc3 dict set def_ps_mapping ff000000 label uart0 dict set def_ps_mapping ff010000 label uart1 dict set def_ps_mapping fe200000 label usb0 dict set def_ps_mapping fe300000 label usb1 dict set def_ps_mapping fd4d0000 label watchdog0 dict set def_ps_mapping 43c00000 label dp dict set def_ps_mapping 43c0a000 label dpsub dict set def_ps_mapping fd4c0000 label dpdma dict set def_ps_mapping fd0e0000 label pcie } else { dict set def_ps_mapping f8891000 label pmu dict set def_ps_mapping f8007100 label adc dict set def_ps_mapping e0008000 label can0 dict set def_ps_mapping e0009000 label can1 dict set def_ps_mapping e000a000 label gpio0 dict set def_ps_mapping e0004000 label i2c0 dict set def_ps_mapping e0005000 label i2c1 dict set def_ps_mapping f8f01000 label intc dict set def_ps_mapping f8f00100 label intc dict set def_ps_mapping f8f02000 label L2 dict set def_ps_mapping f8006000 label memory-controller dict set def_ps_mapping f800c000 label ocmc dict set def_ps_mapping e0000000 label uart0 dict set def_ps_mapping e0001000 label uart1 dict set def_ps_mapping e0006000 label spi0 dict set def_ps_mapping e0007000 label spi1 dict set def_ps_mapping e000d000 label qspi dict set def_ps_mapping e000e000 label smcc dict set def_ps_mapping e1000000 label nand0 dict set def_ps_mapping e2000000 label nor dict set def_ps_mapping e000b000 label gem0 dict set def_ps_mapping e000c000 label gem1 dict set def_ps_mapping e0100000 label sdhci0 dict set def_ps_mapping e0101000 label sdhci1 dict set def_ps_mapping f8000000 label slcr dict set def_ps_mapping f8003000 label dmac_s dict set def_ps_mapping f8007000 label devcfg dict set def_ps_mapping f8f00200 label global_timer dict set def_ps_mapping f8001000 label ttc0 dict set def_ps_mapping f8002000 label ttc1 dict set def_ps_mapping f8f00600 label scutimer dict set def_ps_mapping f8005000 label watchdog0 dict set def_ps_mapping f8f00620 label scuwatchdog dict set def_ps_mapping e0002000 label usb0 dict set def_ps_mapping e0003000 label usb1 } set ps_mapping [dict create] global zynq_soc_dt_tree if {[lsearch [get_dt_trees] $zynq_soc_dt_tree] >= 0} { # get nodes under bus foreach node [get_all_tree_nodes $zynq_soc_dt_tree] { # only care about the device with parent ambe set parent [get_property PARENT $node] set ignore_parent_list {(/|cpu)} if {[regexp $ignore_parent_list $parent matched]} { continue } set unit_addr [get_property UNIT_ADDRESS $node] if {[string length $unit_addr] <= 1} { set unit_addr "" } set node_name [get_property NODE_NAME $node] set node_label [get_property NODE_LABEL $node] if {[catch {set status_prop [get_property CONFIG.status $node]} msg]} { set status_prop "enable" } if {[string_is_empty $node_label] || \ [string_is_empty $unit_addr]} { continue } dict set ps_mapping $unit_addr label $node_label dict set ps_mapping $unit_addr name $node_name dict set ps_mapping $unit_addr status $status_prop } } if {[string_is_empty $ps_mapping]} { return $def_ps_mapping } else { return $ps_mapping } } proc ps_node_mapping {ip_name prop} { if {[is_ps_ip [get_drivers $ip_name]]} { set unit_addr [get_ps_node_unit_addr $ip_name] if {$unit_addr == -1} {return $ip_name} set ps7_mapping [gen_ps7_mapping] if {[catch {set tmp [dict get $ps7_mapping $unit_addr $prop]} msg]} { continue } return $tmp } return $ip_name } proc get_ps_node_unit_addr {ip_name {prop "label"}} { set ip [get_cells -hier $ip_name] set ip_mem_handle [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]] # loop through the base addresses: workaround for intc foreach handler ${ip_mem_handle} { set unit_addr [string tolower [get_property BASE_VALUE $handler]] regsub -all {^0x} $unit_addr {} unit_addr set ps7_mapping [gen_ps7_mapping] if {[is_ps_ip [get_drivers $ip_name]]} { if {[catch {set tmp [dict get $ps7_mapping $unit_addr $prop]} msg]} { continue } return $unit_addr } } return -1 } proc remove_empty_reference_node {} { # check for ps_ips global zynq_soc_dt_tree set dts_files [list_remove_element [get_dt_trees] $zynq_soc_dt_tree] foreach dts_file $dts_files { set_cur_working_dts $dts_file foreach node [get_all_tree_nodes $dts_file] { if {[regexp "^&.*" $node matched]} { # check if it has child node set child_nodes [get_dt_nodes -of_objects $node] if {![string_is_empty $child_nodes]} { continue } set prop_list [list_property -regexp $node "CONFIG.*"] if {[string_is_empty $prop_list]} { dtg_debug "removing $node" delete_objs $node } } } } } proc add_dts_header {dts_file str_add} { set cur_dts [current_dt_tree] set dts_obj [set_cur_working_dts ${dts_file}] set header [get_property HEADER $dts_obj] append header "\n" $str_add set_property HEADER $header $dts_obj set_cur_working_dts $cur_dts } proc gen_fixed_factor_clk_node {misc_clk_node clk_freq} { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set pl0_clk_val [get_property CONFIG.C_PL_CLK0_BUF [get_cells -hier $zynq_periph]] set pl1_clk_val [get_property CONFIG.C_PL_CLK1_BUF [get_cells -hier $zynq_periph]] set pl2_clk_val [get_property CONFIG.C_PL_CLK2_BUF [get_cells -hier $zynq_periph]] set pl3_clk_val [get_property CONFIG.C_PL_CLK3_BUF [get_cells -hier $zynq_periph]] set parent_freq "" set div "" set mult "" if {[string match -nocase $pl0_clk_val "true"]} { set parent_freq [get_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] set parent_freq [expr $parent_freq * 1000000] set clock_name "zynqmp_clk 71" } elseif {[string match -nocase $pl1_clk_val "true"]} { set parent_freq [get_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] set parent_freq [expr $parent_freq * 1000000] set clock_name "zynqmp_clk 72" } elseif {[string match -nocase $pl2_clk_val "true"]} { set parent_freq [get_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] set parent_freq [expr $parent_freq * 1000000] set clock_name "zynqmp_clk 73" } elseif {[string match -nocase $pl3_clk_val "true"]} { set parent_freq [get_property CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] set parent_freq [expr $parent_freq * 1000000] set clock_name "zynqmp_clk 74" } if {![string equal $parent_freq ""]} { if {$parent_freq >= $clk_freq} { set div [expr round($parent_freq / $clk_freq)] set mult 1 } elseif {$parent_freq < $clk_freq} { set mult [expr round($clk_freq / $parent_freq)] set div 1 } } if {![string equal $div ""] && ![string equal $mult ""]} { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-factor-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clocks" $clock_name reference hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-div" $div int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-mult" $mult int } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } proc zynq_gen_pl_clk_binding {drv_handle} { # add dts binding for required nodes # clock-names = "ref_clk"; # clocks = <&clkc 0>; global bus_clk_list set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] # Assuming these device supports the clocks set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { set valid_ip_list "axi_timer axi_uartlite axi_uart16550 axi_gpio axi_traffic_gen axi_ethernet axi_ethernet_buffer can canfd axi_iic xadc_wiz vcu" } else { set valid_ip_list "xadc_wiz" } set valid_proc_list "ps7_cortexa9 psu_cortexa53" if {[lsearch -nocase $valid_proc_list $proctype] >= 0} { set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {[lsearch $valid_ip_list $iptype] >= 0} { # FIXME: this is hardcoded - maybe dynamic detection # Keep the below logic, until we have clock frame work for ZynqMP if {[string match -nocase $iptype "can"] || [string match -nocase $iptype "canfd"]} { set clks "can_clk s_axi_aclk" } elseif {[string match -nocase $iptype "vcu"]} { set clks "pll_ref_clk s_axi_lite_aclk" } else { set clks "s_axi_aclk" } foreach pin $clks { if {[string match -nocase $proctype "psu_cortexa53"] } { set dts_file [current_dt_tree] set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] $pin] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] # create the node and assuming reg 0 is taken by cpu set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} if {[string match -nocase $iptype "can"] || [string match -nocase $iptype "vcu"] || [string match -nocase $iptype "canfd"]} { set clocks [lindex $clk_refs 0] append clocks ">, <&[lindex $clk_refs 1]" set_drv_prop $drv_handle "clocks" "$clocks" reference set_drv_prop_if_empty $drv_handle "clock-names" "$clks" stringlist } else { set_drv_prop_if_empty $drv_handle "clocks" $clk_refs reference set_drv_prop_if_empty $drv_handle "clock-names" "$clks" stringlist } } } else { set_drv_prop_if_empty $drv_handle "clock-names" "ref_clk" stringlist set_drv_prop_if_empty $drv_handle "clocks" "clkc 0" reference } } } } } proc gen_endpoint {drv_handle value} { global end_mappings dict append end_mappings $drv_handle $value set val [dict get $end_mappings $drv_handle] } proc gen_axis_switch_in_endpoint {drv_handle value} { global axis_switch_in_end_mappings dict append axis_switch_in_end_mappings $drv_handle $value set val [dict get $axis_switch_in_end_mappings $drv_handle] } proc gen_axis_switch_in_remo_endpoint {drv_handle value} { global axis_switch_in_remo_mappings dict append axis_switch_in_remo_mappings $drv_handle $value set val [dict get $axis_switch_in_remo_mappings $drv_handle] } proc gen_axis_switch_port1_endpoint {drv_handle value} { global axis_switch_port1_end_mappings dict append axis_switch_port1_end_mappings $drv_handle $value set val [dict get $axis_switch_port1_end_mappings $drv_handle] } proc gen_axis_switch_port2_endpoint {drv_handle value} { global axis_switch_port2_end_mappings dict append axis_switch_port2_end_mappings $drv_handle $value set val [dict get $axis_switch_port2_end_mappings $drv_handle] } proc gen_axis_switch_port3_endpoint {drv_handle value} { global axis_switch_port3_end_mappings dict append axis_switch_port3_end_mappings $drv_handle $value set val [dict get $axis_switch_port3_end_mappings $drv_handle] } proc gen_axis_switch_port4_endpoint {drv_handle value} { global axis_switch_port4_end_mappings dict append axis_switch_port4_end_mappings $drv_handle $value set val [dict get $axis_switch_port4_end_mappings $drv_handle] } proc gen_axis_switch_port1_remote_endpoint {drv_handle value} { global axis_switch_port1_remo_mappings dict append axis_switch_port1_remo_mappings $drv_handle $value set val [dict get $axis_switch_port1_remo_mappings $drv_handle] } proc gen_axis_switch_port2_remote_endpoint {drv_handle value} { global axis_switch_port2_remo_mappings dict append axis_switch_port2_remo_mappings $drv_handle $value set val [dict get $axis_switch_port2_remo_mappings $drv_handle] } proc gen_axis_switch_port3_remote_endpoint {drv_handle value} { global axis_switch_port3_remo_mappings dict append axis_switch_port3_remo_mappings $drv_handle $value set val [dict get $axis_switch_port3_remo_mappings $drv_handle] } proc gen_axis_switch_port4_remote_endpoint {drv_handle value} { global axis_switch_port4_remo_mappings dict append axis_switch_port4_remo_mappings $drv_handle $value set val [dict get $axis_switch_port4_remo_mappings $drv_handle] } proc gen_axis_port1_endpoint {drv_handle value} { global port1_end_mappings dict append port1_end_mappings $drv_handle $value set val [dict get $port1_end_mappings $drv_handle] } proc gen_axis_port2_endpoint {drv_handle value} { global port2_end_mappings dict append port2_end_mappings $drv_handle $value set val [dict get $port2_end_mappings $drv_handle] } proc gen_axis_port3_endpoint {drv_handle value} { global port3_end_mappings dict append port3_end_mappings $drv_handle $value set val [dict get $port3_end_mappings $drv_handle] } proc gen_axis_port4_endpoint {drv_handle value} { global port4_end_mappings dict append port4_end_mappings $drv_handle $value set val [dict get $port4_end_mappings $drv_handle] } proc gen_broad_endpoint_port1 {drv_handle value} { global port1_broad_end_mappings dict append port1_broad_end_mappings $drv_handle $value set val [dict get $port1_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port2 {drv_handle value} { global port2_broad_end_mappings dict append port2_broad_end_mappings $drv_handle $value set val [dict get $port2_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port3 {drv_handle value} { global port3_broad_end_mappings dict append port3_broad_end_mappings $drv_handle $value set val [dict get $port3_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port4 {drv_handle value} { global port4_broad_end_mappings dict append port4_broad_end_mappings $drv_handle $value set val [dict get $port4_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port5 {drv_handle value} { global port5_broad_end_mappings dict append port5_broad_end_mappings $drv_handle $value set val [dict get $port5_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port6 {drv_handle value} { global port6_broad_end_mappings dict append port6_broad_end_mappings $drv_handle $value set val [dict get $port6_broad_end_mappings $drv_handle] } proc gen_broad_endpoint_port7 {drv_handle value} { global port7_broad_end_mappings dict append port7_broad_end_mappings $drv_handle $value set val [dict get $port7_broad_end_mappings $drv_handle] } proc get_endpoint_mapping {inip mappings} { #search the inip in mappings and return value if found set endpoint "" if {[dict exists $mappings $inip]} { set endpoint [dict get $mappings $inip] } return "$endpoint" } proc add_endpoint_mapping {drv_handle port_node in_end remo_in_end} { #Add the endpoint/remote-endpoint for given drv_handle if {[regexp -nocase $drv_handle "$remo_in_end" match]} { if {[llength $remo_in_end]} { set node [add_or_get_dt_node -n "endpoint" -l $remo_in_end -p $port_node] } if {[llength $in_end]} { hsi::utils::add_new_dts_param "$node" "remote-endpoint" $in_end reference } } } proc update_axis_switch_endpoints {inip port_node drv_handle} { #Read all the non memorymapped axis_switch global variables to get the #inip value corresponding to drv_handle global port1_end_mappings global port2_end_mappings global port3_end_mappings global port4_end_mappings global axis_port1_remo_mappings global axis_port2_remo_mappings global axis_port3_remo_mappings global axis_port4_remo_mappings if {[info exists port1_end_mappings] && [info exists axis_port1_remo_mappings]} { set in1_end [get_endpoint_mapping $inip $port1_end_mappings] set remo_in1_end [get_endpoint_mapping $inip $axis_port1_remo_mappings] } if {[info exists port2_end_mappings] && [info exists axis_port2_remo_mappings]} { set in2_end [get_endpoint_mapping $inip $port2_end_mappings] set remo_in2_end [get_endpoint_mapping $inip $axis_port2_remo_mappings] } if {[info exists port3_end_mappings] && [info exists axis_port3_remo_mappings]} { set in3_end [get_endpoint_mapping $inip $port3_end_mappings] set remo_in3_end [get_endpoint_mapping $inip $axis_port3_remo_mappings] } if {[info exists port4_end_mappings] && [info exists axis_port4_remo_mappings]} { set in4_end [get_endpoint_mapping $inip $port4_end_mappings] set remo_in4_end [get_endpoint_mapping $inip $axis_port4_remo_mappings] } if {[info exists remo_in1_end] && [info exists in1_end]} { dtg_verbose "$port_node $remo_in1_end" add_endpoint_mapping $drv_handle $port_node $in1_end $remo_in1_end } if {[info exists remo_in2_end] && [info exists in2_end]} { dtg_verbose "$port_node $remo_in2_end" add_endpoint_mapping $drv_handle $port_node $in2_end $remo_in2_end } if {[info exists remo_in3_end] && [info exists in3_end]} { dtg_verbose "$port_node $remo_in3_end" add_endpoint_mapping $drv_handle $port_node $in3_end $remo_in3_end } if {[info exists remo_in4_end] && [info exists in4_end]} { dtg_verbose "$port_node $remo_in4_end" add_endpoint_mapping $drv_handle $port_node $in4_end $remo_in4_end } } proc update_endpoints {drv_handle} { global end_mappings global remo_mappings global set port1_end_mappings global set port2_end_mappings global set port3_end_mappings global set port4_end_mappings global set axis_port1_remo_mappings global set axis_port2_remo_mappings global set axis_port3_remo_mappings global set axis_port4_remo_mappings global set port1_broad_end_mappings global set port2_broad_end_mappings global set port3_broad_end_mappings global set port4_broad_end_mappings global set port5_broad_end_mappings global set port6_broad_end_mappings global set port7_broad_end_mappings global set broad_port1_remo_mappings global set broad_port2_remo_mappings global set broad_port3_remo_mappings global set broad_port4_remo_mappings global set broad_port5_remo_mappings global set broad_port6_remo_mappings global set broad_port7_remo_mappings global set axis_switch_in_end_mappings global set axis_switch_in_remo_mappings global set axis_switch_port1_end_mappings global set axis_switch_port2_end_mappings global set axis_switch_port3_end_mappings global set axis_switch_port4_end_mappings global set axis_switch_port1_remo_mappings global set axis_switch_port2_remo_mappings global set axis_switch_port3_remo_mappings global set axis_switch_port4_remo_mappings set broad [hsi::utils::get_os_parameter_value "broad"] set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set node [gen_peripheral_nodes $drv_handle] set ip [get_cells -hier $drv_handle] if {[string match -nocase [get_property IP_NAME $ip] "v_proc_ss"]} { set topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]] if {$topology == 0} { set max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,video-width" $max_data_width int set ports_node [add_or_get_dt_node -n "ports" -l scaler_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l scaler_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "${port_node}" "/* For xlnx,video-format user needs to fill as per their requirement */" "" comment hsi::utils::add_new_dts_param "$port_node" "reg" 0 int hsi::utils::add_new_dts_param "$port_node" "xlnx,video-format" 3 int hsi::utils::add_new_dts_param "$port_node" "xlnx,video-width" $max_data_width int set scaninip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis"] if {[llength $scaninip] && \ [string match -nocase [get_property IP_NAME $scaninip] "axis_switch"]} { set axis_node [add_or_get_dt_node -n "endpoint" -l $drv_handle$scaninip -p $port_node] hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" axis_switch_out1$scaninip reference } # Get next IN IP if axis_slice connected if {[llength "$scaninip"] && \ [string match -nocase [get_property IP_NAME $scaninip] "axis_register_slice"]} { set intf "S_AXIS" set scaninip [get_connected_stream_ip [get_cells -hier $scaninip] "$intf"] } foreach inip $scaninip { if {[llength $inip]} { if {[string match -nocase [get_property IP_NAME $inip] "ISPPipeline_accel"]} { set port0_node [add_or_get_dt_node -n "endpoint" -l v_proc_ss$inip -p $port_node] hsi::utils::add_new_dts_param "$port0_node" "remote-endpoint" $inip$drv_handle reference } set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {![llength $ip_mem_handles]} { # Add endpoints if IN IP is axis_switch and non memory mapped if {[string match -nocase [get_property IP_NAME $inip] "axis_switch"]} { update_axis_switch_endpoints $inip $port_node $drv_handle } set broad_ip [get_broad_in_ip $inip] if {[llength $broad_ip]} { if {[string match -nocase [get_property IP_NAME $broad_ip] "axis_broadcaster"]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $broad_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set intlen [llength $master_intf] set sca_in_end "" set sca_remo_in_end "" set sca_remo_in1_end "" set sca_remo_in2_end "" set sca_remo_in3_end "" switch $intlen { "1" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set sca_in_end [dict get $port1_broad_end_mappings $broad_ip] dtg_verbose "sca_in_end:$sca_in_end" } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[regexp -nocase $drv_handle "$sca_remo_in_end" match]} { if {[llength $sca_remo_in_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in_end -p $port_node] } if {[llength $sca_in_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in_end reference } } } "2" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set sca_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} { set sca_in1_end [dict get $port2_broad_end_mappings $broad_ip] } if {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} { set sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip] } if {[regexp -nocase $drv_handle "$sca_remo_in_end" match]} { if {[llength $sca_remo_in_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in_end -p $port_node] } if {[llength $sca_in_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in_end reference } } if {[regexp -nocase $drv_handle "$sca_remo_in1_end" match]} { if {[llength $sca_remo_in1_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in1_end -p $port_node] } if {[llength $sca_in1_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in1_end reference } } } "3" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set sca_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} { set sca_in1_end [dict get $port2_broad_end_mappings $broad_ip] } if {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} { set sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip] } if {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} { set sca_in2_end [dict get $port3_broad_end_mappings $broad_ip] } if {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} { set sca_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip] } if {[regexp -nocase $drv_handle "$sca_remo_in_end" match]} { if {[llength $sca_remo_in_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in_end -p $port_node] } if {[llength $sca_in_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in_end reference } } if {[regexp -nocase $drv_handle "$sca_remo_in1_end" match]} { if {[llength $sca_remo_in1_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in1_end -p $port_node] } if {[llength $sca_in1_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in1_end reference } } if {[regexp -nocase $drv_handle "$sca_remo_in2_end" match]} { if {[llength $sca_remo_in2_end]} { set sca_node [add_or_get_dt_node -n "endpoint" -l $sca_remo_in2_end -p $port_node] } if {[llength $sca_in2_end]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $sca_in2_end reference } } } "4" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set sca_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set sca_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} { set sca_in1_end [dict get $port2_broad_end_mappings $broad_ip] } if {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} { set sca_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip] } if {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} { set sca_in2_end [dict get $port3_broad_end_mappings $broad_ip] } if {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} { set sca_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip] } if {[info exists port4_broad_end_mappings] && [dict exists $port4_broad_end_mappings $broad_ip]} { set sca_in3_end [dict get $port4_broad_end_mappings $broad_ip] } if {[info exists broad_port4_remo_mappings] && [dict exists $broad_port4_remo_mappings $broad_ip]} { set sca_remo_in3_end [dict get $broad_port4_remo_mappings $broad_ip] } } } return } } } } } foreach inip $scaninip { if {[llength $inip]} { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] } else { set inip [get_in_connect_ip $inip $master_intf] if {[llength $inip]} { if {[string match -nocase [get_property IP_NAME $inip] "axi_vdma"]} { gen_frmbuf_rd_node $inip $drv_handle $port_node } } } if {[llength $inip]} { set sca_in_end "" set sca_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set sca_in_end [dict get $end_mappings $inip] dtg_verbose "drv:$drv_handle inend:$sca_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set sca_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "drv:$drv_handle inremoend:$sca_remo_in_end" } if {[llength $sca_remo_in_end]} { set scainnode [add_or_get_dt_node -n "endpoint" -l $sca_remo_in_end -p $port_node] } if {[llength $sca_in_end]} { hsi::utils::add_new_dts_param "$scainnode" "remote-endpoint" $sca_in_end reference } } } else { dtg_warning "$drv_handle pin s_axis is not connected..check your design" } } } if {$topology == 3} { set ports_node [add_or_get_dt_node -n "ports" -l csc_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l csc_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "${port_node}" "/* For xlnx,video-format user needs to fill as per their requirement */" "" comment hsi::utils::add_new_dts_param "$port_node" "reg" 0 int hsi::utils::add_new_dts_param "$port_node" "xlnx,video-format" 3 int set max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$port_node" "xlnx,video-width" $max_data_width int set cscinip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis"] if {[llength $cscinip] && \ [string match -nocase [get_property IP_NAME $cscinip] "axis_switch"]} { set csc_node [add_or_get_dt_node -n "endpoint" -l $drv_handle$cscinip -p $port_node] hsi::utils::add_new_dts_param "$csc_node" "remote-endpoint" axis_switch_out2$cscinip reference } if {[llength $cscinip]} { foreach inip $cscinip { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $port_node } } else { set inip [get_in_connect_ip $inip $master_intf] if {[llength $inip]} { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $port_node } } } if {[llength $inip]} { set csc_in_end "" set csc_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set csc_in_end [dict get $end_mappings $inip] dtg_verbose "drv:$drv_handle inend:$csc_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set csc_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "drv:$drv_handle inremoend:$csc_remo_in_end" } if {[llength $csc_remo_in_end]} { set cscinnode [add_or_get_dt_node -n "endpoint" -l $csc_remo_in_end -p $port_node] } if {[llength $csc_in_end]} { hsi::utils::add_new_dts_param "$cscinnode" "remote-endpoint" $csc_in_end reference } } } } else { dtg_warning "$drv_handle pin s_axis is not connected..check your design" } } } if {[string match -nocase [get_property IP_NAME $ip] "v_demosaic"]} { set ports_node [add_or_get_dt_node -n "ports" -l demosaic_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l demosaic_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set demo_inip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] set len [llength $demo_inip] if {$len > 1} { for {set i 0 } {$i < $len} {incr i} { set temp_ip [lindex $demo_inip $i] if {[regexp -nocase "ila" $temp_ip match]} { continue } set demo_inip "$temp_ip" } } foreach inip $demo_inip { if {[llength $inip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {![llength $ip_mem_handles]} { set broad_ip [get_broad_in_ip $inip] if {[llength $broad_ip]} { if {[string match -nocase [get_property IP_NAME $broad_ip] "axis_broadcaster"]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $broad_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set intlen [llength $master_intf] set mipi_in_end "" set mipi_remo_in_end "" switch $intlen { "1" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set mipi_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set mipi_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists sca_remo_in_end] && [regexp -nocase $drv_handle "$sca_remo_in_end" match]} { if {[llength $mipi_remo_in_end]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l $mipi_remo_in_end -p $port_node] } if {[llength $mipi_in_end]} { hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $mipi_in_end reference } } } "2" { if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set mipi_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set mipi_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} { set mipi_in1_end [dict get $port2_broad_end_mappings $broad_ip] } if {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} { set mipi_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip] } if {[info exists mipi_remo_in_end] && [regexp -nocase $drv_handle "$mipi_remo_in_end" match]} { if {[llength $mipi_remo_in_end]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l $mipi_remo_in_end -p $port_node] } if {[llength $mipi_in_end]} { hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $mipi_in_end reference } } if {[info exists mipi_remo_in1_end] && [regexp -nocase $drv_handle "$mipi_remo_in1_end" match]} { if {[llength $mipi_remo_in1_end]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l $mipi_remo_in1_end -p $port_node] } if {[llength $mipi_in1_end]} { hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $mipi_in1_end reference } } } } return } } } } } if {[llength $demo_inip]} { if {[string match -nocase [get_property IP_NAME $demo_inip] "axis_switch"]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $demo_inip] if {![llength $ip_mem_handles]} { set demo_in_end "" set demo_remo_in_end "" if {[info exists port1_end_mappings] && [dict exists $port1_end_mappings $demo_inip]} { set demo_in_end [dict get $port1_end_mappings $demo_inip] dtg_verbose "demo_in_end:$demo_in_end" } if {[info exists axis_port1_remo_mappings] && [dict exists $axis_port1_remo_mappings $demo_inip]} { set demo_remo_in_end [dict get $axis_port1_remo_mappings $demo_inip] dtg_verbose "demo_remo_in_end:$demo_remo_in_end" } if {[info exists port2_end_mappings] && [dict exists $port2_end_mappings $demo_inip]} { set demo_in1_end [dict get $port2_end_mappings $demo_inip] dtg_verbose "demo_in1_end:$demo_in1_end" } if {[info exists axis_port2_remo_mappings] && [dict exists $axis_port2_remo_mappings $demo_inip]} { set demo_remo_in1_end [dict get $axis_port2_remo_mappings $demo_inip] dtg_verbose "demo_remo_in1_end:$demo_remo_in1_end" } if {[info exists port3_end_mappings] && [dict exists $port3_end_mappings $demo_inip]} { set demo_in2_end [dict get $port3_end_mappings $demo_inip] dtg_verbose "demo_in2_end:$demo_in2_end" } if {[info exists axis_port3_remo_mappings] && [dict exists $axis_port3_remo_mappings $demo_inip]} { set demo_remo_in2_end [dict get $axis_port3_remo_mappings $demo_inip] dtg_verbose "demo_remo_in2_end:$demo_remo_in2_end" } if {[info exists port4_end_mappings] && [dict exists $port4_end_mappings $demo_inip]} { set demo_in3_end [dict get $port4_end_mappings $demo_inip] dtg_verbose "demo_in3_end:$demo_in3_end" } if {[info exists axis_port4_remo_mappings] && [dict exists $axis_port4_remo_mappings $demo_inip]} { set demo_remo_in3_end [dict get $axis_port4_remo_mappings $demo_inip] dtg_verbose "demo_remo_in3_end:$demo_remo_in3_end" } set drv [split $demo_remo_in_end "-"] set handle [lindex $drv 0] if {[info exists demo_remo_in_end] && [regexp -nocase $drv_handle "$demo_remo_in_end" match]} { if {[llength $demo_remo_in_end]} { set demosaic_node [add_or_get_dt_node -n "endpoint" -l $demo_remo_in_end -p $port_node] } if {[llength $demo_in_end]} { hsi::utils::add_new_dts_param "$demosaic_node" "remote-endpoint" $demo_in_end reference } dtg_verbose "****DEMO_END1****" } if {[info exists demo_remo_in1_end] && [regexp -nocase $drv_handle "$demo_remo_in1_end" match]} { if {[llength $demo_remo_in1_end]} { set demosaic_node1 [add_or_get_dt_node -n "endpoint" -l $demo_remo_in1_end -p $port_node] } if {[llength $demo_in1_end]} { hsi::utils::add_new_dts_param "$demosaic_node1" "remote-endpoint" $demo_in1_end reference } dtg_verbose "****DEMO_END2****" } if {[info exists demo_remo_in2_end] && [regexp -nocase $drv_handle "$demo_remo_in2_end" match]} { if {[llength $demo_remo_in2_end]} { set demosaic_node2 [add_or_get_dt_node -n "endpoint" -l $demo_remo_in2_end -p $port_node] } if {[llength $demo_in2_end]} { hsi::utils::add_new_dts_param "$demosaic_node2" "remote-endpoint" $demo_in2_end reference } dtg_verbose "****DEMO_END3****" } if {[info exists demo_remo_in3_end] && [regexp -nocase $drv_handle "$demo_remo_in3_end" match]} { if {[llength $demo_remo_in3_end]} { set demosaic_node3 [add_or_get_dt_node -n "endpoint" -l $demo_remo_in3_end -p $port_node] } if {[llength $demo_in3_end]} { hsi::utils::add_new_dts_param "$demosaic_node3" "remote-endpoint" $demo_in3_end reference } dtg_verbose "****DEMO_END3****" } return } else { set demo_in_end "" set demo_remo_in_end "" if {[info exists axis_switch_port1_end_mappings] && [dict exists $axis_switch_port1_end_mappings $demo_inip]} { set demo_in_end [dict get $axis_switch_port1_end_mappings $demo_inip] dtg_verbose "demo_in_end:$demo_in_end" } if {[info exists axis_switch_port1_remo_mappings] && [dict exists $axis_switch_port1_remo_mappings $demo_inip]} { set demo_remo_in_end [dict get $axis_switch_port1_remo_mappings $demo_inip] dtg_verbose "demo_remo_in_end:$demo_remo_in_end" } if {[info exists axis_switch_port2_end_mappings] && [dict exists $axis_switch_port2_end_mappings $demo_inip]} { set demo_in1_end [dict get $axis_switch_port2_end_mappings $demo_inip] dtg_verbose "demo_in1_end:$demo_in1_end" } if {[info exists axis_switch_port2_remo_mappings] && [dict exists $axis_switch_port2_remo_mappings $demo_inip]} { set demo_remo_in1_end [dict get $axis_switch_port2_remo_mappings $demo_inip] dtg_verbose "demo_remo_in1_end:$demo_remo_in1_end" } if {[info exists axis_switch_port3_end_mappings] && [dict exists $axis_switch_port3_end_mappings $demo_inip]} { set demo_in2_end [dict get $axis_switch_port3_end_mappings $demo_inip] dtg_verbose "demo_in2_end:$demo_in2_end" } if {[info exists axis_switch_port3_remo_mappings] && [dict exists $axis_switch_port3_remo_mappings $demo_inip]} { set demo_remo_in2_end [dict get $axis_switch_port3_remo_mappings $demo_inip] dtg_verbose "demo_remo_in2_end:$demo_remo_in2_end" } if {[info exists axis_switch_port4_end_mappings] && [dict exists $axis_switch_port4_end_mappings $demo_inip]} { set demo_in3_end [dict get $axis_switch_port4_end_mappings $demo_inip] dtg_verbose "demo_in3_end:$demo_in3_end" } if {[info exists axis_switch_port4_remo_mappings] && [dict exists $axis_switch_port4_remo_mappings $demo_inip]} { set demo_remo_in3_end [dict get $axis_switch_port4_remo_mappings $demo_inip] dtg_verbose "demo_remo_in3_end:$demo_remo_in3_end" } set drv [split $demo_remo_in_end "-"] set handle [lindex $drv 0] if {[regexp -nocase $drv_handle "$demo_remo_in_end" match]} { if {[llength $demo_remo_in_end]} { set demosaic_node [add_or_get_dt_node -n "endpoint" -l $demo_remo_in_end -p $port_node] } if {[llength $demo_in_end]} { hsi::utils::add_new_dts_param "$demosaic_node" "remote-endpoint" $demo_in_end reference } dtg_verbose "****DEMO_END1****" } if {[regexp -nocase $drv_handle "$demo_remo_in1_end" match]} { if {[llength $demo_remo_in1_end]} { set demosaic_node1 [add_or_get_dt_node -n "endpoint" -l $demo_remo_in1_end -p $port_node] } if {[llength $demo_in1_end]} { hsi::utils::add_new_dts_param "$demosaic_node1" "remote-endpoint" $demo_in1_end reference } dtg_verbose "****DEMO_END2****" } } } } set inip "" if {[llength $demo_inip]} { foreach inip $demo_inip { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } set inip [get_in_connect_ip $inip $master_intf] } if {[llength $inip]} { set demo_in_end "" set demo_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set demo_in_end [dict get $end_mappings $inip] dtg_verbose "demo_in_end:$demo_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set demo_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "demo_remo_in_end:$demo_remo_in_end" } if {[llength $demo_remo_in_end]} { set demosaic_node [add_or_get_dt_node -n "endpoint" -l $demo_remo_in_end -p $port_node] } if {[llength $demo_in_end]} { hsi::utils::add_new_dts_param "$demosaic_node" "remote-endpoint" $demo_in_end reference } } } } else { dtg_warning "$drv_handle pin s_axis is not connected..check your design" } dtg_verbose "***************DEMOEND****************" } if {[string match -nocase [get_property IP_NAME $ip] "v_gamma_lut"]} { set ports_node [add_or_get_dt_node -n "ports" -l gamma_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l gamma_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$port_node" "xlnx,video-width" $max_data_width int set gamma_inip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] set inip "" if {[llength $gamma_inip]} { foreach inip $gamma_inip { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } set inip [get_in_connect_ip $inip $master_intf] } if {[llength $inip]} { set gamma_in_end "" set gamma_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set gamma_in_end [dict get $end_mappings $inip] dtg_verbose "gamma_in_end:$gamma_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set gamma_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "gamma_remo_in_end:$gamma_remo_in_end" } if {[llength $gamma_remo_in_end]} { set gamma_node [add_or_get_dt_node -n "endpoint" -l $gamma_remo_in_end -p $port_node] } if {[llength $gamma_in_end]} { hsi::utils::add_new_dts_param "$gamma_node" "remote-endpoint" $gamma_in_end reference } } } } else { dtg_warning "$drv_handle pin s_axis_video is not connected..check your design" } } if {[string match -nocase [get_property IP_NAME $ip] "mipi_dsi_tx_subsystem"]} { set dsitx_inip [get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS"] if {![llength $dsitx_inip]} { dtg_warning "$drv_handle pin S_AXIS is not connected ..check your design" } set port_node [add_or_get_dt_node -n "port" -l encoder_dsi_port$drv_handle -u 0 -p $node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set inip "" foreach inip $dsitx_inip { if {[llength $inip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $port_node } } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } puts "******************dsitx****************" set inip [get_in_connect_ip $inip $master_intf] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $port_node } } } } if {[llength $inip]} { set dsitx_in_end "" set dsitx_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set dsitx_in_end [dict get $end_mappings $inip] dtg_verbose "dsitx_in_end:$dsitx_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set dsitx_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "dsitx_remo_in_end:$dsitx_remo_in_end" } if {[llength $dsitx_remo_in_end]} { set dsitx_node [add_or_get_dt_node -n "endpoint" -l $dsitx_remo_in_end -p $port_node] } if {[llength $dsitx_in_end]} { hsi::utils::add_new_dts_param "$dsitx_node" "remote-endpoint" $dsitx_in_end reference } } } if {[string match -nocase [get_property IP_NAME $ip] "v_smpte_uhdsdi_tx_ss"]} { set ports_node [add_or_get_dt_node -n "ports" -l sditx_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set sdi_port_node [add_or_get_dt_node -n "port" -l encoder_sdi_port$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$sdi_port_node" "reg" 0 int set sditx_in_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "VIDEO_IN"] if {![llength $sditx_in_ip]} { dtg_warning "$drv_handle pin VIDEO_IN is not connected...check your design" } set inip "" foreach inip $sditx_in_ip { if {[llength $inip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $sdi_port_node } } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } set inip [get_in_connect_ip $inip $master_intf] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $sdi_port_node } } } } if {[llength $inip]} { set sditx_in_end "" set sditx_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set sditx_in_end [dict get $end_mappings $inip] dtg_verbose "sditx_in_end:$sditx_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set sditx_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "sditx_remo_in_end:$sditx_remo_in_end" } if {[llength $sditx_remo_in_end]} { set sditx_node [add_or_get_dt_node -n "endpoint" -l $sditx_remo_in_end -p $sdi_port_node] } if {[llength $sditx_in_end]} { hsi::utils::add_new_dts_param "$sditx_node" "remote-endpoint" $sditx_in_end reference } } } if {[string match -nocase [get_property IP_NAME $ip] "v_hdmi_tx_ss"] || [string match -nocase [get_property IP_NAME $ip] "v_hdmi_txss1"]} { set ports_node [add_or_get_dt_node -n "ports" -l hdmitx_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set hdmi_port_node [add_or_get_dt_node -n "port" -l encoder_hdmi_port$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$hdmi_port_node" "reg" 0 int set hdmitx_in_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "VIDEO_IN"] if {![llength $hdmitx_in_ip]} { dtg_warning "$drv_handle pin VIDEO_IN is not connected...check your design" } set inip "" set axis_sw_nm "" foreach inip $hdmitx_in_ip { if {[llength $inip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $hdmitx_in_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $hdmi_port_node } } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } # Check if slice is connected to axis_switch(NM) if {[string match -nocase [get_property IP_NAME $inip] "axis_register_slice"]} { set intf "S_AXIS" set streamin_ip [get_connected_stream_ip [get_cells -hier $inip] $intf] if {[llength $streamin_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $streamin_ip] } if {![llength $ip_mem_handles] && [string match -nocase [get_property IP_NAME $streamin_ip] "axis_switch"]} { set inip "$streamin_ip" set axis_sw_nm "1" } } if {![llength $axis_sw_nm]} { set inip [get_in_connect_ip $inip $master_intf] } if {[string match -nocase [get_property IP_NAME $inip] "v_frmbuf_rd"]} { gen_frmbuf_rd_node $inip $drv_handle $hdmi_port_node } } } } if {[llength $inip]} { set hdmitx_in_end "" set hdmitx_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set hdmitx_in_end [dict get $end_mappings $inip] dtg_verbose "hdmitx_in_end:$hdmitx_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set hdmitx_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "hdmitx_remo_in_end:$hdmitx_remo_in_end" } if {[llength $hdmitx_remo_in_end]} { set hdmitx_node [add_or_get_dt_node -n "endpoint" -l $hdmitx_remo_in_end -p $hdmi_port_node] } if {[llength $hdmitx_in_end]} { hsi::utils::add_new_dts_param "$hdmitx_node" "remote-endpoint" $hdmitx_in_end reference } # Add endpoints if IN IP is axis_switch and NM if {[llength $axis_sw_nm]} { update_axis_switch_endpoints $inip $hdmi_port_node $drv_handle } } } if {[string match -nocase [get_property IP_NAME $ip] "v_scenechange"]} { set memory_scd [get_property CONFIG.MEMORY_BASED [get_cells -hier $drv_handle]] if {$memory_scd == 1} { #memory scd return } set scd_ports_node [add_or_get_dt_node -n "scd" -l scd_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$scd_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$scd_ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l scd_port0$drv_handle -u 0 -p $scd_ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set scd_inip [get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_VIDEO"] if {![llength $scd_inip]} { dtg_warning "$drv_handle pin S_AXIS_VIDEO is not connected...check your design" } set broad_ip [get_broad_in_ip $scd_inip] if {[llength $broad_ip]} { if {[string match -nocase [get_property IP_NAME $broad_ip] "axis_broadcaster"]} { set scd_in_end "" set scd_remo_in_end "" if {[info exists port1_broad_end_mappings] && [dict exists $port1_broad_end_mappings $broad_ip]} { set scd_in_end [dict get $port1_broad_end_mappings $broad_ip] } if {[info exists broad_port1_remo_mappings] && [dict exists $broad_port1_remo_mappings $broad_ip]} { set scd_remo_in_end [dict get $broad_port1_remo_mappings $broad_ip] } if {[info exists port2_broad_end_mappings] && [dict exists $port2_broad_end_mappings $broad_ip]} { set scd_in1_end [dict get $port2_broad_end_mappings $broad_ip] } if {[info exists broad_port2_remo_mappings] && [dict exists $broad_port2_remo_mappings $broad_ip]} { set scd_remo_in1_end [dict get $broad_port2_remo_mappings $broad_ip] } if {[info exists port3_broad_end_mappings] && [dict exists $port3_broad_end_mappings $broad_ip]} { set scd_in2_end [dict get $port3_broad_end_mappings $broad_ip] } if {[info exists broad_port3_remo_mappings] && [dict exists $broad_port3_remo_mappings $broad_ip]} { set scd_remo_in2_end [dict get $broad_port3_remo_mappings $broad_ip] } if {[info exists port4_broad_end_mappings] && [dict exists $port4_broad_end_mappings $broad_ip]} { set scd_in3_end [dict get $port4_broad_end_mappings $broad_ip] } if {[info exists broad_port4_remo_mappings] && [dict exists $broad_port4_remo_mappings $broad_ip]} { set scd_remo_in3_end [dict get $broad_port4_remo_mappings $broad_ip] } if {[info exists scd_remo_in_end] && [regexp -nocase $drv_handle "$scd_remo_in_end" match]} { if {[llength $scd_remo_in_end]} { set scd_node [add_or_get_dt_node -n "endpoint" -l $scd_remo_in_end -p $port_node] } if {[llength $scd_in_end]} { hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $scd_in_end reference } } if {[info exists scd_remo_in1_end] && [regexp -nocase $drv_handle "$scd_remo_in1_end" match]} { if {[llength $scd_remo_in1_end]} { set scd_node [add_or_get_dt_node -n "endpoint" -l $scd_remo_in1_end -p $port_node] } if {[llength $scd_in1_end]} { hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $scd_in1_end reference } } if {[info exists scd_remo_in2_end] && [regexp -nocase $drv_handle "$scd_remo_in2_end" match]} { if {[llength $scd_remo_in2_end]} { set scd_node [add_or_get_dt_node -n "endpoint" -l $scd_remo_in2_end -p $port_node] } if {[llength $scd_in2_end]} { hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $scd_in2_end reference } } if {[info exists scd_remo_in3_end] && [regexp -nocase $drv_handle "$scd_remo_in3_end" match]} { if {[llength $scd_remo_in3_end]} { set scd_node [add_or_get_dt_node -n "endpoint" -l $scd_remo_in3_end -p $port_node] } if {[llength $scd_in3_end]} { hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $scd_in3_end reference } } return } } foreach inip $scd_inip { if {[llength $inip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $inip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] } else { if {[string match -nocase [get_property IP_NAME $inip] "system_ila"]} { continue } set inip [get_in_connect_ip $inip $master_intf] } if {[llength $inip]} { set scd_in_end "" set scd_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set scd_in_end [dict get $end_mappings $inip] } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set scd_remo_in_end [dict get $remo_mappings $inip] } if {[llength $scd_remo_in_end]} { set scd_node [add_or_get_dt_node -n "endpoint" -l $scd_remo_in_end -p $port_node] } if {[llength $scd_in_end]} { hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $scd_in_end reference } } } } } if {[string match -nocase [get_property IP_NAME $ip] "v_tpg"]} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "ps7_cortexa9"]} { #TBF return } set ports_node [add_or_get_dt_node -n "ports" -l tpg_ports$drv_handle -p $node] set port0_node [add_or_get_dt_node -n "port" -l tpg_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int hsi::utils::add_new_dts_param "${port0_node}" "/* Fill the field xlnx,video-format based on user requirement */" "" comment hsi::utils::add_new_dts_param "$port0_node" "xlnx,video-format" 2 int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$port0_node" "xlnx,video-width" $max_data_width int set tpg_inip [get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_VIDEO"] if {![llength $tpg_inip]} { dtg_warning "$drv_handle pin S_AXIS_VIDEO is not connected...check your design" } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $tpg_inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $tpg_inip $master_intf] #if tpg is getting input from gamma ip then setting inip #to gamma as the get_in_connect_ip is traversing through #first input and which might not be correct. For each ip we should #have immediate input. As we are not sure about the history #handling for only gamma ip for now. if {[string match -nocase [get_property IP_NAME $tpg_inip] "v_gamma_lut"]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $tpg_inip] if {[llength $ip_mem_handles]} { set inip $tpg_inip } } if {[llength $inip]} { set tpg_in_end "" set tpg_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set tpg_in_end [dict get $end_mappings $inip] } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set tpg_remo_in_end [dict get $remo_mappings $inip] } if {[llength $tpg_remo_in_end]} { set tpg_node [add_or_get_dt_node -n "endpoint" -l $tpg_remo_in_end -p $port0_node] } if {[llength $tpg_in_end]} { hsi::utils::add_new_dts_param "$tpg_node" "remote-endpoint" $tpg_in_end reference } } } } set ips [get_cells -hier -filter {IP_NAME == "axis_switch"}] foreach ip $ips { if {[llength $ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {![llength $ip_mem_handles]} { set axis_ip [get_property IP_NAME $ip] set default_dts [set_drv_def_dts $ip] set unit_addr [get_baseaddr ${ip} no_prefix] if { ![string equal $unit_addr "-1"] } { break } set label $ip set bus_node [add_or_get_bus_node $ip $default_dts] set dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]] if {[llength $axis_ip]} { set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $ip $intf] if {[llength $inip]} { set inipname [get_property IP_NAME $inip] set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange" if {[lsearch -nocase $valid_mmip_list $inipname] >= 0} { set rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u 0 -d ${default_dts} -p $bus_node -auto_ref_parent] set ports_node [add_or_get_dt_node -n "ports" -l axis_switch_ports$ip -p $rt_node] gen_axis_switch_clk_property $ip $default_dts $rt_node hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l axis_switch_port0$ip -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int if {[llength $inip]} { set axis_switch_in_end "" set axis_switch_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set axis_switch_in_end [dict get $end_mappings $inip] dtg_verbose "drv:$ip inend:$axis_switch_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set axis_switch_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "drv:$ip inremoend:$axis_switch_remo_in_end" } if {[llength $axis_switch_remo_in_end]} { set axisinnode [add_or_get_dt_node -n "endpoint" -l $axis_switch_remo_in_end -p $port_node] } if {[llength $axis_switch_in_end]} { hsi::utils::add_new_dts_param "$axisinnode" "remote-endpoint" $axis_switch_in_end reference } } } } } } } } set ip [get_cells -hier $drv_handle] if {[string match -nocase [get_property IP_NAME $ip] "axis_switch"]} { set axis_ip [get_property IP_NAME $ip] set default_dts [set_drv_def_dts $ip] set unit_addr [get_baseaddr ${ip} no_prefix] set bus_node [add_or_get_bus_node $ip $default_dts] set dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]] set intf "S00_AXIS" set inips [get_axis_switch_in_connect_ip $ip $intf] foreach inip $inips { if {[llength $inip]} { set inipname [get_property IP_NAME $inip] set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange" if {[lsearch -nocase $valid_mmip_list $inipname] >= 0} { set ports_node [add_or_get_dt_node -n "ports" -l axis_switch_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l axis_switch_port0$ip -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int if {[llength $inip]} { set axis_switch_in_end "" set axis_switch_remo_in_end "" if {[info exists axis_switch_in_end_mappings] && [dict exists $axis_switch_in_end_mappings $inip]} { set axis_switch_in_end [dict get $axis_switch_in_end_mappings $inip] dtg_verbose "drv:$ip inend:$axis_switch_in_end" } if {[info exists axis_switch_in_remo_mappings] && [dict exists $axis_switch_in_remo_mappings $inip]} { set axis_switch_remo_in_end [dict get $axis_switch_in_remo_mappings $inip] dtg_verbose "drv:$ip inremoend:$axis_switch_remo_in_end" } if {[llength $axis_switch_remo_in_end]} { set axisinnode [add_or_get_dt_node -n "endpoint" -l $axis_switch_remo_in_end -p $port_node] } if {[llength $axis_switch_in_end]} { hsi::utils::add_new_dts_param "$axisinnode" "remote-endpoint" $axis_switch_in_end reference } } } } } } set ips [get_cells -hier -filter {IP_NAME == "axis_broadcaster"}] foreach ip $ips { if {[llength $ip]} { set axis_broad_ip [get_property IP_NAME $ip] set default_dts [set_drv_def_dts $ip] # broad_ip means broadcaster input ip is connected to another ip set broad_ip [get_broad_in_ip $ip] set validate_ip 1 if {[llength $broad_ip]} { if { [get_property IP_NAME $broad_ip] in { "v_proc_ss" "ISPPipeline_accel" } } { # set validate ip is 0 when axis_broadcaster input ip is # connect to v_proc_ss or ISPPipeline_accel to skip the below checks set validate_ip 0 } } # add unit_addr and ip_type check when axis_broadcaster input ip is connected with other ips if {$validate_ip} { set unit_addr [get_baseaddr ${ip} no_prefix] if { ![string equal $unit_addr "-1"] } { break } set ip_type [get_property IP_TYPE $ip] if {[string match -nocase $ip_type "BUS"]} { break } } set label $ip set bus_node [add_or_get_bus_node $ip $default_dts] set dev_type [get_property IP_NAME [get_cell -hier [get_cells -hier $ip]]] set rt_node [add_or_get_dt_node -n "axis_broadcaster$ip" -l ${label} -u 0 -d ${default_dts} -p $bus_node -auto_ref_parent] if {[llength $axis_broad_ip]} { set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $ip $intf] if {[llength $broad]} { if {[llength $inip]} { set inipname [get_property IP_NAME $inip] set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_hdmi_rx_ss v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_hdmi_tx_ss v_hdmi_txss1 v_uhdsdi_audio audio_formatter i2s_receiver i2s_transmitter mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange ISPPipeline_accel" if {[lsearch -nocase $valid_mmip_list $inipname] >= 0} { set ports_node [add_or_get_dt_node -n "ports" -l axis_broadcaster_ports$ip -p $rt_node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l axis_broad_port0$ip -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int if {[llength $inip]} { set axis_broad_in_end "" set axis_broad_remo_in_end "" if {[info exists end_mappings] && [dict exists $end_mappings $inip]} { set axis_broad_in_end [dict get $end_mappings $inip] dtg_verbose "drv:$ip inend:$axis_broad_in_end" } if {[info exists remo_mappings] && [dict exists $remo_mappings $inip]} { set axis_broad_remo_in_end [dict get $remo_mappings $inip] dtg_verbose "drv:$ip inremoend:$axis_broad_remo_in_end" } if {[llength $axis_broad_remo_in_end]} { set axisinnode [add_or_get_dt_node -n "endpoint" -l $axis_broad_remo_in_end -p $port_node] } if {[llength $axis_broad_in_end]} { hsi::utils::add_new_dts_param "$axisinnode" "remote-endpoint" $axis_broad_in_end reference } } } } } } } } } proc get_axis_switch_in_connect_ip {ip intfpins} { global connectip "" foreach intf $intfpins { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] foreach cip $connectip { if {[llength $cip]} { set ipname [get_property IP_NAME $cip] #puts "ipname:$ipname" set ip_mem_handles [hsi::utils::get_ip_mem_ranges $cip] if {[llength $ip_mem_handles]} { break } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $cip] -filter {TYPE==SLAVE || TYPE ==TARGET}] get_axis_switch_in_connect_ip $cip $master_intf } } } } return $connectip } proc gen_remoteendpoint {drv_handle value} { global remo_mappings dict append remo_mappings $drv_handle $value set val [dict get $remo_mappings $drv_handle] } proc gen_axis_port1_remoteendpoint {drv_handle value} { global axis_port1_remo_mappings dict append axis_port1_remo_mappings $drv_handle $value set val [dict get $axis_port1_remo_mappings $drv_handle] } proc gen_axis_port2_remoteendpoint {drv_handle value} { global axis_port2_remo_mappings dict append axis_port2_remo_mappings $drv_handle $value set val [dict get $axis_port2_remo_mappings $drv_handle] } proc gen_axis_port3_remoteendpoint {drv_handle value} { global axis_port3_remo_mappings dict append axis_port3_remo_mappings $drv_handle $value set val [dict get $axis_port3_remo_mappings $drv_handle] } proc gen_axis_port4_remoteendpoint {drv_handle value} { global axis_port4_remo_mappings dict append axis_port4_remo_mappings $drv_handle $value set val [dict get $axis_port4_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port1 {drv_handle value} { global broad_port1_remo_mappings dict append broad_port1_remo_mappings $drv_handle $value set val [dict get $broad_port1_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port2 {drv_handle value} { global broad_port2_remo_mappings dict append broad_port2_remo_mappings $drv_handle $value set val [dict get $broad_port2_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port3 {drv_handle value} { global broad_port3_remo_mappings dict append broad_port3_remo_mappings $drv_handle $value set val [dict get $broad_port3_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port4 {drv_handle value} { global broad_port4_remo_mappings dict append broad_port4_remo_mappings $drv_handle $value set val [dict get $broad_port4_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port5 {drv_handle value} { global broad_port5_remo_mappings dict append broad_port5_remo_mappings $drv_handle $value set val [dict get $broad_port5_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port6 {drv_handle value} { global broad_port6_remo_mappings dict append broad_port6_remo_mappings $drv_handle $value set val [dict get $broad_port6_remo_mappings $drv_handle] } proc gen_broad_remoteendpoint_port7 {drv_handle value} { global broad_port7_remo_mappings dict append broad_port7_remo_mappings $drv_handle $value set val [dict get $broad_port7_remo_mappings $drv_handle] } proc gen_frmbuf_rd_node {ip drv_handle sdi_port_node} { set frmbuf_rd_node [add_or_get_dt_node -n "endpoint" -l encoder$drv_handle -p $sdi_port_node] hsi::utils::add_new_dts_param "$frmbuf_rd_node" "remote-endpoint" $ip$drv_handle reference set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set pl_display [add_or_get_dt_node -n "drm-pl-disp-drv$drv_handle" -l "v_pl_disp$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $pl_display "compatible" "xlnx,pl-disp" string hsi::utils::add_new_dts_param $pl_display "dmas" "$ip 0" reference hsi::utils::add_new_dts_param $pl_display "dma-names" "dma0" string hsi::utils::add_new_dts_param "${pl_display}" "/* Fill the field xlnx,vformat based on user requirement */" "" comment hsi::utils::add_new_dts_param $pl_display "xlnx,vformat" "YUYV" string set pl_display_port_node [add_or_get_dt_node -n "port" -l pl_display_port$drv_handle -u 0 -p $pl_display] hsi::utils::add_new_dts_param "$pl_display_port_node" "reg" 0 int set pl_disp_crtc_node [add_or_get_dt_node -n "endpoint" -l $ip$drv_handle -p $pl_display_port_node] hsi::utils::add_new_dts_param "$pl_disp_crtc_node" "remote-endpoint" encoder$drv_handle reference } proc gen_broadcaster {ip} { dtg_verbose "+++++++++gen_broadcaster:$ip" set count 0 set inputip "" set outip "" set connectip "" set compatible [get_comp_str $ip] set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_connected_stream_ip [get_cells -hier $ip] $intf] set inip [get_in_connect_ip $ip $intf] set default_dts [set_drv_def_dts $ip] set bus_node [add_or_get_bus_node $ip $default_dts] set broad_node [add_or_get_dt_node -n "axis_broadcaster$ip" -l $ip -u 0 -p $bus_node] set ports_node [add_or_get_dt_node -n "ports" -l axis_broadcaster_ports$ip -p $broad_node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int hsi::utils::add_new_dts_param "$broad_node" "compatible" "$compatible" string set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set broad 10 hsi::utils::set_os_parameter_value "broad" $broad foreach intf $master_intf { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set connectip [get_connected_stream_ip [get_cells -hier $connectip] $master_intf] if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master2_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set connectip [get_connected_stream_ip [get_cells -hier $connectip] $master2_intf] } if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master3_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set connectip [get_connected_stream_ip [get_cells -hier $connectip] $master3_intf] } } } } incr count set port_node [add_or_get_dt_node -n "port" -l axis_broad_port$count$ip -u $count -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" $count int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_broad_out$count$ip -p $port_node] hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference set addbroadip "1" if {[get_property IP_NAME $connectip] in { "v_scenechange" "v_frmbuf_wr" }} { set addbroadip "" } if {[llength $addbroadip]} { gen_broad_endpoint_port$count $ip "axis_broad_out$count$ip" gen_broad_remoteendpoint_port$count $ip $connectip$ip } append inputip " " $connectip append outip " " $connectip$ip if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_broad_frmbuf_wr_node $inputip $outip $ip $count } } } } proc gen_axis_switch {ip} { set compatible [get_comp_str $ip] dtg_verbose "+++++++++gen_axis_switch:$ip" set routing_mode [get_property CONFIG.ROUTING_MODE [get_cells -hier $ip]] if {$routing_mode == 1} { # Routing_mode is 1 means it is a memory mapped return } set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_connected_stream_ip [get_cells -hier $ip] $intf] set intf1 [::hsi::get_intf_pins -of_objects [get_cells -hier $inip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set iip [get_connected_stream_ip [get_cells -hier $inip] $intf1] set inip [get_in_connect_ip $ip $intf] set default_dts [set_drv_def_dts $ip] set bus_node [add_or_get_bus_node $ip $default_dts] set switch_node [add_or_get_dt_node -n "axis_switch_$ip" -l $ip -u 0 -p $bus_node] set ports_node [add_or_get_dt_node -n "ports" -l axis_switch_ports$ip -p $switch_node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] hsi::utils::add_new_dts_param "$switch_node" "xlnx,routing-mode" $routing_mode int set num_si [get_property CONFIG.NUM_SI [get_cells -hier $ip]] hsi::utils::add_new_dts_param "$switch_node" "xlnx,num-si-slots" $num_si int set num_mi [get_property CONFIG.NUM_MI [get_cells -hier $ip]] hsi::utils::add_new_dts_param "$switch_node" "xlnx,num-mi-slots" $num_mi int hsi::utils::add_new_dts_param "$switch_node" "compatible" "$compatible" string set count 0 foreach intf $master_intf { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] #Get next out IP if slice connected if {[llength $connectip] && \ [string match -nocase [get_property IP_NAME $connectip] "axis_register_slice"]} { set intf "M_AXIS" set connectip [get_connected_stream_ip [get_cells -hier $connectip] "$intf"] } set len [llength $connectip] if {$len > 1} { for {set i 0 } {$i < $len} {incr i} { set temp_ip [lindex $connectip $i] if {[regexp -nocase "ila" $temp_ip match]} { continue } set connectip "$temp_ip" } } if {[llength $connectip]} { incr count } if {$count == 1} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port1$ip -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 1 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out1$ip -p $port_node] gen_axis_port1_endpoint $ip "axis_switch_out1$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_port1_remoteendpoint $ip $connectip$ip } if {$count == 2} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port2$ip -u 2 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 2 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out2$ip -p $port_node] gen_axis_port2_endpoint $ip "axis_switch_out2$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_port2_remoteendpoint $ip $connectip$ip } if {$count == 3} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port3$ip -u 3 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 3 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out3$ip -p $port_node] gen_axis_port3_endpoint $ip "axis_switch_out3$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_port3_remoteendpoint $ip $connectip$ip } if {$count == 4} { set port_node [add_or_get_dt_node -n "port" -l axis_switch_port4$ip -u 4 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 4 int set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out4$ip -p $port_node] gen_axis_port4_endpoint $ip "axis_switch_out4$ip" hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference gen_axis_port4_remoteendpoint $ip $connectip$ip } } } proc gen_broad_frmbuf_wr_node {inputip outip drv_handle count} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set dts_file [current_dt_tree] set bus_node [add_or_get_bus_node $drv_handle $dts_file] set vcap [add_or_get_dt_node -n "vcapaxis_broad_out1$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string set inputip [split $inputip " "] set j 0 foreach ip $inputip { if {[llength $ip]} { if {$j < $count} { append dmasip "<&$ip 0>," " " } } incr j } append dmasip "<&$ip 0>" hsi::utils::add_new_dts_param $vcap "dmas" "$dmasip" string set prt "" for {set i 0} {$i < $count} {incr i} { append prt " " "port$i" } hsi::utils::add_new_dts_param $vcap "dma-names" $prt stringlist set vcap_ports_node [add_or_get_dt_node -n "ports" -l "vcap_portsaxis_broad_out1$drv_handle" -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set outip [split $outip " "] set b 0 for {set a 1} {$a <= $count} {incr a} { set vcap_port_node [add_or_get_dt_node -n "port" -l "vcap_portaxis_broad_out$a$drv_handle" -u "$b" -p "$vcap_ports_node"] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" $b int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l [lindex $outip $a] -p "$vcap_port_node"] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" axis_broad_out$a$drv_handle reference incr b } } proc get_connect_ip {ip intfpins} { dtg_verbose "get_con_ip:$ip pins:$intfpins" if {[llength $intfpins]== 0} { return } if {[llength $ip]== 0} { return } if {[string match -nocase [get_property IP_NAME [get_cells -hier $ip]] "axis_broadcaster"]} { gen_broadcaster $ip return } global connectip "" foreach intf $intfpins { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] if {[llength $connectip]} { if {[string match -nocase [get_property IP_NAME [get_cells -hier $connectip]] "axis_broadcaster"]} { gen_broadcaster $connectip break } if {[string match -nocase [get_property IP_NAME [get_cells -hier $connectip]] "axis_switch"]} { gen_axis_switch $connectip break } } set len [llength $connectip] if {$len > 1} { for {set i 0 } {$i < $len} {incr i} { set ip [lindex $connectip $i] if {[regexp -nocase "ila" $ip match]} { continue } set connectip "$ip" } } if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {[llength $ip_mem_handles]} { break } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] get_connect_ip $connectip $master_intf } } } return $connectip } proc get_in_connect_ip {ip intfpins} { dtg_verbose "get_in_con_ip:$ip pins:$intfpins" if {[llength $intfpins]== 0} { return } if {[llength $ip]== 0} { return } global connectip "" foreach intf $intfpins { set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf] if {[llength $connectip]} { set extip [get_property IP_NAME $connectip] if {[string match -nocase $extip "dfe_glitch_protect"] || [string match -nocase $extip "axi_interconnect"] || [string match -nocase $extip "axi_crossbar"]} { return } } set len [llength $connectip] if {$len > 1} { for {set i 0 } {$i < $len} {incr i} { set ip [lindex $connectip $i] if {[regexp -nocase "ila" $ip match]} { continue } set connectip "$ip" } } if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {[llength $ip_mem_handles]} { break } else { if {[string match -nocase [get_property IP_NAME $connectip] "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}] get_in_connect_ip $connectip $master_intf } } } return $connectip } proc get_broad_in_ip {ip} { dtg_verbose "get_braod_in_ip:$ip" if {[llength $ip]== 0} { return } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set connectip "" foreach intf $master_intf { set connect [get_connected_stream_ip [get_cells -hier $ip] $intf] foreach connectip $connect { if {[llength $connectip]} { if {[string match -nocase [get_property IP_NAME $connectip] "axis_broadcaster"]} { return $connectip } set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}] foreach intf $master_intf { set connectip [get_connected_stream_ip [get_cells -hier $connectip] $intf] set len [llength $connectip] if {$len > 1} { for {set i 0 } {$i < $len} {incr i} { set ip [lindex $connectip $i] if {[regexp -nocase "ila" $ip match]} { continue } set connectip "$ip" } } foreach connect $connectip { if {[string match -nocase [get_property IP_NAME $connectip] "axis_broadcaster"]} { return $connectip } } } if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master2_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}] foreach intf $master2_intf { set connectip [get_connected_stream_ip [get_cells -hier $connectip] $intf] if {[llength $connectip]} { if {[string match -nocase [get_property IP_NAME $connectip] "axis_broadcaster"]} { return $connectip } } } } if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {![llength $ip_mem_handles]} { set master3_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set connectip [get_connected_stream_ip [get_cells -hier $connectip] $master3_intf] } } } } } } } return $connectip } proc get_connected_stream_ip { ip_name intf_name } { set ip [::hsi::get_cells -hier $ip_name] if { [llength $ip] == 0 } { return "" } set intf [::hsi::get_intf_pins -of_objects $ip "$intf_name"] if { [llength $intf] == 0 } { return "" } set intf_type [common::get_property TYPE $intf] set intf_net [::hsi::get_intf_nets -of_objects $intf] if { [llength $intf_net] == 0 } { return "" } set connected_intf_pins [::hsi::utils::get_other_intf_pin $intf_net $intf] set connected_intf_pin [::hsi::utils::get_intf_pin_oftype $connected_intf_pins $intf_type 0] if { [llength $connected_intf_pin] } { set connected_ip [::hsi::get_cells -of_objects $connected_intf_pin] return $connected_ip } return "" } proc gen_dfx_reg_property {drv_handle dfx_node} { set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]] set reg "" set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] foreach mem_handle ${ip_mem_handles} { set base [string tolower [get_property BASE_VALUE $mem_handle]] set high [string tolower [get_property HIGH_VALUE $mem_handle]] set size [format 0x%x [expr {${high} - ${base} + 1}]] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string_is_empty $reg]} { if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { # check if base address is 64bit and split it as MSB and LSB if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } } else { set reg "0x0 $base 0x0 $size" } } else { set reg "$base $size" } } else { if {[string match -nocase $proctype "ps7_cortexa9"] || [string match -nocase $proctype "microblaze"]} { set index [check_base $reg $base $size] if {$index == "true"} { continue } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set index [check_64_base $reg $base $size] if {$index == "true"} { continue } } # ensure no duplication if {![regexp ".*${reg}.*" "$base $size" matched]} { if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set base1 "0x0 $base" set size1 "0x0 $size" if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set base1 "$low_base $high_base" } if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set size1 "$low_size $high_size" } set reg "$reg $base1 $size1" } else { set reg "$reg $base $size" } } } } hsi::utils::add_new_dts_param "$dfx_node" "reg" "$reg" intlist } proc gen_dfx_clk_property {drv_handle dts_file child_node dfx_node} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { return 0 } set clocks "" set axi 0 set is_clk_wiz 0 set is_pl_clk 0 set updat "" global bus_clk_list set clocknames "" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"]} { return } set clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}] set ip [get_property IP_NAME [get_cells -hier $drv_handle]] foreach clk $clk_pins { set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]] set valid_clk_list "clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9" set pl_clk "" set clkout "" foreach pin $pins { if {[lsearch $valid_clk_list $pin] >= 0} { set clkout $pin set is_clk_wiz 1 set periph [::hsi::get_cells -of_objects $pin] } } if {[llength $clkout]} { set number [regexp -all -inline -- {[0-9]+} $clkout] set clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set axi_clk "s_axi_aclk" foreach clk1 $clk_wiz { if {[regexp $axi_clk $clk1 match]} { set axi 1 } } if {[string match -nocase $axi "0"]} { dtg_warning "no s_axi_aclk for clockwizard IP block: \" $periph\"\n\r" set pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set clk_list "pl_clk*" set clk_pl "" set num "" foreach clk_wiz_pin $pins { set clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]] foreach pin $clk_wiz_pins { if {[regexp $clk_list $pin match]} { set clk_pl $pin } } } set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \" $drv_handle\"\n\r" continue } # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${child_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } if {![string match -nocase $axi "0"]} { switch $number { "1" { set peri "$periph 0" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "2" { set peri "$periph 1" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "3" { set peri "$periph 2" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "4" { set peri "$periph 3" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "5" { set peri "$periph 4" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "6" { set peri "$periph 5" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "7" { set peri "$periph 6" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } } } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } foreach pin $pins { if {[lsearch $clklist $pin] >= 0} { set pl_clk $pin set is_pl_clk 1 } } if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "zynqmp_clk 71" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "zynqmp_clk 72" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "zynqmp_clk 73" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "zynqmp_clk 74" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $is_clk_wiz "0"]&& [string match -nocase $is_pl_clk "0"]} { set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \"$drv_handle\"\n\r" continue } # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${child_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } append clocknames " " "$clk" set is_pl_clk 0 set is_clk_wiz 0 set axi 0 } hsi::utils::add_new_dts_param "${dfx_node}" "clock-names" "$clocknames" stringlist set ip [get_property IP_NAME [get_cells -hier $drv_handle]] set len [llength $updat] switch $len { "1" { set refs [lindex $updat 0] hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "2" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "3" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "4" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "5" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "6" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } "7" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]" hsi::utils::add_new_dts_param "${dfx_node}" "clocks" "$refs" reference } } } proc gen_axis_switch_clk_property {drv_handle dts_file node} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { return 0 } set clocks "" set axi 0 set is_clk_wiz 0 set is_pl_clk 0 set updat "" global bus_clk_list set clocknames "" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"]} { return } set clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}] set ip [get_property IP_NAME [get_cells -hier $drv_handle]] foreach clk $clk_pins { set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]] set valid_clk_list "clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9" set pl_clk "" set clkout "" foreach pin $pins { if {[lsearch $valid_clk_list $pin] >= 0} { set clkout $pin set is_clk_wiz 1 set periph [::hsi::get_cells -of_objects $pin] } } if {[llength $clkout]} { set number [regexp -all -inline -- {[0-9]+} $clkout] set clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set axi_clk "s_axi_aclk" foreach clk1 $clk_wiz { if {[regexp $axi_clk $clk1 match]} { set axi 1 } } if {[string match -nocase $axi "0"]} { dtg_warning "no s_axi_aclk for clockwizard IP block: \" $periph\"\n\r" set pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set clk_list "pl_clk*" set clk_pl "" set num "" foreach clk_wiz_pin $pins { set clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]] foreach pin $clk_wiz_pins { if {[regexp $clk_list $pin match]} { set clk_pl $pin } } } set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \" $drv_handle\"\n\r" continue } set bus_node [add_or_get_bus_node $drv_handle $dts_file] # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } if {![string match -nocase $axi "0"]} { switch $number { "1" { set peri "$periph 0" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "2" { set peri "$periph 1" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "3" { set peri "$periph 2" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "4" { set peri "$periph 3" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "5" { set peri "$periph 4" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "6" { set peri "$periph 5" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "7" { set peri "$periph 6" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } } } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } foreach pin $pins { if {[lsearch $clklist $pin] >= 0} { set pl_clk $pin set is_pl_clk 1 } } if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "zynqmp_clk 71" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "zynqmp_clk 72" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "zynqmp_clk 73" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "zynqmp_clk 74" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $is_clk_wiz "0"]&& [string match -nocase $is_pl_clk "0"]} { set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \"$drv_handle\"\n\r" continue } set bus_node [add_or_get_bus_node $drv_handle $dts_file] # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } append clocknames " " "$clk" set is_pl_clk 0 set is_clk_wiz 0 set axi 0 } hsi::utils::add_new_dts_param "${node}" "clock-names" "$clocknames" stringlist set ip [get_property IP_NAME [get_cells -hier $drv_handle]] set len [llength $updat] switch $len { "1" { set refs [lindex $updat 0] hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "2" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "3" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "4" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "5" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "6" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } "7" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]" hsi::utils::add_new_dts_param "${node}" "clocks" "$refs" reference } } } proc gen_clk_property {drv_handle} { if {[is_ps_ip $drv_handle]} { return 0 } set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { return 0 } set clocks "" set axi 0 set is_clk_wiz 0 set is_pl_clk 0 set updat "" global bus_clk_list set clocknames "" dtg_verbose "gen_clk_property:$drv_handle" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"]} { return } set clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I}] dtg_verbose "clk_pins:$clk_pins" set ip [get_property IP_NAME [get_cells -hier $drv_handle]] set ignore_list "lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2 mrmac" if {[lsearch $ignore_list $ip] >= 0 } { return 0 } if {[string match -nocase $ip "vcu"]} { set clk_pins "pll_ref_clk s_axi_lite_aclk" } foreach clk $clk_pins { set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]] set valid_clk_list "clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9" set pl_clk "" set clkout "" foreach pin $pins { if {[lsearch $valid_clk_list $pin] >= 0} { set clkout $pin set is_clk_wiz 1 set periph [::hsi::get_cells -of_objects $pin] } } if {[llength $clkout]} { set number [regexp -all -inline -- {[0-9]+} $clkout] set clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set axi_clk "s_axi_aclk" foreach clk1 $clk_wiz { if {[regexp $axi_clk $clk1 match]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $periph] if {[llength $ip_mem_handles]} { set axi 1 } } } if {[string match -nocase $axi "0"]} { dtg_warning "no s_axi_aclk for clockwizard IP block: \" $periph\"\n\r" set pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set clk_list "pl_clk*" set clk_pl "" set num "" foreach clk_wiz_pin $pins { set clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]] foreach pin $clk_wiz_pins { if {[regexp $clk_list $pin match]} { set clk_pl $pin } } } if {[llength $clk_pl]} { set num [regexp -all -inline -- {[0-9]+} $clk_pl] } set RpRm [get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm "" RpRm if {[llength $RpRm]} { set dts_file "pl-partial-$RpRm.dtsi" } else { set dts_file "pl.dtsi" } set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \" $drv_handle\"\n\r" continue } # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] if {[llength $RpRm]} { set misc_clk_node [add_or_get_dt_node -n "misc_clk$RpRm${bus_clk_cnt}" -l "misc_clk_$RpRm${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] } else { set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] } set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] if {[llength $RpRm]} { set updat [lappend updat misc_clk_$RpRm${bus_clk_cnt}] } else { set updat [lappend updat misc_clk_${bus_clk_cnt}] } if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } if {![string match -nocase $axi "0"]} { switch $number { "1" { set peri "$periph 0" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "2" { set peri "$periph 1" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "3" { set peri "$periph 2" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "4" { set peri "$periph 3" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "5" { set peri "$periph 4" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "6" { set peri "$periph 5" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "7" { set peri "$periph 6" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } } } } if {[string match -nocase $proctype "psu_cortexa53"] } { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } elseif {[string match -nocase $proctype "ps7_cortexa9"]} { set clklist "FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3" } if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { if {[string match -nocase $proctype "psv_cortexa72"]} { set versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}] } else { set versal_periph [get_cells -hier -filter {IP_NAME == psx_wizard}] } set ver [get_comp_ver $versal_periph] if {$ver >= 3.0} { set clklist "pl0_ref_clk pl1_ref_clk pl2_ref_clk pl3_ref_clk" } else { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } } foreach pin $pins { if {[lsearch $clklist $pin] >= 0} { set pl_clk $pin set is_pl_clk 1 } } if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { if {[string match -nocase $proctype "psv_cortexa72"]} { set versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}] } else { set versal_periph [get_cells -hier -filter {IP_NAME == psx_wizard}] } set ver [get_comp_ver $versal_periph] if {$ver >= 3.0} { switch $pl_clk { "pl0_ref_clk" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl1_ref_clk" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl2_ref_clk" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl3_ref_clk" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "Clock pin \"$clk\" of IP block \"$drv_handle\" is not connected to any of the pl_clk\"\n\r" } } } else { switch $pl_clk { "pl_clk0" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "Clock pin \"$clk\" of IP block \"$drv_handle\" is not connected to any of the pl_clk\"n\r" } } } } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "zynqmp_clk 71" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "zynqmp_clk 72" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "zynqmp_clk 73" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "zynqmp_clk 74" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "Clock pin \"$clk\" of IP block \"$drv_handle\" is not connected to any of the pl_clk\"\n\r" } } } if {[string match -nocase $proctype "ps7_cortexa9"]} { switch $pl_clk { "FCLK_CLK0" { set pl_clk0 "clkc 15" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "FCLK_CLK1" { set pl_clk1 "clkc 16" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "FCLK_CLK2" { set pl_clk2 "clkc 17" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "FCLK_CLK3" { set pl_clk3 "clkc 18" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "Clock pin \"$clk\" of IP block \"$drv_handle\" is not connected to any of the pl_clk\"\n\r" } } } if {[string match -nocase $is_clk_wiz "0"]&& [string match -nocase $is_pl_clk "0"]} { set RpRm [get_rp_rm_for_drv $drv_handle] regsub -all { } $RpRm "" RpRm if {[llength $RpRm]} { set dts_file "pl-partial-$RpRm.dtsi" } else { set dts_file "pl.dtsi" } set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL of IP block: \"$drv_handle\"\n\r" continue } # if clk_freq is float convert it to int set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] if {[llength $RpRm]} { set misc_clk_node [add_or_get_dt_node -n "misc_clk_$RpRm${bus_clk_cnt}" -l "misc_clk_$RpRm${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] } else { set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] } set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] if {[llength $RpRm]} { set updat [lappend updat misc_clk_$RpRm${bus_clk_cnt}] } else { set updat [lappend updat misc_clk_${bus_clk_cnt}] } if {[string match -nocase $proctype "psu_cortexa53"]} { gen_fixed_factor_clk_node ${misc_clk_node} ${clk_freq} } else { hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } } append clocknames " " "$clk" set is_pl_clk 0 set is_clk_wiz 0 set axi 0 } set ip [get_property IP_NAME [get_cells -hier $drv_handle]] if {[string match -nocase $ip "dfx_axi_shutdown_manager"]} { # DFX axi shutdown manager driver expecting aclk as clock name # but IP has clk pin name. We cannot update this in Driver as it # breaks the backward compatiblity. so rename clk -> aclk set clocknames [string map {clk aclk} $clocknames] } set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist if {[string match -nocase $ip "vcu"]} { set vcu_label $drv_handle set vcu_clk1 "$drv_handle 0" set updat [lappend updat $vcu_clk1] set vcu_clk2 "$drv_handle 1" set updat [lappend updat $vcu_clk2] set vcu_clk3 "$drv_handle 2" set updat [lappend updat $vcu_clk3] set vcu_clk4 "$drv_handle 3" set updat [lappend updat $vcu_clk4] set len [llength $updat] set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]" set_drv_prop $drv_handle "clocks" "$refs" reference return } set len [llength $updat] switch $len { "1" { set refs [lindex $updat 0] set_drv_prop $drv_handle "clocks" "$refs" reference } "2" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]" set_drv_prop $drv_handle "clocks" "$refs" reference } "3" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]" set_drv_prop $drv_handle "clocks" "$refs" reference } "4" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]" set_drv_prop $drv_handle "clocks" "$refs" reference } "5" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]" set_drv_prop $drv_handle "clocks" "$refs" reference } "6" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]" set_drv_prop $drv_handle "clocks" "$refs" reference } "7" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]" set_drv_prop $drv_handle "clocks" "$refs" reference } "8" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]" set_drv_prop $drv_handle "clocks" "$refs" reference } "9" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]" set_drv_prop $drv_handle "clocks" "$refs" reference } "10" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]" set_drv_prop $drv_handle "clocks" "$refs" reference } "11" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]" set_drv_prop $drv_handle "clocks" "$refs" reference } "12" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]" set_drv_prop $drv_handle "clocks" "$refs" reference } "13" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]" set_drv_prop $drv_handle "clocks" "$refs" reference } "14" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]" set_drv_prop $drv_handle "clocks" "$refs" reference } "15" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]>, <&[lindex $updat 14]" set_drv_prop $drv_handle "clocks" "$refs" reference } "16" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]>, <&[lindex $updat 4]>, <&[lindex $updat 5]>, <&[lindex $updat 6]>, <&[lindex $updat 7]>, <&[lindex $updat 8]>, <&[lindex $updat 9]>, <&[lindex $updat 10]>, <&[lindex $updat 11]>, <&[lindex $updat 12]>, <&[lindex $updat 13]>, <&[lindex $updat 14]>, <&[lindex $updat 15]" set_drv_prop $drv_handle "clocks" "$refs" reference } } } proc overwrite_clknames {clknames drv_handle} { set_drv_prop $drv_handle "clock-names" $clknames stringlist } proc get_comp_ver {drv_handle} { set slave [get_cells -hier ${drv_handle}] set vlnv [split [get_property VLNV $slave] ":"] set ver [lindex $vlnv 3] return $ver } proc get_comp_str {drv_handle} { set slave [get_cells -hier ${drv_handle}] set vlnv [split [get_property VLNV $slave] ":"] set ver [lindex $vlnv 3] set name [lindex $vlnv 2] set ver [lindex $vlnv 3] set comp_prop "xlnx,${name}-${ver}" regsub -all {_} $comp_prop {-} comp_prop return $comp_prop } proc get_intr_type {intc_name ip_name port_name} { set intc [get_cells -hier $intc_name] set ip [get_cells -hier $ip_name] if {[llength $intc] == 0 && [llength $ip] == 0} { return -1 } if {[llength $intc] == 0} { return -1 } set intr_pin [get_pins -of_objects $ip $port_name] set sensitivity "" if {[llength $intr_pin] >= 1} { # TODO: check with HSM dev and see if this is a bug set sensitivity [get_property SENSITIVITY $intr_pin] } set intc_type [get_property IP_NAME $intc ] set valid_intc_list "ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic" if {[lsearch -nocase $valid_intc_list $intc_type] >= 0} { if {[string match -nocase $sensitivity "EDGE_FALLING"]} { return 2; } elseif {[string match -nocase $sensitivity "EDGE_RISING"]} { return 1; } elseif {[string match -nocase $sensitivity "LEVEL_HIGH"]} { return 4; } elseif {[string match -nocase $sensitivity "LEVEL_LOW"]} { return 8; } } else { # Follow the openpic specification if {[string match -nocase $sensitivity "EDGE_FALLING"]} { return 3; } elseif {[string match -nocase $sensitivity "EDGE_RISING"]} { return 0; } elseif {[string match -nocase $sensitivity "LEVEL_HIGH"]} { return 2; } elseif {[string match -nocase $sensitivity "LEVEL_LOW"]} { return 1; } } return -1 } proc get_drv_conf_prop_list {ip_name {def_pattern "CONFIG.*"}} { set drv_handle [get_ip_handler $ip_name] if {[catch {set rt [list_property -regexp $drv_handle ${def_pattern}]} msg]} { set rt "" } return $rt } proc get_ip_conf_prop_list {ip_name {def_pattern "CONFIG.*"}} { set ip [get_cells -hier $ip_name] if {[catch {set rt [list_property -regexp $ip ${def_pattern}]} msg]} { set rt "" } return $rt } proc get_ip_handler {ip_name} { # check if it is processor if {[string equal -nocase [get_sw_processor] $ip_name]} { return [get_sw_processor] } # check if it is the target processor # get it from drvers return [get_drivers $ip_name] } proc set_drv_prop args { set drv_handle [lindex $args 0] set prop_name [lindex $args 1] set value [lindex $args 2] # check if property exists if not create it set list [get_drv_conf_prop_list $drv_handle] if {[lsearch -glob ${list} ${prop_name}] < 0} { hsi::utils::add_new_property $drv_handle $prop_name string "$value" } if {[llength $args] >= 4} { set type [lindex $args 3] set_property ${prop_name} $value $drv_handle set prop [get_comp_params ${prop_name} $drv_handle] set_property CONFIG.TYPE $type $prop } else { set_property ${prop_name} $value $drv_handle } return 0 } proc set_drv_prop_if_empty args { set drv_handle [lindex $args 0] set prop_name [lindex $args 1] set value [lindex $args 2] set cur_prop_value [get_property CONFIG.$prop_name $drv_handle] if {[string_is_empty $cur_prop_value] == 0} { dtg_debug "$drv_handle $prop_name property is not empty, current value is '$cur_prop_value'" return -1 } if {[llength $args] >= 4} { set type [lindex $args 3] set_drv_prop $drv_handle $prop_name $value $type } else { set_drv_prop $drv_handle $prop_name $value } return 0 } proc gen_mb_interrupt_property {cpu_handle {intr_port_name ""}} { # generate interrupts and interrupt-parent properties for soft IP proc_called_by if {[is_ps_ip $cpu_handle]} { return 0 } set slave [get_cells -hier ${cpu_handle}] set intc "" if {[string_is_empty $intr_port_name]} { set intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}] } set cpin [hsi::utils::get_interrupt_sources [get_cells -hier $cpu_handle]] set intc [get_cells -of_objects $cpin] if { [::hsi::utils::is_intr_cntrl $intc] != 1 } { set intf_pins [::hsi::get_intf_pins -of_objects $intc] foreach intp $intf_pins { set connectip [get_connected_stream_ip [get_cells -hier $intc] $intp] if { [::hsi::utils::is_intr_cntrl $connectip] == 1 } { set intc $connectip } } } if {[string_is_empty $intc]} { error "no interrupt controller found" } set_drv_prop $cpu_handle interrupt-handle $intc reference } proc get_interrupt_parent { periph_name intr_pin_name } { lappend intr_cntrl if { [llength $intr_pin_name] == 0 } { return $intr_cntrl } if { [llength $periph_name] != 0 } { set periph [::hsi::get_cells -hier -filter "NAME==$periph_name"] if { [llength $periph] == 0 } { return $intr_cntrl } set intr_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intr_pin_name"] if { [llength $intr_pin] == 0 } { return $intr_cntrl } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "I"] } { return $intr_cntrl } } else { set intr_pin [::hsi::get_ports $intr_pin_name] if { [llength $intr_pin] == 0 } { return $intr_cntrl } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "O"] } { return $intr_cntrl } } set intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin] foreach intr_sink $intr_sink_pins { set sink_periph [lindex [::hsi::get_cells -of_objects $intr_sink] 0] if { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } { lappend intr_cntrl $sink_periph } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlconcat"] } { set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph "dout"]] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlslice"] } { set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph "Dout"]] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "util_reduced_logic"] } { set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph "Res"]] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "dfx_decoupler"] } { set intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}] set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph "$intr"]] } elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "util_ff"]} { set intr_cntrl [list {*}$intr_cntrl {*}[::hsi::utils::get_connected_intr_cntrl $sink_periph "Q"]] } } return $intr_cntrl } proc gen_interrupt_property {drv_handle {intr_port_name ""}} { # generate interrupts and interrupt-parent properties for soft IP proc_called_by if {[is_ps_ip $drv_handle]} { return 0 } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set slave [get_cells -hier ${drv_handle}] set intr_id -1 set intc "" set intr_info "" set intc_names "" set intr_par "" set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } if {[string_is_empty $intr_port_name]} { if {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"]} { set val [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}] set intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT&&DIRECTION==O}] set single [get_property CONFIG.C_IRQ_CONNECTION [get_cells -hier $slave]] if {$single == 0} { dtg_warning "The axi_intc Interrupt Output connection is Bus. Change it to Single" } } else { set intr_port_name [get_pins -of_objects $slave -filter {TYPE==INTERRUPT}] } } # TODO: consolidation with get_intr_id proc foreach pin ${intr_port_name} { set connected_intc [get_intr_cntrl_name $drv_handle $pin] regsub -all {\{|\}} $connected_intc "" connected_intc if {[llength $connected_intc] == 0 } { if {![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"]} { dtg_warning "Interrupt pin \"$pin\" of IP block: \"$drv_handle\" is not connected to any interrupt controller\n\r" } continue } set connected_intc [get_cells -hier $connected_intc] set connected_intc_name [get_property IP_NAME $connected_intc] set valid_gpio_list "ps7_gpio axi_gpio" set valid_cascade_proc "microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78" # check whether intc is gpio or other if {[lsearch -nocase $valid_gpio_list $connected_intc_name] >= 0} { set cur_intr_info "" generate_gpio_intr_info $connected_intc $drv_handle $pin } else { set intc [get_interrupt_parent $drv_handle $pin] if { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0 } { set pins [::hsi::get_pins -of_objects [::hsi::get_cells -hier -filter "NAME==$drv_handle"] -filter "NAME==irq"] set intc [get_interrupt_parent $drv_handle $pins] } else { set intc [get_interrupt_parent $drv_handle $pin] } if {[string_is_empty $intc] == 1} { dtg_warning "Interrupt pin \"$pin\" of IP block: \"$drv_handle\" is not connected\n\r" continue } set ip_name $intc if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || \ [string match -nocase $proctype "psx_cortexa78"] || [string match -nocase $proctype "microblaze"]} { if {[llength $intc] > 1} { foreach intr_cntr $intc { if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } { set intc $intr_cntr } } } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psu_cortexa53"] && [string match -nocase $intc "axi_intc"] } { set intc [::hsi::utils::get_interrupt_parent $drv_handle $pin] } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psv_cortexa72"] && [string match -nocase $intc "axi_intc"] } { set intc [get_interrupt_parent $drv_handle $pin] } if {[string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "psx_cortexa78"] && [string match -nocase $intc "axi_intc"] } { set intc [get_interrupt_parent $drv_handle $pin] } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { if { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"] } { set intr_id [get_psu_interrupt_id $drv_handle "irq"] } else { set intr_id [get_psu_interrupt_id $drv_handle $pin] } } if { [string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "ps7_cortexa9"]} { if { [string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"] } { set intr_id [::hsi::utils::get_interrupt_id $drv_handle "irq"] } else { set intr_id [::hsi::utils::get_interrupt_id $drv_handle $pin] } } if { [string match -nocase [get_property IP_NAME [get_cells -hier [get_sw_processor]]] "microblaze"]} { if {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"] } { set intr_id [get_psu_interrupt_id $drv_handle "irq"] } else { set intr_id [get_psu_interrupt_id $drv_handle $pin] } } if {[string match -nocase $intr_id "-1"] && ![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"]} { continue } set intr_type [get_intr_type $intc $slave $pin] if {[string match -nocase $intr_type "-1"]} { continue } set cur_intr_info "" set valid_intc_list "ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic" global intrpin_width if { [string match -nocase $proctype "ps7_cortexa9"] } { if {[string match "[get_property IP_NAME $intc]" "ps7_scugic"] } { if {$intr_id > 32} { set intr_id [expr $intr_id - 32] } set cur_intr_info "0 $intr_id $intr_type" } elseif {[string match "[get_property IP_NAME $intc]" "axi_intc"] } { set cur_intr_info "$intr_id $intr_type" } } elseif {[string match -nocase $intc "psu_acpu_gic"] \ || [string match -nocase [get_property IP_NAME $intc] "psv_acpu_gic"] \ || [string match -nocase [get_property IP_NAME $intc] "psx_acpu_gic"]} { set cur_intr_info "0 $intr_id $intr_type" for { set i 1 } {$i < $intrpin_width} {incr i} { set intr_id_inc [expr $intr_id + $i] append cur_intr_info ">, <0 $intr_id_inc $intr_type" } } else { set cur_intr_info "$intr_id $intr_type" for { set i 1 } {$i < $intrpin_width} {incr i} { set intr_id_inc [expr $intr_id + $i] append cur_intr_info ">, <$intr_id_inc $intr_type" } } if {[string_is_empty $intr_info]} { set intr_info "$cur_intr_info" } else { append intr_info " " $cur_intr_info } } append intr_names " " "$pin" append intr_par " " "$intc" lappend intc_names "$intc" "$cur_intr_info" } if {[llength $intr_par] > 1 } { set int_ext 0 set intc0 [lindex $intr_par 0] for {set i 1} {$i < [llength $intr_par]} {incr i} { set intc [lindex $intr_par $i] if {![string match -nocase $intc0 $intc]} { set int_ext 1 } } if {$int_ext == 1} { set intc_names [string map {psu_acpu_gic gic} $intc_names] set ref [lindex $intc_names 0] append ref " [lindex $intc_names 1]>, <&[lindex $intc_names 2] [lindex $intc_names 3]>, <&[lindex $intc_names 4] [lindex $intc_names 5]>,<&[lindex $intc_names 6] [lindex $intc_names 7]>, <&[lindex $intc_names 8] [lindex $intc_names 9]" if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "v_hdmi_tx_ss"] \ || [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "v_hdmi_txss1"]} { set_drv_prop_if_empty $drv_handle "interrupts-extended" $ref reference } } } if {[string_is_empty $intr_info]} { return -1 } global drv_handlers_mapping if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "vdu"]} { dict lappend drv_handlers_mapping $drv_handle "interrupts" "$intr_info" } else { set_drv_prop $drv_handle interrupts $intr_info intlist } if {[string_is_empty $intc]} { return -1 } set intc [ps_node_mapping $intc label] if { $intc in { "psu_acpu_gic" "psv_acpu_gic" "psx_acpu_gic" }} { set intc "gic" } set add_intr_parent "" if { $intc == "gic" && ([string match -nocase $proctype "psu_cortexa53"] \ || [string match -nocase $proctype "psv_cortexa72"] \ || [string match -nocase $proctype "psx_cortexa78"])} { set add_intr_parent "1" } elseif { $intc == "intc" && [string match -nocase $proctype "ps7_cortexa9" ] } { set add_intr_parent "1" } else { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $intc] if {$index != -1 } { set add_intr_parent "1" } } if {[llength $add_intr_parent]} { if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "vdu"]} { dict lappend drv_handlers_mapping $drv_handle "interrupt-parent" "$intc" } else { set_drv_prop $drv_handle interrupt-parent $intc reference } } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"]} { set msi_rx_pin_en [get_property CONFIG.msi_rx_pin_en [get_cells -hier $drv_handle]] if {[string match -nocase $msi_rx_pin_en "true"]} { set_drv_prop_if_empty $drv_handle "interrupt-names" $intr_names stringlist } } elseif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "vdu"]} { dict lappend drv_handlers_mapping $drv_handle "interrupt-names" "$intr_names" } else { set_drv_prop_if_empty $drv_handle "interrupt-names" $intr_names stringlist } } proc gen_reg_property {drv_handle {skip_ps_check ""}} { proc_called_by if {[string_is_empty $skip_ps_check]} { if {[is_ps_ip $drv_handle]} { return 0 } } set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]] if { $ip_name in { "xxv_ethernet" "ddr4" "mrmac" "dcmac" "vdu" }} { return } set reg "" #set ip_skip_list "ddr4_*" set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] set base_val 0 set high_val 0 set size_val 0 foreach mem_handle ${ip_mem_handles} { if {[string match -nocase $ip_name "ai_engine"]} { set base [string tolower [get_property BASE_VALUE $mem_handle]] set high [string tolower [get_property HIGH_VALUE $mem_handle]] set size [format 0x%x [expr {${high} - ${base} + 1}]] if { $base_val == 0 } { set base_val $base } if { $high > $high_val } { set high_val $high } } } foreach mem_handle ${ip_mem_handles} { # if {![regexp $ip_skip_list $mem_handle match]} { set base [string tolower [get_property BASE_VALUE $mem_handle]] set ips [get_cells -hier -filter {IP_NAME == "mrmac"}] if {[llength $ips]} { if {[string match -nocase $base "0xa4010000"] && $ip_name == "axi_gpio"} { return } } set high [string tolower [get_property HIGH_VALUE $mem_handle]] set size [format 0x%x [expr {${high} - ${base} + 1}]] if {[string match -nocase $ip_name "ai_engine"]} { set ip [get_cells -hier $drv_handle] set high $high_val set base $base_val set size [format 0x%x [expr {${high_val} - ${base} + 1}]] } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string_is_empty $reg]} { if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { # check if base address is 64bit and split it as MSB and LSB if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } } else { set reg "0x0 $base 0x0 $size" } } else { set reg "$base $size" } } else { if {[string match -nocase $proctype "ps7_cortexa9"] || [string match -nocase $proctype "microblaze"]} { set index [check_base $reg $base $size] if {$index == "true"} { continue } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set index [check_64_base $reg $base $size] if {$index == "true"} { continue } } # ensure no duplication if {![regexp ".*${reg}.*" "$base $size" matched]} { if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set base1 "0x0 $base" set size1 "0x0 $size" if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set base1 "$low_base $high_base" } if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set size1 "$low_size $high_size" } set reg "$reg $base1 $size1" } else { set reg "$reg $base $size" } } } # } } set_drv_prop_if_empty $drv_handle reg $reg intlist } proc check_64_base {reg base size} { set high_base 0xdeadbeef set low_base 0 if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] } set len [llength $reg] switch $len { "4" { set base_index0 [lindex $reg 0] set base_index1 [lindex $reg 1] if {$high_base != 0xdeadbeef} { if {$base_index0 == $low_base && $base_index1 == $high_base} { return true } } else { if {$base_index1 == $base} { return true } } } "8" { set base_index0 [lindex $reg 0] set base_index1 [lindex $reg 1] set base_index4 [lindex $reg 4] set base_index5 [lindex $reg 5] if {$high_base != 0xdeadbeef} { if {$base_index0 == $low_base && $base_index1 == $high_base} { return true } if {$base_index4 == $low_base && $base_index5 == $high_base} { return true } } else { if {$base_index1 == $base} { return true } if {$base_index5 == $base} { return true } } } "12" { set base_index0 [lindex $reg 0] set base_index1 [lindex $reg 1] set base_index4 [lindex $reg 4] set base_index5 [lindex $reg 5] set base_index8 [lindex $reg 8] set base_index9 [lindex $reg 9] if {$high_base != 0xdeadbeef} { if {$base_index0 == $low_base && $base_index1 == $high_base} { return true } if {$base_index4 == $low_base && $base_index5 == $high_base} { return true } if {$base_index8 == $low_base && $base_index9 == $high_base} { return true } } else { if {$base_index1 == $base} { return true } if {$base_index5 == $base} { return true } if {$base_index9 == $base} { return true } } } } } proc check_base {reg base size} { set len [llength $reg] switch $len { "2" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] if {$base_index0 == $base || $size_index0 == $size} { return true } } "4" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] if {$base_index0 == $base || $base_index1 == $base} { if {$size_index0 == $size || $size_index1 == $size} { return true } } } "6" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size} { return true } } } "8" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] set base_index3 [lindex $reg 6] set size_index3 [lindex $reg 7] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size} { return true } } } "10" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] set base_index3 [lindex $reg 6] set size_index3 [lindex $reg 7] set base_index4 [lindex $reg 8] set size_index4 [lindex $reg 9] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size} { return true } } } "12" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] set base_index3 [lindex $reg 6] set size_index3 [lindex $reg 7] set base_index4 [lindex $reg 8] set size_index4 [lindex $reg 9] set base_index5 [lindex $reg 10] set size_index5 [lindex $reg 11] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size} { return true } } } "14" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] set base_index3 [lindex $reg 6] set size_index3 [lindex $reg 7] set base_index4 [lindex $reg 8] set size_index4 [lindex $reg 9] set base_index5 [lindex $reg 10] set size_index5 [lindex $reg 11] set base_index6 [lindex $reg 12] set size_index6 [lindex $reg 13] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base || $base_index6 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size || $size_index6 == $size} { return true } } } "16" { set base_index0 [lindex $reg 0] set size_index0 [lindex $reg 1] set base_index1 [lindex $reg 2] set size_index1 [lindex $reg 3] set base_index2 [lindex $reg 4] set size_index2 [lindex $reg 5] set base_index3 [lindex $reg 6] set size_index3 [lindex $reg 7] set base_index4 [lindex $reg 8] set size_index4 [lindex $reg 9] set base_index5 [lindex $reg 10] set size_index5 [lindex $reg 11] set base_index6 [lindex $reg 12] set size_index6 [lindex $reg 13] set base_index7 [lindex $reg 14] set size_index7 [lindex $reg 15] if {$base_index0 == $base || $base_index1 == $base || $base_index2 == $base || $base_index3 == $base || $base_index4 == $base || $base_index5 == $base || $base_index6 == $base || $base_index7 == $base} { if {$size_index0 == $size || $size_index1 == $size || $size_index2 == $size || $size_index3 == $size || $size_index4 == $size || $size_index5 == $size || $size_index6 == $size || $size_index7 == $size} { return true } } } } } proc gen_compatible_property {drv_handle} { proc_called_by if {[is_ps_ip $drv_handle]} { return 0 } set reg "" set slave [get_cells -hier ${drv_handle}] set vlnv [split [get_property VLNV $slave] ":"] set name [lindex $vlnv 2] set ver [lindex $vlnv 3] set comp_prop "xlnx,${name}-${ver}" regsub -all {_} $comp_prop {-} comp_prop set_drv_prop_if_empty $drv_handle compatible $comp_prop stringlist } proc is_property_set {value} { if {[string compare -nocase $value "true"] == 0} { return 1 } return 0 } proc ip2drv_prop {ip_name ip_prop_name} { set drv_handle [get_ip_handler $ip_name] set ip [get_cells -hier $ip_name] set emac [get_property IP_NAME $ip] if { $emac == "axi_ethernet"} { # remove CONFIG. set prop [get_property $ip_prop_name [get_cells -hier $ip_name]] set drv_prop_name $ip_prop_name regsub -all {CONFIG.} $drv_prop_name {xlnx,} drv_prop_name regsub -all {_} $drv_prop_name {-} drv_prop_name set drv_prop_name [string tolower $drv_prop_name] add_cross_property $ip $ip_prop_name $drv_handle ${drv_prop_name} hexint return } # remove CONFIG.C_ set drv_prop_name $ip_prop_name regsub -all {CONFIG.C_} $drv_prop_name {xlnx,} drv_prop_name regsub -all {_} $drv_prop_name {-} drv_prop_name set drv_prop_name [string tolower $drv_prop_name] add_cross_property $ip $ip_prop_name $drv_handle ${drv_prop_name} hexint } proc gen_drv_prop_from_ip {drv_handle} { # check if we should generating the ip properties or not set gen_ip_prop [get_drv_conf_prop_list $drv_handle "CONFIG.dtg.ip_params"] if {[string_is_empty $gen_ip_prop]} { return 0 } set prop_name_list [default_parameters $drv_handle] foreach prop_name ${prop_name_list} { ip2drv_prop $drv_handle $prop_name } } # based on libgen dtg proc default_parameters {ip_handle {dont_generate ""}} { set par_handles [get_ip_conf_prop_list $ip_handle "CONFIG.C_.*"] set valid_prop_names {} foreach par $par_handles { regsub -all {CONFIG.} $par {} tmp_par # Ignore some parameters that are always handled specially switch -glob $tmp_par { $dont_generate - \ "INSTANCE" - \ "C_INSTANCE" - \ "*BASEADDR" - \ "*HIGHADDR" - \ "C_SPLB*" - \ "C_DPLB*" - \ "C_IPLB*" - \ "C_PLB*" - \ "M_AXI*" - \ "C_M_AXI*" - \ "S_AXI_ADDR_WIDTH" - \ "C_S_AXI_ADDR_WIDTH" - \ "S_AXI_DATA_WIDTH" - \ "C_S_AXI_DATA_WIDTH" - \ "S_AXI_ACLK_FREQ_HZ" - \ "C_S_AXI_ACLK_FREQ_HZ" - \ "S_AXI_LITE*" - \ "C_S_AXI_LITE*" - \ "S_AXI_PROTOCOL" - \ "C_S_AXI_PROTOCOL" - \ "*INTERCONNECT_?_AXI*" - \ "*S_AXI_ACLK_PERIOD_PS" - \ "M*_AXIS*" - \ "C_M*_AXIS*" - \ "S*_AXIS*" - \ "C_S*_AXIS*" - \ "PRH*" - \ "C_FAMILY" - \ "FAMILY" - \ "*CLK_FREQ_HZ" - \ "*ENET_SLCR_*Mbps_DIV?" - \ "HW_VER" { } \ default { lappend valid_prop_names $par } } } return $valid_prop_names } proc ps7_reset_handle {drv_handle reset_pram conf_prop} { set src_ip -1 set value -1 set ip [get_cells -hier $drv_handle] set value [get_property ${reset_pram} $ip] # workaround for reset not been selected and show as "" $value "" value if {[llength $value]} { # if MIO, assume gpio0 (bad assumption as this needs to match zynq-7000.dtsi) if {[regexp "^MIO" $value matched]} { # switch with kernel version set kernel_ver [get_property CONFIG.kernel_version [get_os]] switch -exact $kernel_ver { default { set src_ip "gpio0" } } } regsub -all "MIO( |)" $value "" value if {$src_ip != "-1"} { if {$value != "-1" && [llength $value] !=0} { regsub -all "CONFIG." $conf_prop "" conf_prop set_drv_property $drv_handle ${conf_prop} "$src_ip $value 0" reference } } } else { dtg_warning "$drv_handle: No reset found" return -1 } } proc gen_peripheral_nodes {drv_handle {node_only ""}} { # Check if the peripheral is in Secure or Non-secure zone if {[check_ip_trustzone_state $drv_handle] == 1} { return } set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set status_enable_flow 0 set ip [get_cells -hier $drv_handle] # TODO: check if the base address is correct set unit_addr [get_baseaddr ${ip} no_prefix] if { [string equal $unit_addr "-1"] } { return 0 } set label $drv_handle set label_len [string length $label] if {$label_len >= 31} { # As per the device tree specification the label length should be maximum of 31 characters dtg_verbose "the label \"$label\" length is $label_len characters which is greater than default 31 characters as per DT SPEC...user need to fix the label\n\r" } set dev_type [get_property CONFIG.dev_type $drv_handle] if {[string_is_empty $dev_type] == 1} { set dev_type [get_property IP_NAME [get_cell -hier $ip]] } set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { set ip_type [get_property IP_NAME $ip] # For psv_cpm BASE_VALUE is different than the node unitaddr from versal.dtsi # So reading proper xsct configs to add status okay if {[string match -nocase $ip_type "psv_cpm"]} { set rev_num -1 set cpm_unit_addr "" foreach drv [get_cells -hier -filter IP_NAME==psv_cpm] { if {![regexp "pspmc.*" "$drv" match]} { set rev_num [llength [get_cells -hier $drv -filter CONFIG.CPM_REVISION_NUMBER==1]] } } #for CPM4 designs the revision number will be 0 #for CPM5 designs the revision number will be 1 if {$rev_num == 0} { # CONFIG.CPM_SLCR is for cpm4 set cpm_unit_addr [get_property CONFIG.CPM_SLCR [get_cells -hier $ip]] } elseif {$rev_num == 1} { # CONFIG.CPM5_SLCR_ADDR is for cpm5 set cpm_unit_addr [get_property CONFIG.CPM5_SLCR_ADDR [get_cells -hier $ip]] } if {[llength $cpm_unit_addr]} { set unit_addr [string tolower $cpm_unit_addr] regsub -all {^0x} $unit_addr {} unit_addr } } if {[string match -nocase $ip_type "psv_cpm_slcr"]} { set versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}] if {[llength $versal_periph]} { set avail_param [list_property [get_cells -hier $versal_periph]] if {[lsearch -nocase $avail_param "CONFIG.CPM_PCIE0_PORT_TYPE"] >= 0} { set val [get_property CONFIG.CPM_PCIE0_PORT_TYPE [get_cells -hier $versal_periph]] if {[string match -nocase $val "Root_Port_of_PCI_Express_Root_Complex"]} { #For Root port device tree entry should be set Okay } else { # For Non-Root port(PCI_Express_Endpoint_device) there should not be any device tree entry in DTS return 0 } } } } } # TODO: more ignore ip list? set ip_type [get_property IP_NAME $ip] set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set ignore_list "lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2" } else { set ignore_list "lmb_bram_if_cntlr PERIPHERAL axi_noc axi_noc2" } if {[string match -nocase $ip_type "psu_pcie"]} { set pcie_config [get_property CONFIG.C_PCIE_MODE [get_cells -hier $drv_handle]] if {[string match -nocase $pcie_config "Endpoint Device"]} { lappend ignore_list $ip_type } } if {[lsearch $ignore_list $ip_type] >= 0 \ } { return 0 } set default_dts [set_drv_def_dts $drv_handle] set ps7_mapping [gen_ps7_mapping] set bus_node [add_or_get_bus_node $ip $default_dts] set status_enable_flow 0 set status_disabled 0 if {[is_ps_ip $drv_handle]} { set tmp [get_ps_node_unit_addr $drv_handle] if {$tmp != -1} {set unit_addr $tmp} if {[catch {set tmp [dict get $ps7_mapping $unit_addr label]} msg]} { # CHK: if PS IP that's not in the zynq-7000 dtsi, do not generate it return 0 } if {![string_is_empty $tmp]} { set status_enable_flow 1 } if {[catch {set tmp [dict get $ps7_mapping $unit_addr status]} msg]} { set status_disabled 0 } if {[string equal -nocase "disabled" $tmp]} { set status_disabled 1 } } if {$status_enable_flow} { set label [dict get $ps7_mapping $unit_addr label] set dev_type [dict get $ps7_mapping $unit_addr name] set bus_node "" # check if it has status property set rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${default_dts} -p $bus_node -auto_ref_parent] if {[string match -nocase $rt_node "&dwc3_0"]} { set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psu_cortexa53"] } { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set avail_param [list_property [get_cells -hier $zynq_periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__USB0__PERIPHERAL__ENABLE"] >= 0} { set value [get_property CONFIG.PSU__USB0__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]] if {$value == 1} { if {[lsearch -nocase $avail_param "CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE"] >= 0} { set val [get_property CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]] if {$val == 0} { hsi::utils::add_new_dts_param "${rt_node}" "maximum-speed" "high-speed" stringlist hsi::utils::add_new_dts_param "${rt_node}" "snps,dis_u2_susphy_quirk" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "snps,dis_u3_susphy_quirk" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "/delete-property/ phy-names" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "/delete-property/ phys" "" boolean } } } } } } if {[string match -nocase $rt_node "&dwc3_1"]} { set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psu_cortexa53"] } { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set avail_param [list_property [get_cells -hier $zynq_periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__USB1__PERIPHERAL__ENABLE"] >= 0} { set value [get_property CONFIG.PSU__USB1__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]] if {$value == 1} { if {[lsearch -nocase $avail_param "CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE"] >= 0} { set val [get_property CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE [get_cells -hier $zynq_periph]] if {$val == 0} { hsi::utils::add_new_dts_param "${rt_node}" "maximum-speed" "high-speed" stringlist hsi::utils::add_new_dts_param "${rt_node}" "snps,dis_u2_susphy_quirk" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "snps,dis_u3_susphy_quirk" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "/delete-property/ phy-names" "" boolean hsi::utils::add_new_dts_param "${rt_node}" "/delete-property/ phys" "" boolean } } } } } } if {$status_disabled} { if {[string match -nocase $ip_type "psu_smmu_gpv"]} { return } hsi::utils::add_new_dts_param "${rt_node}" "status" "okay" string } } else { if {[string match -nocase $ip_type "tsn_endpoint_ethernet_mac"]} { set rt_node [add_or_get_dt_node -n tsn_endpoint_ip_0 -l tsn_endpoint_ip_0 -d ${default_dts} -p $bus_node -auto_ref_parent] } else { set rt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${default_dts} -p $bus_node -auto_ref_parent] } } if {![string_is_empty $node_only]} { return $rt_node } zynq_gen_pl_clk_binding $drv_handle # generate mb ccf node generate_mb_ccf_node $drv_handle generate_cci_node $drv_handle $rt_node set dts_file_list "" if {[catch {set rt [report_property -return_string -regexp $drv_handle "CONFIG.*\\.dts(i|)"]} msg]} { set rt "" } foreach line [split $rt "\n"] { regsub -all {\s+} $line { } line if {[regexp "CONFIG.*\\.dts(i|)" $line matched]} { lappend dts_file_list [lindex [split $line " "] 0] } } regsub -all {CONFIG.} $dts_file_list {} dts_file_list set drv_dt_prop_list [get_driver_conf_list $drv_handle] foreach dts_file ${dts_file_list} { set dts_prop_list [get_property CONFIG.${dts_file} $drv_handle] set dt_node "" if {[string_is_empty ${dts_prop_list}] == 0} { set dt_node [add_or_get_dt_node -n ${dev_type} -l ${label} -u ${unit_addr} -d ${dts_file} -p $bus_node] foreach prop ${dts_prop_list} { add_driver_prop $drv_handle $dt_node CONFIG.${prop} # remove from default list set drv_dt_prop_list [list_remove_element $drv_dt_prop_list "CONFIG.${prop}"] } } } # update rest of properties to dt node foreach drv_prop_name $drv_dt_prop_list { add_driver_prop $drv_handle $rt_node ${drv_prop_name} } return $rt_node } proc detect_bus_label {bus_name} { # Using amba_pl as label for pl-bus node # to support backward compatibility if {[regexp "pl-bus" $bus_name match]} { return "amba_pl" } return $bus_name } proc detect_fpga_noderef {} { set proc_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]] if {[string match -nocase $proc_name "psv_cortexa72"] || [string match -nocase $proc_name "psx_cortexa78"]} { set targets "&fpga" } else { set targets "&fpga_full" } return $targets } proc detect_bus_name {ip_drv} { # FIXME: currently use single bus assumption # TODO: detect bus connection # zynq: uses amba base zynq-7000.dtsi # pl ip creates amba_pl # mb: detection is required (currently always call amba_pl) set valid_buses [get_cells -hier -filter { IP_TYPE == "BUS" && IP_NAME != "axi_protocol_converter" && IP_NAME != "lmb_v10"}] set proc_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]] set valid_proc_list "ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78" set remove_pl [get_property CONFIG.remove_pl [get_os]] set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {[is_pl_ip $ip_drv] && $remove_pl} { return 0 } if {[lsearch -nocase $valid_proc_list $proc_name] >= 0} { if {[is_pl_ip $ip_drv]} { # create the parent_node for pl.dtsi set default_dts [set_drv_def_dts $ip_drv] if {!$dt_overlay} { set root_node [add_or_get_dt_node -n / -d ${default_dts}] } return "pl-bus" } return "amba" } return "pl-bus" } proc get_afi_val {val} { set afival "" switch $val { "128" { set afival 0 } "64" { set afival 1 } "32" { set afival 2 } default { dtg_warning "invalid value:$val" } } return $afival } proc get_max_afi_val {val} { set max_afival "" switch $val { "128" { set max_afival 2 } "64" { set max_afival 1 } "32" { set max_afival 0 } default { dtg_warning "invalid value:$val" } } return $max_afival } proc get_axi_datawidth {val} { set data_width "" switch $val { "32" { set data_width 1 } "64" { set data_width 0 } default { dtg_warning "invalid data_width:$val" } } return $data_width } proc add_or_get_bus_node {ip_drv dts_file} { set bus_name [detect_bus_name $ip_drv] set bus_label [detect_bus_label $bus_name] dtg_debug "bus_name: $bus_name" dtg_debug "bus_label: $bus_label" set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $ip_drv] && $remove_pl} { return 0 } if {$dt_overlay && [string match -nocase $dts_file "pl.dtsi"]} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set avail_param [list_property [get_cells -hier $zynq_periph]] set targets "amba" set fpga_node [add_or_get_dt_node -n "&$targets" -d [get_dt_tree ${dts_file}]] set bus_node "$fpga_node" set RpRm [get_rp_rm_for_drv $ip_drv] regsub -all { } $RpRm "" RpRm set config_afi " " if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP0_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP0_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi "0 $afival>, <1 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP1_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP1_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <2 $afival>, <3 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP2_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP2_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <4 $afival>, <5 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP3_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP3_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <6 $afival>, <7 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP4_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP4_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <8 $afival>, <9 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP5_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP5_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <10 $afival>, <11 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_SAXIGP6_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_SAXIGP6_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival [get_afi_val $val] append config_afi " <12 $afival>, <13 $afival>," } if {[lsearch -nocase $avail_param "CONFIG.C_MAXIGP0_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_MAXIGP0_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival0 [get_max_afi_val $val] } if {[lsearch -nocase $avail_param "CONFIG.C_MAXIGP1_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_MAXIGP1_DATA_WIDTH [get_cells -hier $zynq_periph]] set afival1 [get_max_afi_val $val] } set afi0 [expr $afival0 <<8] set afi1 [expr $afival1 << 10] set afival [expr {$afi0} | {$afi1}] set afi_hex [format %x $afival] append config_afi " <14 0x$afi_hex>," if {[lsearch -nocase $avail_param "CONFIG.C_MAXIGP2_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_MAXIGP2_DATA_WIDTH [get_cells -hier $zynq_periph]] switch $val { "128" { set afival 0x200 } "64" { set afival 0x100 } "32" { set afival 0x000 } default { dtg_warning "invalid value:$val" } } append config_afi " <15 $afival" } if {[lsearch -nocase $avail_param "CONFIG.C_PL_CLK0_BUF"] >= 0} { set val [get_property CONFIG.C_PL_CLK0_BUF [get_cells -hier $zynq_periph]] if {[string match -nocase $val "true"]} { set clocking_node [add_or_get_dt_node -n "clocking0" -l "clocking0" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "zynqmp_clk 71" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "zynqmp_clk 71" reference set freq [get_property CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.C_PL_CLK1_BUF"] >= 0} { set val [get_property CONFIG.C_PL_CLK1_BUF [get_cells -hier $zynq_periph]] if {[string match -nocase $val "true"]} { set clocking_node [add_or_get_dt_node -n "clocking1" -l "clocking1" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "zynqmp_clk 72" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "zynqmp_clk 72" reference set freq [get_property CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.C_PL_CLK2_BUF"] >= 0} { set val [get_property CONFIG.C_PL_CLK2_BUF [get_cells -hier $zynq_periph]] if {[string match -nocase $val "true"]} { set clocking_node [add_or_get_dt_node -n "clocking2" -l "clocking2" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "zynqmp_clk 73" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "zynqmp_clk 73" reference set freq [get_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.C_PL_CLK3_BUF"] >= 0} { set val [get_property CONFIG.C_PL_CLK3_BUF [get_cells -hier $zynq_periph]] if {[string match -nocase $val "true"]} { set clocking_node [add_or_get_dt_node -n "clocking3" -l "clocking3" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "zynqmp_clk 74" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "zynqmp_clk 74" reference set freq [get_property CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } set afi_node [add_or_get_dt_node -n "afi0" -l "afi0" -p $bus_node] hsi::utils::add_new_dts_param "${afi_node}" "compatible" "xlnx,afi-fpga" string hsi::utils::add_new_dts_param "${afi_node}" "config-afi" "$config_afi" int set resets "zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119" hsi::utils::add_new_dts_param "${afi_node}" "resets" "$resets" reference } if {[string match -nocase $proctype "ps7_cortexa9"]} { set zynq_periph [get_cells -hier -filter {IP_NAME == processing_system7}] set avail_param [list_property [get_cells -hier $zynq_periph]] set targets "amba" set fpga_node [add_or_get_dt_node -n "&$targets" -d [get_dt_tree ${dts_file}]] set bus_node "$fpga_node" if {[lsearch -nocase $avail_param "CONFIG.C_USE_S_AXI_HP0"] >= 0} { set val [get_property CONFIG.C_USE_S_AXI_HP0 [get_cells -hier $zynq_periph]] if {$val == 1} { set afi0 [get_cells -hier -filter {NAME == "ps7_afi_0"}] set afi0_param [list_property [get_cells -hier $afi0]] if {[lsearch -nocase $afi0_param "CONFIG.C_S_AXI_BASEADDR"] >= 0} { set base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi0]] } if {[lsearch -nocase $afi0_param "CONFIG.C_S_AXI_HIGHADDR"] >= 0} { set high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi0]] } set size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]] set reg "$base_addr $size" regsub -all {^0x} $base_addr {} addr set addr [string tolower $addr] set afi_node [add_or_get_dt_node -n "afi0" -l "afi0" -u $addr -p $bus_node] hsi::utils::add_new_dts_param "${afi_node}" "compatible" "xlnx,afi-fpga" string hsi::utils::add_new_dts_param "${afi_node}" "#address-cells" "1" int hsi::utils::add_new_dts_param "${afi_node}" "#size-cells" "0" int hsi::utils::add_new_dts_param "${afi_node}" "reg" "$reg" intlist if {[lsearch -nocase $avail_param "CONFIG.C_S_AXI_HP0_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_S_AXI_HP0_DATA_WIDTH [get_cells -hier $zynq_periph]] set bus_width [get_axi_datawidth $val] hsi::utils::add_new_dts_param "${afi_node}" "xlnx,afi-width" "$bus_width" int } } } if {[lsearch -nocase $avail_param "CONFIG.C_USE_S_AXI_HP1"] >= 0} { set val [get_property CONFIG.C_USE_S_AXI_HP1 [get_cells -hier $zynq_periph]] if {$val == 1} { set afi1 [get_cells -hier -filter {NAME == "ps7_afi_1"}] set afi1_param [list_property [get_cells -hier $afi1]] if {[lsearch -nocase $afi1_param "CONFIG.C_S_AXI_BASEADDR"] >= 0} { set base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi1]] } if {[lsearch -nocase $afi1_param "CONFIG.C_S_AXI_HIGHADDR"] >= 0} { set high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi1]] } set size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]] set reg "$base_addr $size" regsub -all {^0x} $base_addr {} addr set addr [string tolower $addr] set afi_node [add_or_get_dt_node -n "afi1" -l "afi1" -u $addr -p $bus_node] hsi::utils::add_new_dts_param "${afi_node}" "compatible" "xlnx,afi-fpga" string hsi::utils::add_new_dts_param "${afi_node}" "#address-cells" "1" int hsi::utils::add_new_dts_param "${afi_node}" "#size-cells" "0" int hsi::utils::add_new_dts_param "${afi_node}" "reg" "$reg" intlist if {[lsearch -nocase $avail_param "CONFIG.C_S_AXI_HP1_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_S_AXI_HP1_DATA_WIDTH [get_cells -hier $zynq_periph]] set bus_width [get_axi_datawidth $val] hsi::utils::add_new_dts_param "${afi_node}" "xlnx,afi-width" "$bus_width" int } } } if {[lsearch -nocase $avail_param "CONFIG.C_USE_S_AXI_HP2"] >= 0} { set val [get_property CONFIG.C_USE_S_AXI_HP2 [get_cells -hier $zynq_periph]] if {$val == 1} { set afi2 [get_cells -hier -filter {NAME == "ps7_afi_2"}] set afi2_param [list_property [get_cells -hier $afi2]] if {[lsearch -nocase $afi2_param "CONFIG.C_S_AXI_BASEADDR"] >= 0} { set base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi2]] } if {[lsearch -nocase $afi2_param "CONFIG.C_S_AXI_HIGHADDR"] >= 0} { set high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi2]] } set size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]] set reg "$base_addr $size" regsub -all {^0x} $base_addr {} addr set addr [string tolower $addr] set afi_node [add_or_get_dt_node -n "afi2" -l "afi2" -u $addr -p $bus_node] hsi::utils::add_new_dts_param "${afi_node}" "compatible" "xlnx,afi-fpga" string hsi::utils::add_new_dts_param "${afi_node}" "#address-cells" "1" int hsi::utils::add_new_dts_param "${afi_node}" "#size-cells" "0" int hsi::utils::add_new_dts_param "${afi_node}" "reg" "$reg" intlist if {[lsearch -nocase $avail_param "CONFIG.C_S_AXI_HP2_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_S_AXI_HP2_DATA_WIDTH [get_cells -hier $zynq_periph]] set bus_width [get_axi_datawidth $val] hsi::utils::add_new_dts_param "${afi_node}" "xlnx,afi-width" "$bus_width" int } } } if {[lsearch -nocase $avail_param "CONFIG.C_USE_S_AXI_HP3"] >= 0} { set val [get_property CONFIG.C_USE_S_AXI_HP3 [get_cells -hier $zynq_periph]] if {$val == 1} { set afi3 [get_cells -hier -filter {NAME == "ps7_afi_3"}] set afi3_param [list_property [get_cells -hier $afi3]] if {[lsearch -nocase $afi3_param "CONFIG.C_S_AXI_BASEADDR"] >= 0} { set base_addr [get_property CONFIG.C_S_AXI_BASEADDR [get_cells -hier $afi2]] } if {[lsearch -nocase $afi3_param "CONFIG.C_S_AXI_HIGHADDR"] >= 0} { set high_addr [get_property CONFIG.C_S_AXI_HIGHADDR [get_cells -hier $afi2]] } set size [format 0x%x [expr {${high_addr} - ${base_addr} + 1}]] set reg "$base_addr $size" regsub -all {^0x} $base_addr {} addr set addr [string tolower $addr] set afi_node [add_or_get_dt_node -n "afi3" -l "afi3" -u $addr -p $bus_node] hsi::utils::add_new_dts_param "${afi_node}" "compatible" "xlnx,afi-fpga" string hsi::utils::add_new_dts_param "${afi_node}" "#address-cells" "1" int hsi::utils::add_new_dts_param "${afi_node}" "#size-cells" "0" int hsi::utils::add_new_dts_param "${afi_node}" "reg" "$reg" intlist if {[lsearch -nocase $avail_param "CONFIG.C_S_AXI_HP3_DATA_WIDTH"] >= 0} { set val [get_property CONFIG.C_S_AXI_HP3_DATA_WIDTH [get_cells -hier $zynq_periph]] set bus_width [get_axi_datawidth $val] hsi::utils::add_new_dts_param "${afi_node}" "xlnx,afi-width" "$bus_width" int } } } if {[lsearch -nocase $avail_param "CONFIG.PCW_FPGA_FCLK0_ENABLE"] >= 0} { set val [get_property CONFIG.PCW_FPGA_FCLK0_ENABLE [get_cells -hier $zynq_periph]] if {[string match -nocase $val "1"]} { set clocking_node [add_or_get_dt_node -n "clocking0" -l "clocking0" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "clkc 15" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "clkc 15" reference set freq [get_property CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.PCW_FPGA_FCLK1_ENABLE"] >= 0} { set val [get_property CONFIG.PCW_FPGA_FCLK1_ENABLE [get_cells -hier $zynq_periph]] if {[string match -nocase $val "1"]} { set clocking_node [add_or_get_dt_node -n "clocking1" -l "clocking1" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "clkc 16" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "clkc 16" reference set freq [get_property CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.PCW_FPGA_FCLK2_ENABLE"] >= 0} { set val [get_property CONFIG.PCW_FPGA_FCLK2_ENABLE [get_cells -hier $zynq_periph]] if {[string match -nocase $val "1"]} { set clocking_node [add_or_get_dt_node -n "clocking2" -l "clocking2" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "clkc 17" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "clkc 17" reference set freq [get_property CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.PCW_FPGA_FCLK3_ENABLE"] >= 0} { set val [get_property CONFIG.PCW_FPGA_FCLK3_ENABLE [get_cells -hier $zynq_periph]] if {[string match -nocase $val "1"]} { set clocking_node [add_or_get_dt_node -n "clocking3" -l "clocking3" -p $bus_node] hsi::utils::add_new_dts_param "${clocking_node}" "compatible" "xlnx,fclk" string hsi::utils::add_new_dts_param "${clocking_node}" "clocks" "clkc 18" reference hsi::utils::add_new_dts_param "${clocking_node}" "clock-output-names" "fabric_clk" string hsi::utils::add_new_dts_param "${clocking_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clocks" "clkc 18" reference set freq [get_property CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ [get_cells -hier $zynq_periph]] hsi::utils::add_new_dts_param "${clocking_node}" "assigned-clock-rates" [scan [expr $freq * 1000000] "%d"] int } } } } if {[is_pl_ip $ip_drv] && $dt_overlay} { set targets "amba" set fpga_node [add_or_get_dt_node -n "&$targets" -d [get_dt_tree ${dts_file}]] set RpRm [get_rp_rm_for_drv $ip_drv] regsub -all { } $RpRm "" RpRm if {[llength $RpRm]} { set default_dts "pl-partial-$RpRm.dtsi" } set bus_node "$fpga_node" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { hsi::utils::add_new_dts_param "${bus_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${bus_node}" "#size-cells" 2 int } else { hsi::utils::add_new_dts_param "${bus_node}" "#address-cells" 1 int hsi::utils::add_new_dts_param "${bus_node}" "#size-cells" 1 int } } else { set bus_node [add_or_get_dt_node -n ${bus_name} -l ${bus_label} -d [get_dt_tree ${dts_file}] -p "/" -disable_auto_ref -auto_ref_parent] if {![string match "&*" $bus_node]} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { hsi::utils::add_new_dts_param "${bus_node}" "#address-cells" 2 int hsi::utils::add_new_dts_param "${bus_node}" "#size-cells" 2 int } else { hsi::utils::add_new_dts_param "${bus_node}" "#address-cells" 1 int hsi::utils::add_new_dts_param "${bus_node}" "#size-cells" 1 int } hsi::utils::add_new_dts_param "${bus_node}" "compatible" "simple-bus" stringlist hsi::utils::add_new_dts_param "${bus_node}" "ranges" "" boolean } } return $bus_node } proc gen_root_node {drv_handle} { set default_dts [set_drv_def_dts $drv_handle] # add compatible set ip_name [get_property IP_NAME [get_cell -hier ${drv_handle}]] switch $ip_name { "ps7_cortexa9" { create_dt_tree_from_dts_file global dtsi_fname update_system_dts_include [file tail ${dtsi_fname}] # no root_node required as zynq-7000.dtsi return 0 } "psu_cortexa53" { create_dt_tree_from_dts_file global dtsi_fname set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { update_system_dts_include [file tail ${dtsi_fname}] update_system_dts_include [file tail "zynqmp-clk.dtsi"] return 0 } update_system_dts_include [file tail ${dtsi_fname}] update_system_dts_include [file tail "zynqmp-clk-ccf.dtsi"] # no root_node required as zynqmp.dtsi return 0 } "psv_cortexa72" { create_dt_tree_from_dts_file global dtsi_fname update_system_dts_include [file tail ${dtsi_fname}] set overrides [get_property CONFIG.periph_type_overrides [get_os]] set dtsi_file " " foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set dtsi_file [lindex $override 1] } } if {[string match -nocase $dtsi_file "versal-spp-itr8-cn13940875"] || [string match -nocase $dtsi_file "versal-vc-p-a2197-00-reva-x-prc-01-reva-pm"]} { update_system_dts_include [file tail "versal-spp-pm.dtsi"] } else { update_system_dts_include [file tail "versal-clk.dtsi"] } return 0 } "psx_cortexa78" { create_dt_tree_from_dts_file global dtsi_fname update_system_dts_include [file tail ${dtsi_fname}] set overrides [get_property CONFIG.periph_type_overrides [get_os]] set dtsi_file " " set board_dtsi_file "" foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set board_dtsi_file [lindex $override 1] } } #TMP fix to support ipp fixed clocks if {[string match -nocase $board_dtsi_file "versal-net-ipp-rev1.9"]} { set dtsi_file $board_dtsi_file } else { update_system_dts_include [file tail "versal-net-clk-ccf.dtsi"] } return 0 } "microblaze" { set compatible "xlnx,microblaze" set model "Xilinx MicroBlaze" } default { return -code error "Unknown arch" } } set root_node [add_or_get_dt_node -n / -d ${default_dts}] hsi::utils::add_new_dts_param "${root_node}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${root_node}" "#size-cells" 1 int "" hsi::utils::add_new_dts_param "${root_node}" model $model string "" hsi::utils::add_new_dts_param "${root_node}" compatible $compatible string "" return $root_node } proc cortexa9_opp_gen {drv_handle} { # generate opp overlay for cpu if {[catch {set cpu_max_freq [get_property CONFIG.C_CPU_CLK_FREQ_HZ [get_cells -hier $drv_handle]]} msg]} { set cpu_max_freq "" } if {[string_is_empty ${cpu_max_freq}]} { dtg_warning "DTG failed to detect the CPU clock frequency" return -1 } set cpu_max_freq [expr int([expr $cpu_max_freq/1000])] set processor [get_sw_processor] set default_dts [set_drv_def_dts $processor] set root_node [add_or_get_dt_node -n / -d ${default_dts}] set cpu_root_node [add_or_get_dt_node -n cpus -d ${default_dts} -p $root_node] set cpu_node [add_or_get_dt_node -n cpu -u 0 -d ${default_dts} -p ${cpu_root_node} -disable_auto_ref -force] set tmp_opp $cpu_max_freq set opp "" set i 0 # do not generate opp for freq lower than 200MHz and use fix voltage # 1000000uv while {$tmp_opp >= 200000} { append opp " " "$tmp_opp 1000000" incr i set tmp_opp [expr int([expr $cpu_max_freq / pow(2, $i)])] } if {![string_is_empty $opp]} { hsi::utils::add_new_dts_param $cpu_node "operating-points" "$opp" intlist } } # Q: common function for all processor or one for each driver lib proc gen_cpu_nodes {drv_handle} { set ip_name [get_property IP_NAME [get_cell -hier [get_sw_processor]]] switch $ip_name { "ps7_cortexa9" { # skip node generation for static zynq-7000 dtsi # TODO: this needs to be fixed to allow override cortexa9_opp_gen $drv_handle return 0 } "psu_cortexa53" { # skip node generation for static zynqmp dtsi return 0 } "psv_cortexa72" { return 0 } "psx_cortexa78" { return 0 } "microblaze" {} default { error "Unknown arch" } } set processor [get_sw_processor] set dev_type [get_property CONFIG.dev_type $processor] if {[string_is_empty $dev_type] == 1} { set dev_type $drv_handle } gen_compatible_property $processor gen_mb_interrupt_property $processor gen_drv_prop_from_ip $processor set default_dts [set_drv_def_dts $processor] set cpu_root_node [add_or_get_dt_node -n cpus -d ${default_dts} -p /] hsi::utils::add_new_dts_param "${cpu_root_node}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${cpu_root_node}" "#size-cells" 0 int "" set processor_type [get_property IP_NAME [get_cell -hier ${processor}]] set processor_list [eval "get_cells -hier -filter { IP_TYPE == \"PROCESSOR\" && IP_NAME == \"${processor_type}\" }"] set drv_dt_prop_list [get_driver_conf_list $processor] # generate mb ccf node generate_mb_ccf_node $processor set bus_node [add_or_get_bus_node $drv_handle $default_dts] set cpu_no 0 foreach cpu ${processor_list} { # Generate the node only for the single core if {$cpu_no >= 1} { break } set bus_label [get_property NODE_LABEL $bus_node] set cpu_node [add_or_get_dt_node -n ${dev_type} -l ${cpu} -u ${cpu_no} -d ${default_dts} -p ${cpu_root_node}] hsi::utils::add_new_dts_param "${cpu_node}" "bus-handle" $bus_label reference foreach drv_prop_name $drv_dt_prop_list { add_driver_prop $processor $cpu_node ${drv_prop_name} } hsi::utils::add_new_dts_param "${cpu_node}" "reg" $cpu_no int "" incr cpu_no } hsi::utils::add_new_dts_param "${cpu_root_node}" "#cpus" $cpu_no int "" } proc remove_all_tree {} { # for testing set test_dummy "for_test_dummy.dts" if {[lsearch [get_dt_trees] ${test_dummy}] < 0} { create_dt_tree -dts_file $test_dummy } set_cur_working_dts $test_dummy foreach tree [get_dt_trees] { if {[string equal -nocase $test_dummy $tree]} { continue } catch {delete_objs $tree} msg } } proc gen_mdio_node {drv_handle parent_node} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return } set mdio_node [add_or_get_dt_node -l ${drv_handle}_mdio -n mdio -p $parent_node] hsi::utils::add_new_dts_param "${mdio_node}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${mdio_node}" "#size-cells" 0 int "" return $mdio_node } proc add_memory_node {drv_handle} { set master_dts [get_property CONFIG.master_dts [get_os]] set cur_dts [current_dt_tree] set master_dts_obj [get_dt_trees ${master_dts}] set_cur_working_dts $master_dts # assuming single memory region # - single memory region # - / node is created # - reg property is generated # CHECK node naming set ddr_ip "" set main_memory [get_property CONFIG.main_memory [get_os]] if {![string match -nocase $main_memory "none"]} { set ddr_ip [get_property IP_NAME [get_cells -hier -nocase $main_memory]] } set ddr_list "psu_ddr ps7_ddr axi_emc mig_7series psv_ddr" if {[lsearch -nocase $ddr_list $ddr_ip] >= 0} { set parent_node [add_or_get_dt_node -n / -d ${master_dts}] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set reg_value [get_property CONFIG.reg $drv_handle] # Append base address to memory node. if {[llength "$reg_value"]} { if {[string match -nocase $proctype "psu_cortexa53"] || \ [string match -nocase $proctype "psv_cortexa72"] || \ [string match -nocase $proctype "psx_cortexa78"]} { set higheraddr [expr [lindex $reg_value 0] << 32] set loweraddr [lindex $reg_value 1] set unitaddr [format 0x%x [expr {${higheraddr} + ${loweraddr}}]] } else { set unitaddr [lindex $reg_value 0] } regsub -all {^0x} $unitaddr {} unitaddr set memory_node [add_or_get_dt_node -n memory -p $parent_node -u $unitaddr] hsi::utils::add_new_dts_param "${memory_node}" "reg" $reg_value inthexlist } # maybe hardcoded if {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} { set dev_type memory } if {[string_is_empty $dev_type]} {set dev_type memory} hsi::utils::add_new_dts_param "${memory_node}" "device_type" $dev_type string set_cur_working_dts $cur_dts return $memory_node } } proc gen_mb_ccf_subnode {drv_handle name freq reg} { set cur_dts [current_dt_tree] set default_dts [set_drv_def_dts $drv_handle] set clk_node [add_or_get_dt_node -n clocks -p / -d ${default_dts}] hsi::utils::add_new_dts_param "${clk_node}" "#address-cells" 1 int hsi::utils::add_new_dts_param "${clk_node}" "#size-cells" 0 int set clk_subnode_name "clk_${name}" set clk_subnode [add_or_get_dt_node -l ${clk_subnode_name} -n ${clk_subnode_name} -u $reg -p ${clk_node} -d ${default_dts}] # clk subnode data hsi::utils::add_new_dts_param "${clk_subnode}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${clk_subnode}" "#clock-cells" 0 int hsi::utils::add_new_dts_param $clk_subnode "clock-output-names" $clk_subnode_name string hsi::utils::add_new_dts_param $clk_subnode "reg" $reg int hsi::utils::add_new_dts_param $clk_subnode "clock-frequency" $freq int set_cur_working_dts $cur_dts } proc generate_mb_ccf_node {drv_handle} { global bus_clk_list set sw_proc [get_sw_processor] set proc_ip [get_cells -hier $sw_proc] set proctype [get_property IP_NAME $proc_ip] if {[string match -nocase $proctype "microblaze"]} { set cpu_clk_freq [get_clock_frequency $proc_ip "CLK"] # issue: # - hardcoded reg number cpu clock node # - assume clk_cpu for mb cpu # - only applies to master mb cpu gen_mb_ccf_subnode $sw_proc cpu $cpu_clk_freq 0 } } proc gen_dev_ccf_binding args { set drv_handle [lindex $args 0] set pins [lindex $args 1] set binding_list "clocks clock-frequency" if {[llength $args] >= 3} { set binding_list [lindex $args 2] } # list of ip should have the clocks property global bus_clk_list set sw_proc [get_sw_processor] set proc_ip [get_cells -hier $sw_proc] set proctype [get_property IP_NAME $proc_ip] if {[string match -nocase $proctype "microblaze"]} { set clk_refs "" set clk_names "" set clk_freqs "" foreach p $pins { set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$p"] if {![string equal $clk_freq ""]} { # FIXME: bus clk source count should based on the clock generator not based on clk freq diff if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] # create the node and assuming reg 0 is taken by cpu gen_mb_ccf_subnode $drv_handle bus_${bus_clk_cnt} $clk_freq [expr ${bus_clk_cnt} + 1] set clk_refs [lappend clk_refs &clk_bus_${bus_clk_cnt}] set clk_names [lappend clk_names "$p"] set clk_freqs [lappend clk_freqs "$clk_freq"] } } if {[lsearch $binding_list "clocks"] >= 0} { hsi::utils::add_new_property $drv_handle "clocks" referencelist $clk_refs } if {[lsearch $binding_list "clock-names"] >= 0} { hsi::utils::add_new_property $drv_handle "clock-names" stringlist $clk_names } if {[lsearch $binding_list "clock-frequency"] >= 0} { hsi::utils::add_new_property $drv_handle "clock-frequency" hexintlist $clk_freqs } } } proc update_eth_mac_addr {drv_handle} { set eth_count [get_os_dev_count "eth_mac_count"] set tmp [list_property $drv_handle CONFIG.local-mac-address] if {![string_is_empty $tmp]} { set def_mac [get_property CONFIG.local-mac-address $drv_handle] } else { set def_mac "" } if {[string_is_empty $def_mac]} { set def_mac "00 0a 35 00 00 00" } set mac_addr_data [split $def_mac " "] set last_value [format %02x [expr [lindex $mac_addr_data 5] + $eth_count ]] set mac_addr [lreplace $mac_addr_data 5 5 $last_value] dtg_debug "${drv_handle}:set mac addr to $mac_addr" incr eth_count hsi::utils::set_os_parameter_value "eth_mac_count" $eth_count hsi::utils::add_new_property $drv_handle "local-mac-address" bytelist ${mac_addr} } proc get_os_dev_count {count_para {drv_handle ""} {os_para ""}} { set dev_count [hsi::utils::get_os_parameter_value "${count_para}"] if {[llength $dev_count] == 0} { set dev_count 0 } if {[string_is_empty $os_para] || [string_is_empty $drv_handle]} { return $dev_count } set ip [get_cells -hier $drv_handle] set chosen_ip [hsi::utils::get_os_parameter_value "${os_para}"] if {[string match -nocase "$ip" "$chosen_ip"]} { hsi::utils::set_os_parameter_value $count_para 1 return 0 } else { return $dev_count } } proc get_hw_version {} { set hw_ver_data [split [get_property VIVADO_VERSION [get_hw_designs]] "."] set hw_ver [lindex $hw_ver_data 0].[lindex $hw_ver_data 1] return $hw_ver } proc get_hsi_version {} { set hsi_ver_data [split [version -short] "."] set hsi_ver [lindex $hsi_ver_data 0].[lindex $hsi_ver_data 1] return $hsi_ver } proc get_sw_proc_prop {prop_name} { set sw_proc [get_sw_processor] set proc_ip [get_cells -hier $sw_proc] set property_value [get_property $prop_name $proc_ip] return $property_value } # Get the interrupt controller name, which the ip is connected proc get_intr_cntrl_name { periph_name intr_pin_name } { lappend intr_cntrl if { [llength $intr_pin_name] == 0 } { return $intr_cntrl } if { [llength $periph_name] != 0 } { # This is the case where IP pin is interrupting set periph [::hsi::get_cells -hier -filter "NAME==$periph_name"] if { [llength $periph] == 0 } { return $intr_cntrl } set intr_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intr_pin_name"] if { [llength $intr_pin] == 0 } { return $intr_cntrl } set valid_cascade_proc "microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if { [string match -nocase [common::get_property IP_NAME $periph] "axi_intc"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0 } { set sinks [::hsi::utils::get_sink_pins $intr_pin] foreach intr_sink ${sinks} { set sink_periph [::hsi::get_cells -of_objects $intr_sink] if { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "axi_intc"] } { # this the case where interrupt port is connected to axi_intc. lappend intr_cntrl [get_intr_cntrl_name $sink_periph "irq"] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlconcat"] } { # this the case where interrupt port is connected to XLConcat IP. lappend intr_cntrl [get_intr_cntrl_name $sink_periph "dout"] } elseif { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } { lappend intr_cntrl $sink_periph } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "microblaze"] } { lappend intr_cntrl $sink_periph } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "tmr_voter"] } { lappend intr_cntrl $sink_periph } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "dfx_decoupler"] } { set intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}] lappend intr_cntrl [get_intr_cntrl_name $sink_periph "$intr"] } if {[llength $intr_cntrl] > 1} { foreach intc $intr_cntrl { if { [::hsi::utils::is_ip_interrupting_current_proc $intc] } { set intr_cntrl $intc } } } } return $intr_cntrl } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "I"] } { return $intr_cntrl } } else { # This is the case where External interrupt port is interrupting set intr_pin [::hsi::get_ports $intr_pin_name] if { [llength $intr_pin] == 0 } { return $intr_cntrl } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "O"] } { return $intr_cntrl } } set intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin] if { [llength $intr_sink_pins] == 0 || [string match $intr_sink_pins "{}"]} { return $intr_cntrl } set valid_cascade_proc "microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78" foreach intr_sink ${intr_sink_pins} { if {[llength $intr_sink] == 0} { continue } set sink_periph [::hsi::get_cells -of_objects $intr_sink] if { [llength $sink_periph ] && [::hsi::utils::is_intr_cntrl $sink_periph] == 1 } { if { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "axi_intc"] && [lsearch -nocase $valid_cascade_proc $proctype] >= 0} { lappend intr_cntrl [get_intr_cntrl_name $sink_periph "irq"] } else { lappend intr_cntrl $sink_periph } } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlconcat"] } { # this the case where interrupt port is connected to XLConcat IP. lappend intr_cntrl [get_intr_cntrl_name $sink_periph "dout"] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlslice"]} { lappend intr_cntrl [get_intr_cntrl_name $sink_periph "Dout"] } elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "util_reduced_logic"]} { lappend intr_cntrl [get_intr_cntrl_name $sink_periph "Res"] } elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "axi_gpio"]} { set intr_present [get_property CONFIG.C_INTERRUPT_PRESENT $sink_periph] if {$intr_present == 1} { lappend intr_cntrl $sink_periph } } elseif {[llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "util_ff"]} { lappend intr_cntrl [get_intr_cntrl_name $sink_periph "Q"] } elseif { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "dfx_decoupler"] } { set intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}] lappend intr_cntrl [get_intr_cntrl_name $sink_periph "$intr"] } if {[llength $intr_cntrl] > 1} { foreach intc $intr_cntrl { if { [::hsi::utils::is_ip_interrupting_current_proc $intc] } { set intr_cntrl $intc } } } } set val [string trim $intr_cntrl \{\}] if {[llength $val] == 0} { return } return $intr_cntrl } # Generate interrupt info for the ips which are using gpio # as interrupt. proc generate_gpio_intr_info {connected_intc drv_handle pin} { set intr_info "" global ps_gpio_pincount if {[string_is_empty $connected_intc]} { return -1 } # Get the gpio channel number to which the ip is connected set channel_nr [get_gpio_channel_nr $drv_handle $pin] set slave [get_cells -hier ${drv_handle}] set ip_name $connected_intc set intr_type [get_intr_type $connected_intc $slave $pin] if {[string match -nocase $intr_type "-1"]} { return -1 } set sinkpin [::hsi::utils::get_sink_pins [get_pins -of [get_cells -hier $drv_handle] -filter {TYPE==INTERRUPT}]] set dual [get_property CONFIG.C_IS_DUAL $connected_intc] regsub -all {[^0-9]} $sinkpin "" gpio_pin_count set gpio_cho_pin_lcnt [get_property LEFT [get_pins -of_objects [get_cells -hier $connected_intc] gpio_io_i]] set gpio_cho_pin_rcnt [get_property RIGHT [get_pins -of_objects [get_cells -hier $connected_intc] gpio_io_i]] set gpio_cho_pin_rcnt [expr $gpio_cho_pin_rcnt + 1] set gpio_ch0_pin_cnt [expr {$gpio_cho_pin_lcnt + $gpio_cho_pin_rcnt}] if {[string match $channel_nr "0"]} { # Check for ps7_gpio else check for axi_gpio if {[string match $sinkpin "GPIO_I"]} { set intr_info "$ps_gpio_pincount $intr_type" expr ps_gpio_pincount 1 } elseif {[regexp "gpio_io_i" $sinkpin match]} { set intr_info "0 $intr_type" } else { # if channel width is more than one set intr_info "$gpio_pin_count $intr_type " } } else { if {[string match $dual "1"]} { # gpio channel 2 width is one if {[regexp "gpio2_io_i" $sinkpin match]} { set intr_info "32 $intr_type" } else { # if channel width is more than one set intr_pin [::hsi::get_pins -of_objects $connected_intc -filter "NAME==$pin"] set gpio_channel [::hsi::utils::get_sink_pins $intr_pin] set intr_id [expr $gpio_pin_count + $gpio_ch0_pin_cnt] set intr_info "$intr_id $intr_type" } } } set intc $connected_intc if {[string_is_empty $intr_info]} { return -1 } set_drv_prop $drv_handle interrupts $intr_info intlist if {[string_is_empty $intc]} { return -1 } set intc [ps_node_mapping $intc label] set_drv_prop $drv_handle interrupt-parent $intc reference } # Get the gpio channel number to which the ip is connected # if pin is gpio_io_* then channel is 1 # if pin is gpio2_io_* then channel is 2 proc get_gpio_channel_nr { periph_name intr_pin_name } { lappend intr_cntrl if { [llength $intr_pin_name] == 0 } { return $intr_cntrl } if { [llength $periph_name] != 0 } { set periph [::hsi::get_cells -hier -filter "NAME==$periph_name"] if { [llength $periph] == 0 } { return $intr_cntrl } set intr_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intr_pin_name"] if { [llength $intr_pin] == 0 } { return $intr_cntrl } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "I"] } { return $intr_cntrl } set intr_sink_pins [::hsi::utils::get_sink_pins $intr_pin] set sink_periph [::hsi::get_cells -of_objects $intr_sink_pins] if { [llength $sink_periph] && [string match -nocase [common::get_property IP_NAME $sink_periph] "xlconcat"] } { # this the case where interrupt port is connected to XLConcat IP. return [get_gpio_channel_nr $sink_periph "dout"] } if {[regexp "gpio[2]_*" $intr_sink_pins match]} { return 1 } else { return 0 } } } proc is_interrupt { IP_NAME } { if { [string match -nocase $IP_NAME "ps7_scugic"] } { return true } elseif { [string match -nocase $IP_NAME "psu_acpu_gic"] || [string match -nocase $IP_NAME "psv_acpu_gic"] || [string match -nocase $IP_NAME "psx_acpu_gic"]} { return true } elseif { [string match -nocase $IP_NAME "psu_rcpu_gic"] } { return true } return false; } proc is_orgate { intc_src_port ip_name} { set ret -1 set intr_sink_pins [::hsi::utils::get_sink_pins $intc_src_port] set sink_periph [::hsi::get_cells -of_objects $intr_sink_pins] set ipname [get_property IP_NAME $sink_periph] if { $ipname == "xlconcat" } { set intf "dout" set intr1_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$intf"] set intr_sink_pins [::hsi::utils::get_sink_pins $intr1_pin] set sink_periph [::hsi::get_cells -of_objects $intr_sink_pins] set ipname [get_property IP_NAME $sink_periph] if {$ipname == "util_reduced_logic"} { set width [get_property CONFIG.C_SIZE $sink_periph] return $width } } return $ret } proc get_psu_interrupt_id { ip_name port_name } { global or_id global or_cnt set ret -1 set periph "" set intr_pin "" if { [llength $port_name] == 0 } { return $ret } global pl_ps_irq1 global pl_ps_irq0 if { [llength $ip_name] != 0 } { #This is the case where IP pin is interrupting set periph [::hsi::get_cells -hier -filter "NAME==$ip_name"] if { [llength $periph] == 0 } { return $ret } set intr_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$port_name"] if { [llength $intr_pin] == 0 } { return $ret } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "I"] } { return $ret } } else { #This is the case where External interrupt port is interrupting set intr_pin [::hsi::get_ports $port_name] if { [llength $intr_pin] == 0 } { return $ret } set pin_dir [common::get_property DIRECTION $intr_pin] if { [string match -nocase $pin_dir "O"] } { return $ret } } set intc_periph [get_interrupt_parent $ip_name $port_name] if {[llength $intc_periph] > 1} { foreach intr_cntr $intc_periph { if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } { set intc_periph $intr_cntr } } } if { [llength $intc_periph] == 0 } { return $ret } set intc_type [common::get_property IP_NAME $intc_periph] #set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[llength $intc_type] > 1} { foreach intr_cntr $intc_type { if { [::hsi::utils::is_ip_interrupting_current_proc $intr_cntr] } { set intc_type $intr_cntr } } } set intc_src_ports [::hsi::utils::get_interrupt_sources $intc_periph] #Special Handling for cascading case of axi_intc Interrupt controller set cascade_id 0 set i $cascade_id set found 0 set j $or_id foreach intc_src_port $intc_src_ports { # Check whether externel port is interrupting not peripheral # like externel[7:0] port to gic set pin_dir [common::get_property DIRECTION $intc_src_port] if { [string match -nocase $pin_dir "I"] } { incr i continue } if { [llength $intc_src_port] == 0 } { incr i continue } set intr_width [::hsi::utils::get_port_width $intc_src_port] set intr_periph [::hsi::get_cells -of_objects $intc_src_port] if { [llength $intr_periph] && [is_interrupt $intc_type] } { if {[common::get_property IS_PL $intr_periph] == 0 } { continue } } set width [is_orgate $intc_src_port $ip_name] if { [string compare -nocase "$port_name" "$intc_src_port" ] == 0 } { if { [string compare -nocase "$intr_periph" "$periph"] == 0 && $width != -1} { set or_cnt [expr $or_cnt + 1] if { $or_cnt == $width} { set or_cnt 0 set or_id [expr $or_id + 1] } set ret $i set found 1 break } elseif { [string compare -nocase "$intr_periph" "$periph"] == 0 } { set ret $i set found 1 break } } if { $width != -1} { set i [expr $or_id] } else { set i [expr $i + $intr_width] } } set intr_list_irq0 [list 89 90 91 92 93 94 95 96] set intr_list_irq1 [list 104 105 106 107 108 109 110 111] set sink_pins [::hsi::utils::get_sink_pins $intr_pin] if { [llength $sink_pins] == 0 } { return } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"]} { if {[string match -nocase "[get_property IP_NAME $periph]" "axi_intc"]} { set ip [get_property IP_NAME $periph] set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]] set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]] set sink_pn [::hsi::utils::get_sink_pins $intr_pin] set peri [::hsi::get_cells -of_objects $sink_pn] set periph_ip [get_property IP_NAME [get_cells -hier $peri]] if {[string match -nocase $periph_ip "xlconcat"]} { set dout "dout" set intr_pin [::hsi::get_pins -of_objects $peri -filter "NAME==$dout"] set pins [::hsi::utils::get_sink_pins "$intr_pin"] set perih [::hsi::get_cells -of_objects $pins] if {[string match -nocase "[get_property IP_NAME $perih]" "axi_intc"]} { set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $perih]] set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $perih]] } } set number [regexp -all -inline -- {[0-9]+} $sink_pn] return $number } } if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "ps7_cortexa9"] || [string match -nocase $proctype "psx_cortexa78"]} { if {[string match -nocase "[get_property IP_NAME $periph]" "axi_intc"]} { set ip [get_property IP_NAME $periph] set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]] set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]] set sink_pn [::hsi::utils::get_sink_pins $intr_pin] set peri [::hsi::get_cells -of_objects $sink_pn] set periph_ip [get_property IP_NAME [get_cells -hier $peri]] if {[string match -nocase $periph_ip "xlconcat"]} { set dout "dout" set intr_pin [::hsi::get_pins -of_objects $peri -filter "NAME==$dout"] set pins [::hsi::utils::get_sink_pins "$intr_pin"] set periph [::hsi::get_cells -of_objects $pins] if {[string match -nocase "[get_property IP_NAME $periph]" "axi_intc"]} { set cascade_master [get_property CONFIG.C_CASCADE_MASTER [get_cells -hier $periph]] set en_cascade_mode [get_property CONFIG.C_EN_CASCADE_MODE [get_cells -hier $periph]] } if {$en_cascade_mode == 1} { set number [regexp -all -inline -- {[0-9]+} $sink_pn] return $number } } } } set concat_block 0 foreach sink_pin $sink_pins { set sink_periph [::hsi::get_cells -of_objects $sink_pin] if {[llength $sink_periph] == 0 } { continue } set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]] if {[llength $connected_ip]} { if {[string compare -nocase "$connected_ip" "dfx_decoupler"] == 0} { set dfx_intr [get_pins -of_objects $sink_periph -filter {TYPE==INTERRUPT&&DIRECTION==O}] set intr_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$dfx_intr"] set sink_pins [::hsi::utils::get_sink_pins "$intr_pin"] foreach pin $sink_pins { set sink_pin $pin if {[string match -nocase $sink_pin "IRQ0_F2P"]} { set sink_pin "IRQ0_F2P" break } if {[string match -nocase $sink_pin "IRQ1_F2P"]} { set sink_pin "IRQ1_F2P" break } } } } if {[llength $connected_ip]} { # check for direct connection or concat block connected if { [string compare -nocase "$connected_ip" "xlconcat"] == 0 } { set pin_number [regexp -all -inline -- {[0-9]+} $sink_pin] set number 0 global intrpin_width for { set i 0 } {$i <= $pin_number} {incr i} { set pin_wdth [get_property LEFT [ lindex [ get_pins -of_objects [get_cells -hier $sink_periph ] ] $i ] ] if { $i == $pin_number } { set intrpin_width [expr $pin_wdth + 1] } else { set number [expr $number + {$pin_wdth + 1}] } } dtg_debug "Full pin width for $sink_periph of $sink_pin:$number intrpin_width:$intrpin_width" set dout "dout" set concat_block 1 set intr_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$dout"] set sink_pins [::hsi::utils::get_sink_pins "$intr_pin"] set sink_periph [::hsi::get_cells -of_objects $sink_pins] set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]] while {[llength $connected_ip]} { if {![string match -nocase "$connected_ip" "xlconcat"]} { break } set dout "dout" set intr_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$dout"] set sink_pins [::hsi::utils::get_sink_pins $intr_pin] set sink_periph [::hsi::get_cells -of_objects $sink_pins] set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]] } foreach pin $sink_pins { set sink_pin $pin if {[string match -nocase $sink_pin "IRQ0_F2P"]} { set sink_pin "IRQ0_F2P" break } if {[string match -nocase $sink_pin "IRQ1_F2P"]} { set sink_pin "IRQ1_F2P" break } } } } # check for ORgate or util_ff if { [string compare -nocase "$sink_pin" "Op1"] == 0 || [string compare -nocase "$sink_pin" "D"] == 0 } { if { [string compare -nocase "$sink_pin" "Op1"] == 0 } { set dout "Res" } elseif { [string compare -nocase "$sink_pin" "D"] == 0 } { set dout "Q" } set sink_periph [::hsi::get_cells -of_objects $sink_pin] if {[llength $sink_periph]} { set intr_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$dout"] if {[llength $intr_pin]} { set sink_pins [::hsi::utils::get_sink_pins "$intr_pin"] foreach pin $sink_pins { set sink_pin $pin } set sink_periph [::hsi::get_cells -of_objects $sink_pin] if {[llength $sink_periph]} { set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]] if { [string compare -nocase "$connected_ip" "xlconcat"] == 0 } { set number [regexp -all -inline -- {[0-9]+} $sink_pin] set dout "dout" set concat_block 1 set intr_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$dout"] if {[llength $intr_pin]} { set sink_pins [::hsi::utils::get_sink_pins "$intr_pin"] foreach pin $sink_pins { set sink_pin $pin } } } } } } } # generate irq id for IRQ1_F2P if { [string compare -nocase "$sink_pin" "IRQ1_F2P"] == 0 } { if {$found == 1} { set irqval $pl_ps_irq1 set pl_ps_irq1 [expr $pl_ps_irq1 + 1] if {$concat_block == "0"} { return [lindex $intr_list_irq1 $irqval] } else { set ret [expr 104 + $number] return $ret } } } elseif { [string compare -nocase "$sink_pin" "IRQ0_F2P"] == 0 } { # generate irq id for IRQ0_F2P if {$found == 1} { set irqval $pl_ps_irq0 set pl_ps_irq0 [expr $pl_ps_irq0 + 1] if {$concat_block == "0"} { return [lindex $intr_list_irq0 $irqval] } else { set ret [expr 89 + $number] return $ret } } } elseif {[regexp "^pl_ps_irq.*" "$sink_pin" match] && \ [expr [string trim "$sink_pin" "pl_ps_irq"] <= 15]} { if {$concat_block == "0"} { set intr_index [string trim "$sink_pin" "pl_ps_irq"] set ret [expr 84 + $intr_index] } else { set ret [expr 84 + $number] } } elseif {[regexp "^pl_psx_irq.*" "$sink_pin" match] && \ [expr [string trim "$sink_pin" "pl_psx_irq"] <= 15]} { if {$concat_block == "0"} { set intr_index [string trim "$sink_pin" "pl_psx_irq"] set ret [expr 104 + $intr_index] } else { set ret [expr 104 + $number] } } else { set sink_periph [::hsi::get_cells -of_objects $sink_pin] if {[llength $sink_periph] == 0 } { break } set connected_ip [get_property IP_NAME [get_cells -hier $sink_periph]] if {[string match -nocase $connected_ip "axi_intc"] } { set sink_pin [::hsi::get_pins -of_objects $periph -filter {TYPE==INTERRUPT && DIRECTION==O}] } if {[llength $sink_pin] == 1} { set port_width [::hsi::utils::get_port_width $sink_pin] } else { foreach pin $sink_pin { set port_width [::hsi::utils::get_port_width $pin] } } } } set id $ret return $ret } proc check_ip_trustzone_state { drv_handle } { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle] if {$index == -1 } { return 0 } set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] if {[lsearch -nocase $avail_param "TRUSTZONE"] >= 0} { set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] # Don't generate status okay when the peripheral is in Secure Trustzone if {[string match -nocase $state "Secure"]} { return 1 } } } elseif {[string match -nocase $proctype "psv_cortexa72"]} { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle] if {$index == -1 } { return 0 } set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] if {[lsearch -nocase $avail_param "TRUSTZONE"] >= 0} { set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] # Don't generate status okay when the peripheral is in Secure Trustzone if {[string match -nocase $state "Secure"]} { return 1 } } } elseif {[string match -nocase $proctype "psx_cortexa78"]} { set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $drv_handle] if {$index == -1 } { return 0 } set avail_param [list_property [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] if {[lsearch -nocase $avail_param "TRUSTZONE"] >= 0} { set state [get_property TRUSTZONE [lindex [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $index]] # Don't generate status okay when the peripheral is in Secure Trustzone if {[string match -nocase $state "Secure"]} { return 1 } } } else { return 0 } } proc generate_cci_node { drv_handle rt_node} { set avail_param [list_property [get_cells -hier $drv_handle]] if {[lsearch -nocase $avail_param "CONFIG.IS_CACHE_COHERENT"] >= 0} { set cci_enable [get_property CONFIG.IS_CACHE_COHERENT [get_cells -hier $drv_handle]] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] set nodma_coherent_list "psu_sata" if {[lsearch $nodma_coherent_list $iptype] >= 0} { #CR 974156, as per 2017.1 PCW update return } if {[string match -nocase $cci_enable "1"]} { hsi::utils::add_new_dts_param $rt_node "dma-coherent" "" boolean } } } #This function is used to generate the reg property #by passing baseaddr and highaddr. #In case if we want rewrite the existing reg property #or 64bit addressing we want to do in reg, we can use this #function. proc generate_reg_property {base high} { set size [format 0x%x [expr {${high} - ${base} + 1}]] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if { $proctype in { "psu_cortexa53" "psv_cortexa72" "psx_cortexa78" }} { # When both base and size are 64 bit if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } # When base has 32 bit and size has 64 bit } elseif {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "0x0 $base $low_size $high_size" } else { set reg "0x0 $base 0x0 $size" } } else { set reg "$base $size" } return $reg } # Generating static vtc node # As it is subcore inside subsystem(ex:hdmi_tx) proc generate_vtc_node {drv_handle base_addr} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] set dts_file [current_dt_tree] set baseaddr_v_tc [format 0x%x [expr $base_addr + 0x10000]] set regval "0x0 $baseaddr_v_tc 0x0 0x10000" if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vtc_node [add_or_get_dt_node -n "v_tc_$drv_handle" -l "v_tc_$drv_handle" -u ${baseaddr_v_tc} -d ${dts_file} -p $bus_node] hsi::utils::add_new_dts_param "${vtc_node}" "clock-names" "clk, s_axi_aclk" stringlist hsi::utils::add_new_dts_param "${vtc_node}" "clocks" "misc_clk_2" reference hsi::utils::add_new_dts_param "${vtc_node}" "compatible" "xlnx,bridge-v-tc-6.1" string hsi::utils::add_new_dts_param "${vtc_node}" "reg" $regval intlist } ================================================ FILE: device_tree/data/device_tree.mld ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # # The Device-Tree BSP generator # OPTION psf_version = 2.1; BEGIN OS device_tree OPTION DRC = device_tree_drc; OPTION OS_TYPE = DTS OPTION SUPPORTED_PERIPHERALS = (microblaze ps7_cortexa9 psu_cortexa53 psv_cortexa72 psx_cortexa78); OPTION DESC = "Generate flat device tree"; OPTION COMPILE_BSP = FALSE; PARAMETER name = dtg_version, desc = "DTG version", default = "2014.4"; PARAMETER name = partial_image, desc = "Partial image Support", type = bool, default = false; PARAMETER name = dt_overlay, desc = "Enable Device-tree Overlay support", type = bool, default = false; PARAMETER name = dt_setbaud, desc = "Set the baud rate", type = int, default = false; PARAMETER name = dt_zocl, desc = "Enable ZOCL Accelerator platform support", type = bool, default = false; PARAMETER name = firmware_name, desc = "Device-tree Overlay Firmware name", type = string, default = ""; PARAMETER name = remove_pl, desc = "Remove PL Support", type = bool, default = false; PARAMETER name = dt_verbose, desc = "VERBOSE logging Support", type = bool, default = false; PARAMETER name = no_alias, desc = "No Alias Support", type = bool, default = false; PARAMETER name = dtg_alias, desc = "DTG generated Alias Support", type = bool, default = false; PARAMETER name = no_labels, desc = "Dont generate the Lables", type = bool, default = false; PARAMETER name = mainline_kernel, desc = "Kernel mainline version", type = enum, values = ("none" = none, "v4.17" = v4.17, "v4.18" = v4.18, "v4.19" = v4.19, "v5.0" = v5.0, "v5.1" = v5.1, "v5.2" = v5.2, "v5.3" = v5.3, "v5.4" = v5.4), default = none; PARAMETER name = overlay_custom_dts, desc = "Overlay custom dts filename", type = string, default =""; PARAMETER name = partial_overlay_custom_dts, desc = "Partial overlay custom dts filename", type = string, default =""; PARAMETER name = bootargs, desc = "Booting arguments", type = string, default = ""; PARAMETER name = console_device, desc = "Instance name of IP core for boot console (e.g. RS232_Uart_1, not xps_uart16550)", type = peripheral_instance, range = (axi_uart16550, axi_uartlite, ps7_uart, psu_uart, psv_sbsauart, psx_sbsauart), default = none; PARAMETER name = periph_type_overrides, desc = "List of peripheral type overrides", type = string, default = ""; PARAMETER name = main_memory, desc = "Name of Main Memory used with PetaLinux", type = peripheral_instance, range = (ps7_ddr, psu_ddr, mpmc, mig_7series, axi_emc), default = none; PARAMETER name = kernel_version, desc = "Target kernel version", type = enum, values = ("2014.4" = 2014.4, "2015.1" = 2015.1, "2015.2" = 2015.2, "2015.3" = 2015.3, "2015.4" = 2015.4, "2016.1" = 2016.1, "2016.2" = 2016.2, "2016.3" = 2016.3, "2016.4" = 2016.4, "2017.1" = 2017.1, "2017.2" = 2017.2, "2017.3" = 2017.3, "2017.4" = 2017.4, "2018.1" = 2018.1, "2018.2" = 2018.2, "2018.3" = 2018.3, "2019.1" = 2019.1, "2019.2" = 2019.2, "2020.1" = 2020.1, "2020.2" = 2020.2, "2021.1" = 2021.1, "2021.2" = 2021.2, "2022.1" = 2022.1, "2022.2" = 2022.2, "2023.1" = 2023.1, "2023.2" = 2023.2, "2024.1" = 2024.1, "2024.2" = 2024.2), default = 2024.2; PARAMETER name = pcw_dts, desc = "Target dts filename for PCW configurations", type = string, default = pcw.dtsi; PARAMETER name = master_dts, desc = "Master dts filename", type = string, default = system-top.dts; PARAMETER name = classic_soc, desc = "To diff classic and dfx flow", type = bool, default = false; END OS ================================================ FILE: device_tree/data/device_tree.mss ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # PARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = device_tree PARAMETER console_device = * PARAMETER main_memory = * END ================================================ FILE: device_tree/data/device_tree.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } proc get_ip_prop {drv_handle pram} { set ip [get_cells -hier $drv_handle] set value [get_property ${pram} $ip] return $value } proc inc_os_prop {drv_handle os_conf_dev_var var_name conf_prop} { set ip_check "False" set os_ip [get_property ${os_conf_dev_var} [get_os]] if {![string match -nocase "" $os_ip]} { set os_ip [get_property ${os_conf_dev_var} [get_os]] set ip_check "True" } set count [hsi::utils::get_os_parameter_value $var_name] if {[llength $count] == 0} { if {[string match -nocase "True" $ip_check]} { set count 1 } else { set count 0 } } if {[string match -nocase "True" $ip_check]} { set ip [get_cells -hier $drv_handle] if {[string match -nocase $os_ip $ip]} { set ip_type [get_property IP_NAME $ip] set_property ${conf_prop} 0 $drv_handle return } } set_property $conf_prop $count $drv_handle incr count ::hsi::utils::set_os_parameter_value $var_name $count } proc gen_count_prop {drv_handle data_dict} { dict for {dev_type dev_conf_mapping} [dict get $data_dict] { set os_conf_dev_var [dict get $data_dict $dev_type "os_device"] set valid_ip_list [dict get $data_dict $dev_type "ip"] set drv_conf [dict get $data_dict $dev_type "drv_conf"] set os_count_name [dict get $data_dict $dev_type "os_count_name"] set slave [get_cells -hier $drv_handle] set iptype [get_property IP_NAME $slave] if {[lsearch $valid_ip_list $iptype] < 0} { continue } set irq_chk [dict get $data_dict $dev_type "irq_chk"] if {![string match -nocase "false" $irq_chk]} { set irq_id [::hsi::utils::get_interrupt_id $slave $irq_chk] if {[llength $irq_id] < 0} { dtg_warning "Fail to located interrupt pin - $irq_chk. The $drv_conf is not set for $dev_type" continue } } inc_os_prop $drv_handle $os_conf_dev_var $os_count_name $drv_conf } } proc gen_dev_conf {} { # data to populated certain configs for different devices set data_dict { uart { os_device "CONFIG.console_device" ip "axi_uartlite axi_uart16550 ps7_uart psu_uart psv_uart psx_sbsauart" os_count_name "serial_count" drv_conf "CONFIG.port-number" irq_chk "false" } mdm_uart { os_device "CONFIG.console_device" ip "mdm" os_count_name "serial_count" drv_conf "CONFIG.port-number" irq_chk "Interrupt" } syace { os_device "sysace_device" ip "axi_sysace" os_count_name "sysace_count" drv_conf "CONFIG.port-number" irq_chk "false" } traffic_gen { os_device "trafficgen_device" ip "axi_traffic_gen" os_count_name "trafficgen_count" drv_conf "CONFIG.xlnx,device-id" irq_chk "false" } } # update CONFIG. for each driver when match driver is found foreach drv [get_drivers] { gen_count_prop $drv $data_dict } } # For calling from top level BSP proc bsp_drc {os_handle} { } # If standalone purpose proc device_tree_drc {os_handle} { bsp_drc $os_handle hsi::utils::add_new_child_node $os_handle "global_params" } proc extract_dts_name {override value} { set idx [lsearch -exact $override $value] set var [lreplace $override $idx $idx] return $var } proc gen_edac_node {} { set dts_file [get_property CONFIG.pcw_dts [get_os]] set edac_node [add_or_get_dt_node -n &xilsem_edac -d $dts_file] set pspmc [get_cells -hier -filter {IP_NAME == "pspmc"}] if {[llength $pspmc]} { if { [get_property CONFIG.SEM_MEM_SCAN $pspmc] || [get_property CONFIG.SEM_NPI_SCAN $pspmc] } { hsi::utils::add_new_dts_param "${edac_node}" "status" "okay" string } } } proc gen_ddrmc_node {} { set dts_file [get_property CONFIG.pcw_dts [get_os]] set ddrmc [get_cells -hier -filter {IP_NAME == "noc_mc_ddr4"}] if {[llength $ddrmc]} { set i 0 foreach mc $ddrmc { set ddrmc_node [add_or_get_dt_node -n &mc$i -d $dts_file] if { [get_property CONFIG.MC_ECC $mc] } { hsi::utils::add_new_dts_param "${ddrmc_node}" "status" "okay" string } incr i } } } proc gen_sata_laneinfo {} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {$remove_pl} { return 0 } foreach ip [get_cells] { set slane 0 set freq {} set ip_type [get_property IP_TYPE [get_cells $ip]] #if {$ip_type eq ""} { # set ps $ip #} set ps $ip } set param0 "/bits/ 8 <0x18 0x40 0x18 0x28>" set param1 "/bits/ 8 <0x06 0x14 0x08 0x0E>" set param2 "/bits/ 8 <0x13 0x08 0x4A 0x06>" set param3 "/bits/ 16 <0x96A4 0x3FFC>" set param4 "/bits/ 8 <0x1B 0x4D 0x18 0x28>" set param5 "/bits/ 8 <0x06 0x19 0x08 0x0E>" set param6 " /bits/ 8 <0x13 0x08 0x4A 0x06>" set param7 "/bits/ 16 <0x96A4 0x3FFC>" set param_list "ceva,p%d-cominit-params ceva,p%d-comwake-params ceva,p%d-burst-params ceva,p%d-retry-params" while {$slane < 2} { if {[get_property CONFIG.PSU__SATA__LANE$slane\__ENABLE [get_cells $ps]] == 1} { set gt_lane [get_property CONFIG.PSU__SATA__LANE$slane\__IO [get_cells $ps]] regexp [0-9] $gt_lane gt_lane lappend freq [get_property CONFIG.PSU__SATA__REF_CLK_FREQ [get_cells $ps]] } else { lappend freq 0 } incr slane } foreach {i j} $freq { set i [expr {$i ? $i : $j}] set j [expr {$j ? $j : $i}] } lset freq 0 $i lset freq 1 $j set dts_file [get_property CONFIG.pcw_dts [get_os]] set sata_node [add_or_get_dt_node -n &sata -d $dts_file] set hsi_version [get_hsi_version] set ver [split $hsi_version "."] set version [lindex $ver 0] set slane 0 while {$slane < 2} { set f [lindex $freq $slane] set count 0 if {$f != 0} { while {$count < 4} { if {$version < 2018} { dtg_warning "quotes to be removed or use 2018.1 version for $sata_node params param0..param7" } set val_name [format [lindex $param_list $count] $slane] switch $count { "0" { hsi::utils::add_new_dts_param $sata_node $val_name $param0 noformating } "1" { hsi::utils::add_new_dts_param $sata_node $val_name $param1 noformating } "2" { hsi::utils::add_new_dts_param $sata_node $val_name $param2 noformating } "3" { hsi::utils::add_new_dts_param $sata_node $val_name $param3 noformating } "4" { hsi::utils::add_new_dts_param $sata_node $val_name $param4 noformating } "5" { hsi::utils::add_new_dts_param $sata_node $val_name $param5 noformating } "6" { hsi::utils::add_new_dts_param $sata_node $val_name $param6 noformating } "7" { hsi::utils::add_new_dts_param $sata_node $val_name $param7 noformating } } incr count } } incr slane } } proc gen_ext_axi_interface {} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {$remove_pl} { return 0 } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { set ext_axi_intf [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]] -filter {INSTANCE ==""}] set hsi_version [get_hsi_version] set ver [split $hsi_version "."] set version [lindex $ver 0] set intf_count 0 foreach drv_handle $ext_axi_intf { set base [string tolower [get_property BASE_VALUE $drv_handle]] set high [string tolower [get_property HIGH_VALUE $drv_handle]] set size [format 0x%x [expr {${high} - ${base} + 1}]] set default_dts [get_property CONFIG.pcw_dts [get_os]] set root_node [add_or_get_dt_node -n / -d ${default_dts}] if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } } else { set reg "0x0 $base 0x0 $size" } regsub -all {^0x} $base {} base set ext_int_node [add_or_get_dt_node -n $drv_handle -l $drv_handle$intf_count -u $base -d $default_dts -p $root_node] hsi::utils::add_new_dts_param $ext_int_node "reg" "$reg" intlist incr intf_count if {$version >= 2018} { hsi::utils::add_new_dts_param "${ext_int_node}" "/* This is a external AXI interface, user may need to update the entries */" "" comment } } } } proc gen_include_headers {} { foreach i [get_sw_cores device_tree] { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set kernel_ver [get_property CONFIG.kernel_version [get_os]] set includes_dir [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${kernel_ver}/include"] set dir_path "./" # Copy full include directory to dt WS if {[file exists $includes_dir]} { file delete -force -- $dir_path/include file copy -force $includes_dir $dir_path } } } proc gen_include_dtfile {args} { set kernel_dtsi [lindex $args 0] set fp [open $kernel_dtsi r] set file_data [read $fp] set data [split $file_data "\n"] set include_regexp {^#include \".*\.dts.*\"$} foreach line $data { if {[regexp $include_regexp $line matched]} { set include_dt [lindex [split $line " "] 1] regsub -all " |\t|;|\"" $include_dt {} include_dt foreach file [glob [file normalize [file dirname ${kernel_dtsi}]/*]] { # NOTE: ./ works only if we did not change our directory if {[regexp $include_dt $file match]} { file copy -force $file ./ gen_include_dtfile "$file" break } } } } } proc gen_board_info {} { # periph_type_overrides = {BOARD KC705 full/lite} or {BOARD ZYNQ} or {BOARD ZC1751 ES2/ES1} set overrides [get_property CONFIG.periph_type_overrides [get_os]] if {[string match $overrides ""]} { return } foreach i [get_sw_cores device_tree] { foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set first_element [lindex $override 0] set dtsi_file [lindex $override 1] if {[file exists $dtsi_file]} { set dir [pwd] set pathtype [file pathtype $dtsi_file] if {[string match -nocase $pathtype "relative"]} { dtg_warning "checking file:$dtsi_file pwd:$dir" #Get the absolute path from relative path set dtsi_file [file normalize $dtsi_file] } file copy -force $dtsi_file ./ update_system_dts_include [file tail $dtsi_file] return } set kernel_ver [get_property CONFIG.kernel_version [get_os]] set includes_dir [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${kernel_ver}/include"] set dir_path "./" # Copy full include directory to dt WS if {[file exists $includes_dir]} { file delete -force -- $dir_path/include file copy -force $includes_dir $dir_path } set dts_name [string tolower [lindex $override 1]] if {[string match -nocase $dts_name "template"]} { return } if {[llength $dts_name] == 0} { return } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { set mainline_dtsi [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${mainline_ker}/board"] if {[file exists $mainline_dtsi]} { set mainline_board_file 0 foreach file [glob [file normalize [file dirname ${mainline_dtsi}]/board/*]] { set dtsi_name "$dts_name.dtsi" # NOTE: ./ works only if we did not change our directory if {[regexp $dtsi_name $file match]} { file copy -force $file ./ update_system_dts_include [file tail $file] set mainline_board_file 1 } } if {$mainline_board_file == 0} { error "Error:$dtsi_name board file is not present in DTG. Please add a vaild board." } } } else { set kernel_dtsi [file normalize "[get_property "REPOSITORY" $i]/data/kernel_dtsi/${kernel_ver}/BOARD"] if {[file exists $kernel_dtsi]} { set valid_board_file 0 foreach file [glob [file normalize [file dirname ${kernel_dtsi}]/BOARD/*]] { set dtsi_name "$dts_name.dtsi" # NOTE: ./ works only if we did not change our directory if {[regexp $dtsi_name $file match]} { file copy -force $file ./ update_system_dts_include [file tail $file] set valid_board_file 1 gen_include_dtfile "${file}" break } } if {$valid_board_file == 0} { error "Error:$dtsi_name board file is not present in DTG. Please add a valid board." } set default_dts [get_property CONFIG.master_dts [get_os]] set root_node [add_or_get_dt_node -n / -d ${default_dts}] } else { puts "File not found\n\r" } } } } } } proc gen_zynqmp_ccf_clk {} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set ccf_node [add_or_get_dt_node -n "&pss_ref_clk" -d $default_dts] set periph_list [get_cells -hier] foreach periph $periph_list { set zynq_ultra_ps [get_property IP_NAME $periph] if {[string match -nocase $zynq_ultra_ps "zynq_ultra_ps_e"] } { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__PSS_REF_CLK__FREQMHZ"] >= 0} { set freq [get_property CONFIG.PSU__PSS_REF_CLK__FREQMHZ [get_cells -hier $periph]] if {[string match -nocase $freq "33.333"]} { return } else { dtg_warning "Frequency $freq used instead of 33.333" hsi::utils::add_new_dts_param "${ccf_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } } } set ccf_node [add_or_get_dt_node -n "&video_clk" -d $default_dts] set periph_list [get_cells -hier] foreach periph $periph_list { set zynq_ultra_ps [get_property IP_NAME $periph] if {[string match -nocase $zynq_ultra_ps "zynq_ultra_ps_e"] } { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ"] >= 0} { set freq [get_property CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ [get_cells -hier $periph]] if {[string match -nocase $freq "27"]} { return } else { dtg_warning "Frequency $freq used instead of 27.00" hsi::utils::add_new_dts_param "${ccf_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } } } } proc gen_opp_freq {} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set cpu_opp_table [add_or_get_dt_node -n "&cpu_opp_table" -d $default_dts] set periph_list [get_cells -hier] set opp_freq "" set add_opp_prop "" foreach periph $periph_list { set proc_ps [get_property IP_NAME $periph] if {[string match -nocase $proc_ps "zynq_ultra_ps_e"] } { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ"] >= 0} { set act_freq "" set div "" set freq [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ [get_cells -hier $periph]] if {[string match -nocase $freq "1200"]} { # This is the default value set, so no need to calcualte return } if {[lsearch -nocase $avail_param "CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ"] >= 0} { set act_freq [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ [get_cells -hier $periph]] set act_freq [expr $act_freq * 1000000] } if {[lsearch -nocase $avail_param "CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0"] >= 0} { set div [get_property CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 [get_cells -hier $periph]] } if {[llength $act_freq] && [llength $div]} { set opp_freq [expr $act_freq * $div] } # if design don't have clock configs then skip adding new opps if {$opp_freq == ""} { return } # Remove default opps hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp00" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp01" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp02" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp03" "" boolean } } if { $proc_ps in { "versal_cips" "ps_wizard" }} { set ps_pmc_params [get_property CONFIG.PS_PMC_CONFIG [get_cells -hier $periph]] if {[llength $ps_pmc_params ]} { set act_freq "" set div "" set clkoutdiv "" if {[dict exists $ps_pmc_params "PMC_REF_CLK_FREQMHZ"]} { set act_freq [dict get $ps_pmc_params PMC_REF_CLK_FREQMHZ] } if {[dict exists $ps_pmc_params "PS_CRF_APLL_CTRL_FBDIV"]} { set div [dict get $ps_pmc_params PS_CRF_APLL_CTRL_FBDIV] } if {[dict exists $ps_pmc_params "PS_CRF_APLL_CTRL_CLKOUTDIV"]} { set clkoutdiv [dict get $ps_pmc_params PS_CRF_APLL_CTRL_CLKOUTDIV] } if {[llength $act_freq] && [llength $div] && [llength $clkoutdiv]} { set opp_freq [expr round([expr ($act_freq * $div) / $clkoutdiv]) * 1000000] } # if design don't have clock configs then skip adding new opps if {$opp_freq == ""} { return } } # Remove default opps hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp00" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp01" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp02" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp03" "" boolean } if {[string match -nocase $proc_ps "psx_wizard"] } { set overrides [get_property CONFIG.periph_type_overrides [get_os]] set board_dtsi_file "" foreach override $overrides { if {[lindex $override 0] == "BOARD"} { set board_dtsi_file [lindex $override 1] } } #TMP fix to support ipp fixed clocks if {[string match -nocase $board_dtsi_file "versal-net-ipp-rev1.9"]} { return } #NOTE: CONFIG.PSX_PMCX_CONFIG_INTERNAL this may change set psx_pmcx_params [get_property CONFIG.PSX_PMCX_CONFIG_INTERNAL [get_cells -hier $periph]] if {[llength $psx_pmcx_params]} { set act_freq "" set div "" set clkoutdiv "" if {[dict exists $psx_pmcx_params "PMCX_REF_CLK_FREQMHZ"]} { set act_freq [dict get $psx_pmcx_params PMCX_REF_CLK_FREQMHZ] } if {[dict exists $psx_pmcx_params "PSX_CRF_APLL1_CTRL_FBDIV"]} { set div [dict get $psx_pmcx_params PSX_CRF_APLL1_CTRL_FBDIV] } if {[dict exists $psx_pmcx_params "PSX_CRF_APLL1_CTRL_CLKOUTDIV"]} { set clkoutdiv [dict get $psx_pmcx_params PSX_CRF_APLL1_CTRL_CLKOUTDIV] } if {[llength $act_freq] && [llength $div] && [llength $clkoutdiv]} { set opp_freq [expr round([expr ($act_freq * $div) / $clkoutdiv]) * 1000000] } } # if design don't have clock configs then skip adding new opps if {$opp_freq == ""} { return } # Remove default opps hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-1066000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-1866000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-1900000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-1999000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-2050000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-2100000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-2200000000" "" boolean hsi::utils::add_new_dts_param "$cpu_opp_table" "/delete-node/ opp-2400000000" "" boolean } } if {[llength $opp_freq]} { set opp00_result [expr int ([expr $opp_freq / 1])] set opp01_result [expr int ([expr $opp_freq / 2])] set opp02_result [expr int ([expr $opp_freq / 3])] set opp03_result [expr int ([expr $opp_freq / 4])] set opp00 "/bits/ 64 <$opp00_result>" set opp01 "/bits/ 64 <$opp01_result>" set opp02 "/bits/ 64 <$opp02_result>" set opp03 "/bits/ 64 <$opp03_result>" set opp_microvolt "<1000000>" set clock_latency "<500000>" # Create opp table as per dt-bindings set opp00_table [add_or_get_dt_node -n "opp-${opp00_result}" -d $default_dts -p $cpu_opp_table] hsi::utils::add_new_dts_param "$opp00_table" "opp-hz" $opp00 noformating hsi::utils::add_new_dts_param "$opp00_table" "opp-microvolt" $opp_microvolt noformating hsi::utils::add_new_dts_param "$opp00_table" "clock-latency-ns" $clock_latency noformating set opp01_table [add_or_get_dt_node -n "opp-${opp01_result}" -d $default_dts -p $cpu_opp_table] hsi::utils::add_new_dts_param "$opp01_table" "opp-hz" $opp01 noformating hsi::utils::add_new_dts_param "$opp01_table" "opp-microvolt" $opp_microvolt noformating hsi::utils::add_new_dts_param "$opp01_table" "clock-latency-ns" $clock_latency noformating set opp02_table [add_or_get_dt_node -n "opp-${opp02_result}" -d $default_dts -p $cpu_opp_table] hsi::utils::add_new_dts_param "$opp02_table" "opp-hz" $opp02 noformating hsi::utils::add_new_dts_param "$opp02_table" "opp-microvolt" $opp_microvolt noformating hsi::utils::add_new_dts_param "$opp02_table" "clock-latency-ns" $clock_latency noformating set opp03_table [add_or_get_dt_node -n "opp-${opp03_result}" -d $default_dts -p $cpu_opp_table] hsi::utils::add_new_dts_param "$opp03_table" "opp-hz" $opp03 noformating hsi::utils::add_new_dts_param "$opp03_table" "opp-microvolt" $opp_microvolt noformating hsi::utils::add_new_dts_param "$opp03_table" "clock-latency-ns" $clock_latency noformating } } proc gen_versal_clk {} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set ref_node [add_or_get_dt_node -n "&ref_clk" -d $default_dts] set pl_alt_ref_node [add_or_get_dt_node -n "&pl_alt_ref_clk" -d $default_dts] set periph_list [get_cells -hier] foreach periph $periph_list { set versal_ps [get_property IP_NAME $periph] if { $versal_ps in { "versal_cips" "ps_wizard" }} { set ver [get_comp_ver $periph] if {$ver < 3.0} { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PMC_REF_CLK_FREQMHZ"] >= 0} { set freq [get_property CONFIG.PMC_REF_CLK_FREQMHZ [get_cells -hier $periph]] if {![string match -nocase $freq "33.333"]} { dtg_warning "Frequency $freq used instead of 33.333" hsi::utils::add_new_dts_param "${ref_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ"] >= 0} { set freq [get_property CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ [get_cells -hier $periph]] if {![string match -nocase $freq "33.333"]} { dtg_warning "Frequency $freq used instead of 33.333" hsi::utils::add_new_dts_param "${pl_alt_ref_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } } } if {[string match -nocase $versal_ps "pspmc"] } { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PMC_REF_CLK_FREQMHZ"] >= 0} { set freq [get_property CONFIG.PMC_REF_CLK_FREQMHZ [get_cells -hier $periph]] if {![string match -nocase $freq "33.333"]} { dtg_warning "Frequency $freq used instead of 33.333" hsi::utils::add_new_dts_param "${ref_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } if {[lsearch -nocase $avail_param "CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ"] >= 0} { set freq [get_property CONFIG.PMC_PL_ALT_REF_CLK_FREQMHZ [get_cells -hier $periph]] if {![string match -nocase $freq "33.333"]} { dtg_warning "Frequency $freq used instead of 33.333" hsi::utils::add_new_dts_param "${pl_alt_ref_node}" "clock-frequency" [scan [expr $freq * 1000000] "%d"] int } } } } } proc gen_zynqmp_pinctrl {} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set pinctrl_node [add_or_get_dt_node -n "&pinctrl0" -d $default_dts] set periph_list [get_cells -hier] foreach periph $periph_list { set zynq_ultra_ps [get_property IP_NAME $periph] if {[string match -nocase $zynq_ultra_ps "zynq_ultra_ps_e"] } { set avail_param [list_property [get_cells -hier $periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__UART1__PERIPHERAL__IO"] >= 0} { set uart1_io [get_property CONFIG.PSU__UART1__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $uart1_io "EMIO"]} { set pinctrl_uart1_default [add_or_get_dt_node -n "uart1-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_uart1_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart1_default" "/delete-node/ conf" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart1_default" "/delete-node/ conf-rx" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart1_default" "/delete-node/ conf-tx" "" boolean } } if {[lsearch -nocase $avail_param "CONFIG.PSU__UART0__PERIPHERAL__IO"] >= 0} { set uart0_io [get_property CONFIG.PSU__UART0__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $uart0_io "EMIO"]} { set pinctrl_uart0_default [add_or_get_dt_node -n "uart0-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_uart0_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart0_default" "/delete-node/ conf" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart0_default" "/delete-node/ conf-rx" "" boolean hsi::utils::add_new_dts_param "$pinctrl_uart0_default" "/delete-node/ conf-tx" "" boolean } } if {[lsearch -nocase $avail_param "CONFIG.PSU__CAN1__PERIPHERAL__IO"] >= 0} { set can1_io [get_property CONFIG.PSU__CAN1__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $can1_io "EMIO"]} { set pinctrl_can1_default [add_or_get_dt_node -n "can1-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_can1_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_can1_default" "/delete-node/ conf" "" boolean hsi::utils::add_new_dts_param "$pinctrl_can1_default" "/delete-node/ conf-rx" "" boolean hsi::utils::add_new_dts_param "$pinctrl_can1_default" "/delete-node/ conf-tx" "" boolean } } if {[lsearch -nocase $avail_param "CONFIG.PSU__SD1__PERIPHERAL__IO"] >= 0} { set sd1_io [get_property CONFIG.PSU__SD1__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $sd1_io "EMIO"]} { set pinctrl_sdhci1_default [add_or_get_dt_node -n "sdhci1-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ conf" "" boolean hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ conf-cd" "" boolean hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ mux-cd" "" boolean hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ conf-wp" "" boolean hsi::utils::add_new_dts_param "$pinctrl_sdhci1_default" "/delete-node/ mux-wp" "" boolean } } if {[lsearch -nocase $avail_param "CONFIG.PSU__ENET3__PERIPHERAL__IO"] >= 0} { set gem3_io [get_property CONFIG.PSU__ENET3__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $gem3_io "EMIO"]} { set pinctrl_gem3_default [add_or_get_dt_node -n "gem3-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ conf" "" boolean hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ conf-rx" "" boolean hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ conf-tx" "" boolean hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ conf-mdio" "" boolean hsi::utils::add_new_dts_param "$pinctrl_gem3_default" "/delete-node/ mux-mdio" "" boolean } } if {[lsearch -nocase $avail_param "CONFIG.PSU__I2C1__PERIPHERAL__IO"] >= 0} { set i2c1_io [get_property CONFIG.PSU__I2C1__PERIPHERAL__IO [get_cells -hier $periph]] if {[string match -nocase $i2c1_io "EMIO"]} { set pinctrl_i2c1_default [add_or_get_dt_node -n "i2c1-default" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_i2c1_default" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_i2c1_default" "/delete-node/ conf" "" boolean set pinctrl_i2c1_gpio [add_or_get_dt_node -n "i2c1-gpio" -d $default_dts -p $pinctrl_node] hsi::utils::add_new_dts_param "$pinctrl_i2c1_gpio" "/delete-node/ mux" "" boolean hsi::utils::add_new_dts_param "$pinctrl_i2c1_gpio" "/delete-node/ conf" "" boolean } } } } } proc gen_zocl_node {} { set zocl [get_property CONFIG.dt_zocl [get_os]] puts "zocl:$zocl" set remove_pl [get_property CONFIG.remove_pl [get_os]] set ext_platform [get_property platform.extensible [get_os]] puts "ext_platform:$ext_platform" set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {$remove_pl} { return } if {!$zocl} { return } #Check if design has any PL ip's set ip_count 0 foreach ip [get_drivers] { if {[is_pl_ip $ip]} { incr ip_count break } } if {$ip_count == 0} { dtg_warning "dt_zocl enabled and No PL ip's found in specified design, skip adding zocl node" return } set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set default_dts pl.dtsi set zocl_node [add_or_get_dt_node -n "zyxclmm_drm" -d ${default_dts} -p $bus_node] if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "ps7_cortexa9"]} { hsi::utils::add_new_dts_param $zocl_node "compatible" "xlnx,zocl" string } else { hsi::utils::add_new_dts_param $zocl_node "compatible" "xlnx,zocl-versal" string } #if axi_intc exists in the design then add 0 to 31 extended interrupts. set axi_intr_ctrl [get_cells -hier -filter {IP_NAME == axi_intc}] if {[llength $axi_intr_ctrl]} { set intr_ctrl_len [llength $axi_intr_ctrl] puts "intr_ctrl_len:$intr_ctrl_len" set int0 [lindex $axi_intr_ctrl 0] foreach ip [get_drivers] { if {[string compare -nocase $ip $int0] == 0} { set target_handle $ip } } set intr [get_property CONFIG.interrupt-parent $target_handle] set int1 [lindex $axi_intr_ctrl 1] foreach ip [get_drivers] { if {[string compare -nocase $ip $int1] == 0} { set target_handle $ip } } set intr [get_property CONFIG.interrupt-parent $target_handle] switch $intr_ctrl_len { "1" { set ref [lindex $axi_intr_ctrl 0] append ref " 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>, <&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>, <&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>, <&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>, <&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>, <&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4 " hsi::utils::add_new_dts_param $zocl_node "interrupts-extended" $ref reference } "2" { set ref [lindex $axi_intr_ctrl 0] append ref " 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>, <&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>, <&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>, <&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>, <&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>, <&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4>, <&[lindex $axi_intr_ctrl 1] 0 4>, <&[lindex $axi_intr_ctrl 1] 1 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 3 4>, <&[lindex $axi_intr_ctrl 1] 4 4>, <&[lindex $axi_intr_ctrl 1] 5 4>, <&[lindex $axi_intr_ctrl 1] 6 4>, <&[lindex $axi_intr_ctrl 1] 7 4>, <&[lindex $axi_intr_ctrl 1] 8 4>, <&[lindex $axi_intr_ctrl 1] 9 4>, <&[lindex $axi_intr_ctrl 1] 10 4>, <&[lindex $axi_intr_ctrl 1] 11 4>, <&[lindex $axi_intr_ctrl 1] 12 4>, <&[lindex $axi_intr_ctrl 1] 13 4>, <&[lindex $axi_intr_ctrl 1] 14 4>, <&[lindex $axi_intr_ctrl 1] 15 4>, <&[lindex $axi_intr_ctrl 1] 16 4>, <&[lindex $axi_intr_ctrl 1] 17 4>, <&[lindex $axi_intr_ctrl 1] 18 4>, <&[lindex $axi_intr_ctrl 1] 19 4>, <&[lindex $axi_intr_ctrl 1] 20 4>, <&[lindex $axi_intr_ctrl 1] 21 4>, <&[lindex $axi_intr_ctrl 1] 22 4>, <&[lindex $axi_intr_ctrl 1] 23 4>, <&[lindex $axi_intr_ctrl 1] 24 4>, <&[lindex $axi_intr_ctrl 1] 25 4>, <&[lindex $axi_intr_ctrl 1] 26 4>, <&[lindex $axi_intr_ctrl 1] 27 4>, <&[lindex $axi_intr_ctrl 1] 28 4>, <&[lindex $axi_intr_ctrl 1] 29 4>, <&[lindex $axi_intr_ctrl 1] 30 4 " hsi::utils::add_new_dts_param $zocl_node "interrupts-extended" $ref reference } "3" { set ref [lindex $axi_intr_ctrl 0] append ref " 0 4>, <&[lindex $axi_intr_ctrl 0] 1 4>, <&[lindex $axi_intr_ctrl 0] 2 4>, <&[lindex $axi_intr_ctrl 0] 3 4>, <&[lindex $axi_intr_ctrl 0] 4 4>, <&[lindex $axi_intr_ctrl 0] 5 4>, <&[lindex $axi_intr_ctrl 0] 6 4>, <&[lindex $axi_intr_ctrl 0] 7 4>, <&[lindex $axi_intr_ctrl 0] 8 4>, <&[lindex $axi_intr_ctrl 0] 9 4>, <&[lindex $axi_intr_ctrl 0] 10 4>, <&[lindex $axi_intr_ctrl 0] 11 4>, <&[lindex $axi_intr_ctrl 0] 12 4>, <&[lindex $axi_intr_ctrl 0] 13 4>, <&[lindex $axi_intr_ctrl 0] 14 4>, <&[lindex $axi_intr_ctrl 0] 15 4>, <&[lindex $axi_intr_ctrl 0] 16 4>, <&[lindex $axi_intr_ctrl 0] 17 4>, <&[lindex $axi_intr_ctrl 0] 18 4>, <&[lindex $axi_intr_ctrl 0] 19 4>, <&[lindex $axi_intr_ctrl 0] 20 4>, <&[lindex $axi_intr_ctrl 0] 21 4>, <&[lindex $axi_intr_ctrl 0] 22 4>, <&[lindex $axi_intr_ctrl 0] 23 4>, <&[lindex $axi_intr_ctrl 0] 24 4>, <&[lindex $axi_intr_ctrl 0] 25 4>, <&[lindex $axi_intr_ctrl 0] 26 4>, <&[lindex $axi_intr_ctrl 0] 27 4>, <&[lindex $axi_intr_ctrl 0] 28 4>, <&[lindex $axi_intr_ctrl 0] 29 4>, <&[lindex $axi_intr_ctrl 0] 30 4>, <&[lindex $axi_intr_ctrl 0] 31 4>, <&[lindex $axi_intr_ctrl 1] 0 4>, <&[lindex $axi_intr_ctrl 1] 1 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 2 4>, <&[lindex $axi_intr_ctrl 1] 3 4>, <&[lindex $axi_intr_ctrl 1] 4 4>, <&[lindex $axi_intr_ctrl 1] 5 4>, <&[lindex $axi_intr_ctrl 1] 6 4>, <&[lindex $axi_intr_ctrl 1] 7 4>, <&[lindex $axi_intr_ctrl 1] 8 4>, <&[lindex $axi_intr_ctrl 1] 9 4>, <&[lindex $axi_intr_ctrl 1] 10 4>, <&[lindex $axi_intr_ctrl 1] 11 4>, <&[lindex $axi_intr_ctrl 1] 12 4>, <&[lindex $axi_intr_ctrl 1] 13 4>, <&[lindex $axi_intr_ctrl 1] 14 4>, <&[lindex $axi_intr_ctrl 1] 15 4>, <&[lindex $axi_intr_ctrl 1] 16 4>, <&[lindex $axi_intr_ctrl 1] 17 4>, <&[lindex $axi_intr_ctrl 1] 18 4>, <&[lindex $axi_intr_ctrl 1] 19 4>, <&[lindex $axi_intr_ctrl 1] 20 4>, <&[lindex $axi_intr_ctrl 1] 21 4>, <&[lindex $axi_intr_ctrl 1] 22 4>, <&[lindex $axi_intr_ctrl 1] 23 4>, <&[lindex $axi_intr_ctrl 1] 24 4>, <&[lindex $axi_intr_ctrl 1] 25 4>, <&[lindex $axi_intr_ctrl 1] 26 4>, <&[lindex $axi_intr_ctrl 1] 27 4>, <&[lindex $axi_intr_ctrl 1] 28 4>, <&[lindex $axi_intr_ctrl 1] 29 4>, <&[lindex $axi_intr_ctrl 1] 30 4>, <&[lindex $axi_intr_ctrl 1] 31 4>, <&[lindex $axi_intr_ctrl 2] 0 4>, <&[lindex $axi_intr_ctrl 2] 1 4>, <&[lindex $axi_intr_ctrl 2] 2 4>, <&[lindex $axi_intr_ctrl 2] 3 4>, <&[lindex $axi_intr_ctrl 2] 4 4>, <&[lindex $axi_intr_ctrl 2] 5 4>, <&[lindex $axi_intr_ctrl 2] 6 4>, <&[lindex $axi_intr_ctrl 2] 7 4>, <&[lindex $axi_intr_ctrl 2] 8 4>, <&[lindex $axi_intr_ctrl 2] 9 4>, <&[lindex $axi_intr_ctrl 2] 10 4>, <&[lindex $axi_intr_ctrl 2] 11 4>, <&[lindex $axi_intr_ctrl 2] 12 4>, <&[lindex $axi_intr_ctrl 2] 13 4>, <&[lindex $axi_intr_ctrl 2] 14 4>, <&[lindex $axi_intr_ctrl 2] 15 4>, <&[lindex $axi_intr_ctrl 2] 16 4>, <&[lindex $axi_intr_ctrl 2] 17 4>, <&[lindex $axi_intr_ctrl 2] 18 4>, <&[lindex $axi_intr_ctrl 2] 19 4>, <&[lindex $axi_intr_ctrl 2] 20 4>, <&[lindex $axi_intr_ctrl 2] 21 4>, <&[lindex $axi_intr_ctrl 2] 22 4 >, <&[lindex $axi_intr_ctrl 2] 23 4>, <&[lindex $axi_intr_ctrl 2] 24 4>, <&[lindex $axi_intr_ctrl 2] 25 4>, <&[lindex $axi_intr_ctrl 2] 26 4>, <&[lindex $axi_intr_ctrl 2] 27 4>, <&[lindex $axi_intr_ctrl 2] 28 4>, <&[lindex $axi_intr_ctrl 2] 29 4>, <&[lindex $axi_intr_ctrl 2] 30 4 " hsi::utils::add_new_dts_param $zocl_node "interrupts-extended" $ref reference } } } else { # if axi_intc not found then use gic controller set intr_num "0x0 0x89 0x4>, <0x0 0x90 0x4>, <0x0 0x91 0x4>, <0x0 0x92 0x4>, <0x0 0x93 0x4>, <0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4" hsi::utils::add_new_dts_param $zocl_node "interrupt-parent" gic reference hsi::utils::add_new_dts_param $zocl_node "interrupts" $intr_num intlist } set decouplers [get_cells -hier -filter {IP_NAME == "dfx_decoupler"}] set count 1 foreach decoupler $decouplers { if { $count == 1 } { hsi::utils::add_new_dts_param "$zocl_node" "xlnx,pr-decoupler" "" boolean } else { #zocl driver not supporting multiple decouplers so display warning. dtg_warning "Multiple dfx_decoupler IPs found in the design,\ using pr-isolation-addr from [lindex [split $decouplers " "] 0] IP" break } set baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $decoupler]] if {[llength $baseaddr]} { set baseaddr "0x0 $baseaddr" hsi::utils::add_new_dts_param "$zocl_node" "xlnx,pr-isolation-addr" "$baseaddr" intlist } incr count } } proc generate {lib_handle} { add_skeleton foreach drv_handle [get_drivers] { if {[string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"]} { gen_peripheral_nodes $drv_handle "create_node_only" } } foreach drv_handle [get_drivers] { # generate the default properties if {![string match -nocase [common::get_property IP_NAME [get_cells -hier $drv_handle]] "axi_intc"]} { gen_peripheral_nodes $drv_handle "create_node_only" } gen_reg_property $drv_handle gen_compatible_property $drv_handle gen_drv_prop_from_ip $drv_handle gen_interrupt_property $drv_handle gen_clk_property $drv_handle } gen_board_info gen_include_headers set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { gen_sata_laneinfo gen_zynqmp_ccf_clk gen_versal_clk gen_opp_freq gen_zynqmp_pinctrl gen_zocl_node if {[string match -nocase $proctype "psv_cortexa72"]} { gen_edac_node gen_ddrmc_node } } } if {[string match -nocase $proctype "ps7_cortexa9"]} { set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { gen_zocl_node } } gen_ext_axi_interface } proc update_nonregnodes {} { # Check the each node and if any node doesnot have # reg property move them to root node or fpga node set dts_files [get_dt_trees] foreach dts_file $dts_files { if {[regexp "pl.*.dtsi" $dts_file match]} { current_dt_tree $dts_file set dts_nodes [get_all_tree_nodes $dts_file] set overlay_parent "[detect_fpga_noderef]" foreach dts_node $dts_nodes { # Using firmware-name prop to detect the fpga node if {[llength [get_property CONFIG.firmware-name $dts_node]]} { set overlay_parent "${dts_node}" } } foreach dts_node $dts_nodes { if {[regexp "/" $dts_node match]} { continue } set current_parent [get_property PARENT $dts_node] set reg_prop [get_property CONFIG.reg $dts_node] # If no reg prop in node move them from amba or amba_pl to # fpga node if its overlay else root(/) node if {![llength "${reg_prop}"]} { if {[regexp "&amba" ${current_parent} match]} { # Overlay cases if {[lsearch $dts_nodes $overlay_parent] >= 0} { set_property PARENT "${overlay_parent}" $dts_node } else { dtg_debug "Fpga parent not found $overlay_parent in $dts_file" } } elseif {[regexp "amba_pl:pl-bus" ${current_parent} match]} { # Non Overlay cases set_property PARENT "/" $dts_node } } } } } } proc post_generate {os_handle} { update_chosen $os_handle update_alias $os_handle update_cpu_node $os_handle gen_dev_conf foreach drv_handle [get_drivers] { gen_peripheral_nodes $drv_handle update_endpoints $drv_handle } global zynq_soc_dt_tree delete_objs [get_dt_tree $zynq_soc_dt_tree] remove_empty_reference_node remove_main_memory_node update_nonregnodes } proc add_skeleton {} { set default_dts [get_property CONFIG.master_dts [get_os]] set system_root_node [add_or_get_dt_node -n "/" -d ${default_dts}] set chosen_node [add_or_get_dt_node -n "chosen" -d ${default_dts} -p ${system_root_node}] set alias_node [add_or_get_dt_node -n "aliases" -d ${default_dts} -p ${system_root_node}] } proc update_chosen {os_handle} { set default_dts [get_property CONFIG.master_dts [get_os]] set system_root_node [add_or_get_dt_node -n "/" -d ${default_dts}] set chosen_node [add_or_get_dt_node -n "chosen" -d ${default_dts} -p ${system_root_node}] #getting boot arguments set bootargs [get_property CONFIG.bootargs $os_handle] set console [hsi::utils::get_os_parameter_value "console"] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[llength $bootargs]} { append bootargs " earlycon" } else { set bootargs "earlycon" } if {[string match -nocase $proctype "psv_cortexa72"]} { #as the early params are defined in board dts files return } if {[string match -nocase $proctype "psx_cortexa78"]} { #as the early params are defined in board dts files return } hsi::utils::add_new_dts_param "${chosen_node}" "bootargs" "$bootargs" string set consoleip [get_property CONFIG.console_device $os_handle] if {![string match -nocase $consoleip "none"]} { set consoleip [ps_node_mapping $consoleip label] set index [string first "," $console] set baud [string range $console [expr $index + 1] [string length $console]] hsi::utils::add_new_dts_param "${chosen_node}" "stdout-path" "serial0:${baud}n8" string } } proc update_cpu_node {os_handle} { set default_dts [get_property CONFIG.master_dts [get_os]] set system_root_node [add_or_get_dt_node -n "/" -d ${default_dts}] set avail_cpu_cores 0 set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psv_cortexa72"] } { set current_proc "psv_cortexa72_" set total_cores 2 } elseif {[string match -nocase $proctype "psx_cortexa78"] } { set current_proc "psx_cortexa78_" set total_cores 16 } elseif {[string match -nocase $proctype "psu_cortexa53"] } { set current_proc "psu_cortexa53_" set total_cores 4 set avail_cpu_cores [llength [get_cells -hier -filter {IP_NAME == "psu_cortexa53"}]] } elseif {[string match -nocase $proctype "ps7_cortexa9"] } { set current_proc "ps7_cortexa9_" set total_cores 2 } else { set current_proc "" } if {[string compare -nocase $current_proc ""] == 0} { return } if {[string match -nocase $proctype "psv_cortexa72"]} { set procs [get_cells -hier -filter {IP_TYPE==PROCESSOR}] set pnames "" foreach proc_name $procs { if {[regexp "psv_cortexa72*" $proc_name match]} { append pnames " " $proc_name } } set a72cores [llength $pnames] if {[string match -nocase $a72cores $total_cores]} { return } } if {[string match -nocase $proctype "psx_cortexa78"]} { set procs [get_cells -hier -filter {IP_TYPE==PROCESSOR}] set pnames "" foreach proc_name $procs { if {[regexp "psx_cortexa78*" $proc_name match]} { append pnames " " $proc_name } } set a78cores [llength $pnames] if {[string match -nocase $a78cores $total_cores]} { return } } for {set i 0} {$i < $total_cores} {incr i} { set proc_name [lindex [get_cells -hier -filter {IP_TYPE==PROCESSOR} *$proctype*] $i] if {[llength $proc_name] == 0} { set cpu_node [add_or_get_dt_node -n "cpus" -d ${default_dts} -p ${system_root_node}] hsi::utils::add_new_dts_param "${cpu_node}" "/delete-node/ cpu@$i" "" boolean continue } if {[string match -nocase [get_property IP_NAME [get_cells -hier $proc_name]] "microblaze"]} { return } if {[regexp ".*${current_proc}${i}" $proc_name match]} { continue } else { set cpu_node [add_or_get_dt_node -n "cpus" -d ${default_dts} -p ${system_root_node}] hsi::utils::add_new_dts_param "${cpu_node}" "/delete-node/ cpu@$i" "" boolean } } # zynqmp.dtsi pmu node has cpu references hense generating them as per design set pmc_prop_value "" if { $avail_cpu_cores < $total_cores } { for {set i 0} {$i < $avail_cpu_cores} {incr i} { if { $i > 0 } { append pmc_prop_value ">, <&cpu$i" } else { append pmc_prop_value "&cpu$i" } } } if {[llength $pmc_prop_value]} { set pmu_node [add_or_get_dt_node -n "pmu" -d ${default_dts} -p ${system_root_node}] hsi::utils::add_new_dts_param "${pmu_node}" "interrupt-affinity" "$pmc_prop_value" intlist } } proc update_alias {os_handle} { set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4" if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } { return } set no_alias [get_property CONFIG.no_alias [get_os]] if {$no_alias} { #Don't generate the alias node when no_alias is set to true return } set default_dts [get_property CONFIG.master_dts [get_os]] set system_root_node [add_or_get_dt_node -n "/" -d ${default_dts}] set all_labels [get_all_dt_labels] set all_drivers [get_drivers] # Search for ps_qspi, if it is there then interchange this with first driver # because to have correct internal u-boot commands qspi has to be listed in aliases as the first for spi0 set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "ps7_cortexa9"]} { set pos [lsearch $all_drivers "ps7_qspi*"] } elseif {[string match -nocase $proctype "psu_cortexa53"]} { set pos [lsearch $all_drivers "psu_qspi*"] } elseif {[string match -nocase $proctype "psv_cortexa72"]} { set pos [lsearch $all_drivers "psv_pmc_qspi*"] } elseif {[string match -nocase $proctype "psx_cortexa78"]} { set pos [lsearch $all_drivers "psx_pmc_qspi*"] } else { set pos [lsearch $all_drivers "psu_qspi*"] } if { $pos >= 0 } { set first_element [lindex $all_drivers 0] set qspi_element [lindex $all_drivers $pos] set all_drivers [lreplace $all_drivers 0 0 $qspi_element] set all_drivers [lreplace $all_drivers $pos $pos $first_element] } # Update all_drivers list such that console device should be the first # uart device in the list. set console_ip [get_property CONFIG.console_device [get_os]] if {![string match -nocase $console_ip "none"]} { set valid_console [lsearch $all_drivers $console_ip] if { $valid_console < 0 } { error "Trying to assign a console::$console_ip which doesn't exists !!!" } } set dt_overlay [get_property CONFIG.DT_Overlay [get_os]] set remove_pl [get_property CONFIG.remove_pl [get_os]] foreach drv_handle $all_drivers { if {[is_pl_ip $drv_handle] && $remove_pl} { continue } set alias_str [get_property CONFIG.dtg.alias $drv_handle] if {[string match -nocase $alias_str "serial"]} { if {![string match -nocase $console_ip "none"]} { if {[string match $console_ip $drv_handle] == 0} { # break the loop After swaping console device and uart device # found in list set consoleip_pos [lsearch $all_drivers $console_ip] set first_occur_pos [lsearch $all_drivers $drv_handle] set console_element [lindex $all_drivers $consoleip_pos] set uart_element [lindex $all_drivers $first_occur_pos] set all_drivers [lreplace $all_drivers $consoleip_pos $consoleip_pos $uart_element] set all_drivers [lreplace $all_drivers $first_occur_pos $first_occur_pos $console_element] break } else { # if the first uart device in the list is console device break } } } } set psi2clist "" set pli2clist "" set i2clen "" set alias_node "" set psuartlist "" set pluartlist "" set uartlen "" set psspilist "" set plspilist "" set spilen "" foreach drv_handle $all_drivers { if {[is_pl_ip $drv_handle] && $dt_overlay} { continue } if {[is_pl_ip $drv_handle] && $remove_pl} { continue } if {[check_ip_trustzone_state $drv_handle] == 1} { continue } set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]] if {[string match -nocase $ip_name "psv_pmc_qspi"]} { set ip_type [get_property IP_TYPE [get_cells -hier $drv_handle]] if {[string match -nocase $ip_type "PERIPHERAL"]} { continue } } set tmp [list_property $drv_handle CONFIG.dtg.alias] if {[string_is_empty $tmp]} { continue } else { set alias_str [get_property CONFIG.dtg.alias $drv_handle] if {[string match -nocase $alias_str "i2c"]} { set upate [lappend upate $drv_handle] set i2clen [llength $upate] set i2cps [is_ps_ip $drv_handle] if {$i2cps} { set psi2clist [lappend psi2clist $drv_handle] } set i2cpl [is_pl_ip $drv_handle] if {$i2cpl} { set pli2clist [lappend pli2clist $drv_handle] } } if {[string match -nocase $alias_str "serial"]} { set uartate [lappend uartate $drv_handle] set uartlen [llength $uartate] set uartps [is_ps_ip $drv_handle] if {$uartps} { set psuartlist [lappend psuartlist $drv_handle] } set uartpl [is_pl_ip $drv_handle] if {$uartpl} { set pluartlist [lappend pluartlist $drv_handle] } } if {[string match -nocase $alias_str "spi"]} { set spiat [lappend spiat $drv_handle] set spilen [llength $spiat] set spips [is_ps_ip $drv_handle] if {$spips} { set psspilist [lappend psspilist $drv_handle] } set spipl [is_pl_ip $drv_handle] if {$spipl} { set plspilist [lappend plspilist $drv_handle] } } set alias_count [get_os_dev_count alias_${alias_str}_count] set conf_name ${alias_str}${alias_count} set value [ps_node_mapping $drv_handle label] # When coresight dcc is enabled then set the serial0=dcc in aliases node if {[regexp ".*coresight.*" $value match]} { set value "dcc" } set ip_list "i2c spi serial" # TODO: need to check if the label already exists in the current system if {[lsearch $all_labels $conf_name] >=0} { set str [lsearch $ip_list $alias_str] if {[string match $str "-1"]} { continue } } set dtg_alias_only [get_property CONFIG.dtg_alias [get_os]] set alias_node [add_or_get_dt_node -n "aliases" -d ${default_dts} -p ${system_root_node}] if {$dtg_alias_only} { # if dtg_alias set to true then we are deleting the board.dtsi aliases hsi::utils::add_new_dts_param ${system_root_node} "/delete-node/ aliases" "" boolean } hsi::utils::add_new_dts_param "${alias_node}" ${conf_name} ${value} aliasref hsi::utils::set_os_parameter_value alias_${alias_str}_count [expr $alias_count + 1] } } set i2c_pslen [llength $psi2clist] for {set i 0} {$i < $i2c_pslen} {incr i} { set drv_name [lindex $psi2clist $i] set value [ps_node_mapping $drv_name label] set name "i2c$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } set i2c_pllen [llength $pli2clist] set i2clen1 [expr {$i2c_pslen + $i2c_pllen}] for {set i $i2c_pslen} {$i < $i2clen1} {incr i} { set drv_name [lindex $pli2clist [expr {$i - $i2c_pslen}]] set value [ps_node_mapping $drv_name label] set name "i2c$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } set is_pl_console [is_pl_ip $console_ip] if {$is_pl_console} { for {set i 0} {$i < $uartlen} {incr i} { set drv_name [lindex $uartate $i] set value [ps_node_mapping $drv_name label] # When coresight dcc is enabled then set the serial0=dcc in aliases node if {[regexp ".*coresight.*" $value match]} { set value "dcc" } set name "serial$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } } else { set uart_pslen [llength $psuartlist] for {set i 0} {$i < $uart_pslen} {incr i} { set drv_name [lindex $psuartlist $i] set value [ps_node_mapping $drv_name label] # When coresight dcc is enabled then set the serial0=dcc in aliases node if {[regexp ".*coresight.*" $value match]} { set value "dcc" } set name "serial$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } set uart_pllen [llength $pluartlist] set uartlen1 [expr {$uart_pslen + $uart_pllen}] for {set i $uart_pslen} {$i < $uartlen1} {incr i} { set drv_name [lindex $pluartlist [expr {$i - $uart_pslen}]] set value [ps_node_mapping $drv_name label] # When coresight dcc is enabled then set the serial0=dcc in aliases node if {[regexp ".*coresight.*" $value match]} { set value "dcc" } set name "serial$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } } set spi_pslen [llength $psspilist] for {set i 0} {$i < $spi_pslen} {incr i} { set drv_name [lindex $psspilist $i] set value [ps_node_mapping $drv_name label] set name "spi$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } set spi_pllen [llength $plspilist] set spilen1 [expr {$spi_pslen + $spi_pllen}] for {set i $spi_pslen} {$i < $spilen1} {incr i} { set drv_name [lindex $plspilist [expr {$i - $spi_pslen}]] set value [ps_node_mapping $drv_name label] set name "spi$i" hsi::utils::add_new_dts_param "${alias_node}" ${name} ${value} aliasref } } # remove main memory node proc remove_main_memory_node {} { set main_memory [get_property CONFIG.main_memory [get_os]] if {[string_is_empty $main_memory]} { return 0 } # in theory it will not del the ps ddr as it snot been generated set mc_obj [get_node_object $main_memory "" ""] if {[string_is_empty $mc_obj]} { return 0 } set all_drivers [get_drivers] foreach drv_handle $all_drivers { set ip [get_property IP_NAME [get_cells -hier $drv_handle]] if {[string match -nocase $ip "ddr4"]} { set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] if {[llength $ip_mem_handles] > 1} { return } } } set cur_dts [current_dt_tree] foreach dts_file [get_dt_tree] { set dts_nodes [get_all_tree_nodes $dts_file] foreach node ${dts_nodes} { if {[regexp $mc_obj $node match]} { current_dt_tree $dts_file delete_objs $mc_obj current_dt_tree $cur_dts } } } } ================================================ FILE: device_tree/data/kernel_dtsi/2014.4/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-1.0"; reg = <0xf8006000 0x1000>; xlnx,has-ecc = <0x0>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x1000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "xlnx,ps7-ethernet-1.00.a"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 13>, <&clkc 30>; clock-names = "ref_clk", "aper_clk"; local-mac-address = [00 0a 35 00 00 00]; xlnx,has-mdio = <0x1>; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,ps7-ethernet-1.00.a"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 14>, <&clkc 31>; clock-names = "ref_clk", "aper_clk"; local-mac-address = [00 0a 35 00 00 00]; xlnx,has-mdio = <0x1>; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; ps-clk-frequency = <33333333>; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "xlnx,zynq-wdt-r1p2"; device_type = "watchdog"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; reset = <0>; timeout-sec = <10>; }; usb0: usb@e0002000 { clocks = <&clkc 28>; compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; }; usb1: usb@e0003000 { clocks = <&clkc 29>; compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; xlnx,has-ecc = <0x0>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x1000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "xlnx,ps7-ethernet-1.00.a"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 13>, <&clkc 30>; clock-names = "ref_clk", "aper_clk"; local-mac-address = [00 0a 35 00 00 00]; xlnx,has-mdio = <0x1>; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,ps7-ethernet-1.00.a"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 14>, <&clkc 31>; clock-names = "ref_clk", "aper_clk"; local-mac-address = [00 0a 35 00 00 00]; xlnx,has-mdio = <0x1>; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; ps-clk-frequency = <33333333>; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; usb0: usb@e0002000 { clocks = <&clkc 28>; compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; }; usb1: usb@e0003000 { clocks = <&clkc 29>; compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.3/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; syscon = <&slcr>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.4/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; syscon = <&slcr>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; }; cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; }; cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; }; cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf01>, <1 14 0xf01>, <1 11 0xf01>, <1 10 0xf01>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf902f000 0x0 0x2000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf906f000 0x0 0x2000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; xlnx,id = <0>; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; xlnx,id = <1>; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; xlnx,id = <2>; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; xlnx,id = <3>; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; xlnx,id = <4>; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; xlnx,id = <5>; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; xlnx,id = <6>; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; xlnx,id = <7>; xlnx,bus-width = <128>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; }; /* ADMA */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,id = <0>; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,id = <1>; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,id = <2>; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,id = <3>; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,id = <4>; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,id = <5>; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,id = <6>; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,id = <7>; xlnx,bus-width = <64>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; jumbo-max-len = <10240>; jumbo-supported; }; gem1: ethernet@ff0c0000 { compatible = "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; jumbo-max-len = <10240>; jumbo-supported; }; gem2: ethernet@ff0d0000 { compatible = "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; jumbo-max-len = <10240>; jumbo-supported; }; gem3: ethernet@ff0e0000 { compatible = "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; jumbo-max-len = <10240>; jumbo-supported; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; interrupt-parent = <&gic>; interrupts = < 0 118 4>, < 0 116 4>, < 0 115 4>, /* MSI_1 [63...32] */ < 0 114 4 >; /* MSI_0 [31...0] */ interrupt-names = "misc", "intx", "msi_1", "msi_0"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x0 0xe0000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; }; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma"; }; plane1 { dmas = <&xlnx_dpdma 0>; dma-names = "dma"; }; }; }; xlnx_dp: dp@43c00000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@43c0a000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; dma-video0channel@43c10000 { compatible = "xlnx,video0"; }; dma-video1channel@43c10000 { compatible = "xlnx,video1"; }; dma-video2channel@43c10000 { compatible = "xlnx,video2"; }; dma-graphicschannel@43c10000 { compatible = "xlnx,graphics"; }; dma-audio0channel@43c10000 { compatible = "xlnx,audio0"; }; dma-audio1channel@43c10000 { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; syscon = <&slcr>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; }; cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; }; cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; }; cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; }; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { /* fixme: what to attach to */ #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_ddr: pd-ddr { #power-domain-cells = <0x0>; pd-id = <0x37>; }; pd_apll: pd-apll { #power-domain-cells = <0x0>; pd-id = <0x32>; }; pd_vpll: pd-vpll { #power-domain-cells = <0x0>; pd-id = <0x33>; }; pd_dpll: pd-dpll { #power-domain-cells = <0x0>; pd-id = <0x34>; }; pd_rpll: pd-rpll { #power-domain-cells = <0x0>; pd-id = <0x35>; }; pd_iopll: pd-iopll { #power-domain-cells = <0x0>; pd-id = <0x36>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf01>, <1 14 0xf01>, <1 11 0xf01>, <1 10 0xf01>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf902f000 0x0 0x2000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf906f000 0x0 0x2000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <1>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <2>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <3>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <4>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <5>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <6>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <7>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; }; /* ADMA */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,id = <0>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,id = <1>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,id = <2>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,id = <3>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,id = <4>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,id = <5>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,id = <6>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,id = <7>; xlnx,bus-width = <64>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "intx", "msi_1", "msi_0"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x0 0xe0000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; mmu-masters = < &gem0 0x874 &gem1 0x875 &gem2 0x876 &gem3 0x877 >; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb@fe200000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb0>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; usb1: usb@fe300000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; power-domains = <&pd_usb1>; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma"; }; plane1 { dmas = <&xlnx_dpdma 0>; dma-names = "dma"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd400000 0x0 0x20000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; syscon = <&slcr>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; }; cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; }; cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; }; cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; }; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { /* fixme: what to attach to */ #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_ddr: pd-ddr { #power-domain-cells = <0x0>; pd-id = <0x37>; }; pd_apll: pd-apll { #power-domain-cells = <0x0>; pd-id = <0x32>; }; pd_vpll: pd-vpll { #power-domain-cells = <0x0>; pd-id = <0x33>; }; pd_dpll: pd-dpll { #power-domain-cells = <0x0>; pd-id = <0x34>; }; pd_rpll: pd-rpll { #power-domain-cells = <0x0>; pd-id = <0x35>; }; pd_iopll: pd-iopll { #power-domain-cells = <0x0>; pd-id = <0x36>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf01>, <1 14 0xf01>, <1 11 0xf01>, <1 10 0xf01>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <1>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <2>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <3>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <4>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <5>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <6>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,id = <7>; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; }; /* ADMA */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,id = <0>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,id = <1>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,id = <2>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,id = <3>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,id = <4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,id = <5>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,id = <6>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,id = <7>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff0a0000 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "intx", "msi_1", "msi_0"; reg = <0x0 0xfd0e0000 0x1000>, <0x0 0xfd480000 0x1000>, <0x0 0xe0000000 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x1000>, <0x0 0xc0000000 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>, <0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>; reg-names = "serdes", "siou", "fpd", "lpd"; xlnx,tx_termination_fix; lan0: lane@0 { #phy-cells = <4>; }; lan1: lane@1 { #phy-cells = <4>; }; lan2: lane@2 { #phy-cells = <4>; }; lan3: lane@3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x1000>; clock-names = "clk_xin", "clk_ahb"; broken-tuning; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x20000>; #iommu-cells = <1>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; mmu-masters = < &gem0 0x874 &gem1 0x875 &gem2 0x876 &gem3 0x877 &usb0 0x860 &usb1 0x861 &qspi 0x873 &lpd_dma_chan1 0x868 &lpd_dma_chan2 0x869 &lpd_dma_chan3 0x86a &lpd_dma_chan4 0x86b &lpd_dma_chan5 0x86c &lpd_dma_chan6 0x86d &lpd_dma_chan7 0x86e &lpd_dma_chan8 0x86f &fpd_dma_chan1 0x14e8 &fpd_dma_chan2 0x14e9 &fpd_dma_chan3 0x14ea &fpd_dma_chan4 0x14eb &fpd_dma_chan5 0x14ec &fpd_dma_chan6 0x14ed &fpd_dma_chan7 0x14ee &fpd_dma_chan8 0x14ef &sdhci0 0x870 &sdhci1 0x871 &nand0 0x872>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb@fe200000 { #address-cells = <2>; #size-cells = <1>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; usb1: usb@fe300000 { #address-cells = <2>; #size-cells = <1>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x1000>; timeout-sec = <10>; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma"; }; plane1 { dmas = <&xlnx_dpdma 0>; dma-names = "dma"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.3/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; #interrupt-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; broken-adma2; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; broken-adma2; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; }; cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; }; cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; }; cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; }; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { /* fixme: what to attach to */ #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf01>, <1 14 0xf01>, <1 11 0xf01>, <1 10 0xf01>; }; edac { compatible = "arm,cortex-a53-edac"; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; power-domains = <&pd_gpu>; }; /* ADMA */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "fpd", "lpd"; xlnx,tx_termination_fix; lane0: lane@0 { #phy-cells = <4>; }; lane1: lane@1 { #phy-cells = <4>; }; lane2: lane@2 { #phy-cells = <4>; }; lane3: lane@3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; mmu-masters = < &gem0 0x874 &gem1 0x875 &gem2 0x876 &gem3 0x877 &usb0 0x860 &usb1 0x861 &qspi 0x873 &lpd_dma_chan1 0x868 &lpd_dma_chan2 0x869 &lpd_dma_chan3 0x86a &lpd_dma_chan4 0x86b &lpd_dma_chan5 0x86c &lpd_dma_chan6 0x86d &lpd_dma_chan7 0x86e &lpd_dma_chan8 0x86f &fpd_dma_chan1 0x14e8 &fpd_dma_chan2 0x14e9 &fpd_dma_chan3 0x14ea &fpd_dma_chan4 0x14eb &fpd_dma_chan5 0x14ec &fpd_dma_chan6 0x14ed &fpd_dma_chan7 0x14ee &fpd_dma_chan8 0x14ef &sdhci0 0x870 &sdhci1 0x871 &nand0 0x872>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb@fe200000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; usb1: usb@fe300000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.4/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ /include/ "skeleton.dtsi" / { compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; pmu { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; broken-adma2; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; broken-adma2; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-mehod = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <800000>; }; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { /* fixme: what to attach to */ #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf01>, <1 14 0xf01>, <1 11 0xf01>, <1 10 0xf01>; }; edac { compatible = "arm,cortex-a53-edac"; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <2>; #size-cells = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xfd1a0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "fpd", "lpd"; xlnx,tx_termination_fix; lane0: lane@0 { #phy-cells = <4>; }; lane1: lane@1 { #phy-cells = <4>; }; lane2: lane@2 { #phy-cells = <4>; }; lane3: lane@3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; mmu-masters = < &gem0 0x874 &gem1 0x875 &gem2 0x876 &gem3 0x877 &usb0 0x860 &usb1 0x861 &qspi 0x873 &lpd_dma_chan1 0x868 &lpd_dma_chan2 0x869 &lpd_dma_chan3 0x86a &lpd_dma_chan4 0x86b &lpd_dma_chan5 0x86c &lpd_dma_chan6 0x86d &lpd_dma_chan7 0x86e &lpd_dma_chan8 0x86f &fpd_dma_chan1 0x14e8 &fpd_dma_chan2 0x14e9 &fpd_dma_chan3 0x14ea &fpd_dma_chan4 0x14eb &fpd_dma_chan5 0x14ec &fpd_dma_chan6 0x14ed &fpd_dma_chan7 0x14ee &fpd_dma_chan8 0x14ef &sdhci0 0x870 &sdhci1 0x871 &nand0 0x872>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb@fe200000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; usb1: usb@fe300000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125>, <&clk125>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>; /* snps,quirk-frame-length-adjustment = <0x20>; */ snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; dma-channels = <6>; #dma-cells = <1>; dma-video0channel@fd4c0000 { compatible = "xlnx,video0"; }; dma-video1channel@fd4c0000 { compatible = "xlnx,video1"; }; dma-video2channel@fd4c0000 { compatible = "xlnx,video2"; }; dma-graphicschannel@fd4c0000 { compatible = "xlnx,graphics"; }; dma-audio0channel@fd4c0000 { compatible = "xlnx,audio0"; }; dma-audio1channel@fd4c0000 { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Signed-off-by: Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* i * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom@55 { compatible = "at,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &xlnx_dp_sub { xlnx,vid-clk-pl; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_0_cd_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_0_wp_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@00000000 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: spi1_flash0@0 { compatible = "mtd_dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; spi1_flash0@00000000 { label = "spi1_flash0"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_0_ce_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_0_ce_grp"; bias-pull-up; }; mux-rb { groups = "nand0_0_rb_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_0_rb_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_0_dqs_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_0_dqs_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zcu106.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; /* FIXME */ }; }; /* 6 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; broken-adma2; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; broken-adma2; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clkc: clkc { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clkc"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; clock-output-names = "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus", "gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref", "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clkc 63>, <&clkc 31>; }; &can1 { clocks = <&clkc 64>, <&clkc 31>; }; &cpu0 { clocks = <&clkc 10>; }; &fpd_dma_chan1 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan2 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan3 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan4 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan5 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan6 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan7 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan8 { clocks = <&clkc 19>, <&clkc 31>; }; &gpu { clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; }; &lpd_dma_chan1 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan2 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan3 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan4 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan5 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan6 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan7 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan8 { clocks = <&clkc 68>, <&clkc 31>; }; &nand0 { clocks = <&clkc 60>, <&clkc 31>; }; &gem0 { clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem1 { clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem2 { clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem3 { clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; }; &gpio { clocks = <&clkc 31>; }; &i2c0 { clocks = <&clkc 61>; }; &i2c1 { clocks = <&clkc 62>; }; &pcie { clocks = <&clkc 23>; }; &qspi { clocks = <&clkc 53>, <&clkc 31>; }; &sata { clocks = <&clkc 22>; }; &sdhci0 { clocks = <&clkc 54>, <&clkc 31>; }; &sdhci1 { clocks = <&clkc 55>, <&clkc 31>; }; &spi0 { clocks = <&clkc 58>, <&clkc 31>; }; &spi1 { clocks = <&clkc 59>, <&clkc 31>; }; &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; &uart1 { clocks = <&clkc 57>, <&clkc 31>; }; &usb0 { clocks = <&clkc 32>, <&clkc 34>; }; &usb1 { clocks = <&clkc 33>, <&clkc 34>; }; &watchdog0 { clocks = <&clkc 75>; }; &xilinx_ams { clocks = <&clkc 70>; }; &xilinx_drm { clocks = <&clkc 16>; }; &xlnx_dp { clocks = <&dp_aclk>, <&clkc 17>; }; &xlnx_dpdma { clocks = <&clkc 20>; }; &xlnx_dp_snd_codec0 { clocks = <&clkc 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <100000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmufw: firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,pinctrl-zynqmp"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; }; }; usb1: usb1 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom@55 { compatible = "at,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &xlnx_dp_sub { xlnx,vid-clk-pl; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_0_cd_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_0_wp_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@00000000 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: spi1_flash0@0 { compatible = "mtd_dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; spi1_flash0@00000000 { label = "spi1_flash0"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_0_ce_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_0_ce_grp"; bias-pull-up; }; mux-rb { groups = "nand0_0_rb_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_0_rb_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_0_dqs_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_0_dqs_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; kim { /* Bluetooth driver for connection */ compatible = "kim"; status = "okay"; /* * FIXME: The following is complete CRAP since * the vendor driver doesn't follow the gpio * binding. Passing in a magic Linux gpio number * here until we fix the vendor driver. */ /* FIXME BT_EN*/ /* nshutdown_gpio = <&gpio 8 0>; */ nshutdown_gpio = <346>; /* 338 base + MIO8 */ dev_name = "/dev/ttyPS1"; /* MIO2/3 */ flow_cntrl = <1>; baud_rate = <3000000>; }; /* * CONFIG_BT_WILINK - depends on * btwilink: add minimal device tree support * commit b3ef820a9310743d62cf50341f529ca17319dd77 */ btwilink { /* Bluetooth driver itself */ status = "okay"; compatible = "btwilink"; }; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_4bit_0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_4bit_0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_0_cd_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_4bit_0_1_grp"; function = "sdio1"; }; conf { groups = "sdio1_4bit_0_1_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_3_ss0_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_3_ss0_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_0_ss0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_0_ss0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &sdhci1 { bus-width = <0x4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; }; &spi1 { /* High Speed connector */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; /* for 1.0 silicon */ }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zcu106.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; /* FIXME */ }; }; /* 6 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; broken-adma2; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; broken-adma2; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clkc: clkc { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clkc"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; clock-output-names = "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus", "gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref", "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clkc 63>, <&clkc 31>; }; &can1 { clocks = <&clkc 64>, <&clkc 31>; }; &cpu0 { clocks = <&clkc 10>; }; &fpd_dma_chan1 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan2 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan3 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan4 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan5 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan6 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan7 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan8 { clocks = <&clkc 19>, <&clkc 31>; }; &gpu { clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; }; &lpd_dma_chan1 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan2 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan3 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan4 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan5 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan6 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan7 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan8 { clocks = <&clkc 68>, <&clkc 31>; }; &nand0 { clocks = <&clkc 60>, <&clkc 31>; }; &gem0 { clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem1 { clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem2 { clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem3 { clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; }; &gpio { clocks = <&clkc 31>; }; &i2c0 { clocks = <&clkc 61>; }; &i2c1 { clocks = <&clkc 62>; }; &pcie { clocks = <&clkc 23>; }; &qspi { clocks = <&clkc 53>, <&clkc 31>; }; &sata { clocks = <&clkc 22>; }; &sdhci0 { clocks = <&clkc 54>, <&clkc 31>; }; &sdhci1 { clocks = <&clkc 55>, <&clkc 31>; }; &spi0 { clocks = <&clkc 58>, <&clkc 31>; }; &spi1 { clocks = <&clkc 59>, <&clkc 31>; }; &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; &uart1 { clocks = <&clkc 57>, <&clkc 31>; }; &usb0 { clocks = <&clkc 32>, <&clkc 34>; }; &usb1 { clocks = <&clkc 33>, <&clkc 34>; }; &watchdog0 { clocks = <&clkc 75>; }; &xilinx_ams { clocks = <&clkc 70>; }; &xilinx_drm { clocks = <&clkc 16>; }; &xlnx_dp { clocks = <&dp_aclk>, <&clkc 17>; }; &xlnx_dpdma { clocks = <&clkc 20>; }; &xlnx_dp_snd_codec0 { clocks = <&clkc 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <100000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmufw: firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,pinctrl-zynqmp"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; #stream-id-cells = <1>; iommus = <&smmu 0x860>; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; }; }; usb1: usb1 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; #stream-id-cells = <1>; iommus = <&smmu 0x861>; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom@55 { compatible = "at,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &xlnx_dp_sub { xlnx,vid-clk-pl; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_0_cd_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_0_wp_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@0 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: spi1_flash0@0 { compatible = "mtd_dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; spi1_flash0@0 { label = "spi1_flash0"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_0_ce_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_0_ce_grp"; bias-pull-up; }; mux-rb { groups = "nand0_0_rb_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_0_rb_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_0_dqs_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_0_dqs_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board_sn@0 { reg = <0x0 0x14>; }; eth_mac: eth_mac@20 { reg = <0x20 0x6>; }; board_name: board_name@d0 { reg = <0xd0 0x6>; }; board_revision: board_revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME Npt detected */ tca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; /* fpd_dma clk 667MHz, lpd_dma 500MHz */ &fpd_dma_chan1 { xlnx,include-sg; /* for testing purpose */ xlnx,overfetch; /* for testing purpose */ xlnx,ratectrl = <0>; /* for testing purpose */ xlnx,src-issue = <31>; }; &fpd_dma_chan2 { xlnx,ratectrl = <100>; /* for testing purpose */ xlnx,src-issue = <4>; /* for testing purpose */ }; &fpd_dma_chan4 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan6 { xlnx,include-sg; /* for testing purpose */ }; &fpd_dma_chan8 { xlnx,include-sg; /* for testing purpose */ }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; /* FIXME */ }; }; /* 6 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; broken-adma2; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; broken-adma2; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clkc: clkc { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clkc"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; clock-output-names = "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus", "gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref", "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clkc 63>, <&clkc 31>; }; &can1 { clocks = <&clkc 64>, <&clkc 31>; }; &cpu0 { clocks = <&clkc 10>; }; &fpd_dma_chan1 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan2 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan3 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan4 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan5 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan6 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan7 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan8 { clocks = <&clkc 19>, <&clkc 31>; }; &gpu { clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; }; &lpd_dma_chan1 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan2 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan3 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan4 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan5 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan6 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan7 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan8 { clocks = <&clkc 68>, <&clkc 31>; }; &nand0 { clocks = <&clkc 60>, <&clkc 31>; }; &gem0 { clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem1 { clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem2 { clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem3 { clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; }; &gpio { clocks = <&clkc 31>; }; &i2c0 { clocks = <&clkc 61>; }; &i2c1 { clocks = <&clkc 62>; }; &pcie { clocks = <&clkc 23>; }; &qspi { clocks = <&clkc 53>, <&clkc 31>; }; &sata { clocks = <&clkc 22>; }; &sdhci0 { clocks = <&clkc 54>, <&clkc 31>; }; &sdhci1 { clocks = <&clkc 55>, <&clkc 31>; }; &spi0 { clocks = <&clkc 58>, <&clkc 31>; }; &spi1 { clocks = <&clkc 59>, <&clkc 31>; }; &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; &uart1 { clocks = <&clkc 57>, <&clkc 31>; }; &usb0 { clocks = <&clkc 32>, <&clkc 34>; }; &usb1 { clocks = <&clkc 33>, <&clkc 34>; }; &watchdog0 { clocks = <&clkc 75>; }; &xilinx_ams { clocks = <&clkc 70>; }; &xilinx_drm { clocks = <&clkc 16>; }; &xlnx_dp { clocks = <&dp_aclk>, <&clkc 17>; }; &xlnx_dpdma { clocks = <&clkc 20>; }; &xlnx_dp_snd_codec0 { clocks = <&clkc 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmufw: firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,pinctrl-zynqmp"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom@55 { compatible = "at,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &xlnx_dp_sub { xlnx,vid-clk-pl; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_0_cd_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_0_wp_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc2.dtsi ================================================ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@0 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: spi1_flash0@0 { compatible = "mtd_dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; spi1_flash0@0 { label = "spi1_flash0"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_0_ce_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_0_ce_grp"; bias-pull-up; }; mux-rb { groups = "nand0_0_rb_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_0_rb_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_0_dqs_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_0_dqs_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp", "spi0_0_ss2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_3_ss0_grp", "spi1_3_ss1_grp", "spi1_3_ss2_grp"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board_sn@0 { reg = <0x0 0x14>; }; eth_mac: eth_mac@20 { reg = <0x20 0x6>; }; board_name: board_name@d0 { reg = <0xd0 0x6>; }; board_revision: board_revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu104-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME Npt detected */ tca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; /* FIXME */ }; }; /* 6 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_0_cd_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_0_cd_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_0_wp_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_0_wp_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk-ccf.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clkc 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clkc: clkc { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clkc"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; clock-output-names = "iopll", "rpll", "apll", "dpll", "vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace", "dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref", "dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus", "gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref", "usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5", "cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch", "gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref", "uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref", "adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clkc 63>, <&clkc 31>; }; &can1 { clocks = <&clkc 64>, <&clkc 31>; }; &cpu0 { clocks = <&clkc 10>; }; &fpd_dma_chan1 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan2 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan3 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan4 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan5 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan6 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan7 { clocks = <&clkc 19>, <&clkc 31>; }; &fpd_dma_chan8 { clocks = <&clkc 19>, <&clkc 31>; }; &gpu { clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>; }; &lpd_dma_chan1 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan2 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan3 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan4 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan5 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan6 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan7 { clocks = <&clkc 68>, <&clkc 31>; }; &lpd_dma_chan8 { clocks = <&clkc 68>, <&clkc 31>; }; &nand0 { clocks = <&clkc 60>, <&clkc 31>; }; &gem0 { clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem1 { clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem2 { clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>; clock-names = "pclk", "tx_clk", "hclk"; }; &gem3 { clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; }; &gpio { clocks = <&clkc 31>; }; &i2c0 { clocks = <&clkc 61>; }; &i2c1 { clocks = <&clkc 62>; }; &pcie { clocks = <&clkc 23>; }; &qspi { clocks = <&clkc 53>, <&clkc 31>; }; &sata { clocks = <&clkc 22>; }; &sdhci0 { clocks = <&clkc 54>, <&clkc 31>; }; &sdhci1 { clocks = <&clkc 55>, <&clkc 31>; }; &spi0 { clocks = <&clkc 58>, <&clkc 31>; }; &spi1 { clocks = <&clkc 59>, <&clkc 31>; }; &uart0 { clocks = <&clkc 56>, <&clkc 31>; }; &uart1 { clocks = <&clkc 57>, <&clkc 31>; }; &usb0 { clocks = <&clkc 32>, <&clkc 34>; }; &usb1 { clocks = <&clkc 33>, <&clkc 34>; }; &watchdog0 { clocks = <&clkc 75>; }; &xilinx_ams { clocks = <&clkc 70>; }; &xilinx_drm { clocks = <&clkc 16>; }; &xlnx_dp { clocks = <&dp_aclk>, <&clkc 17>; }; &xlnx_dpdma { clocks = <&clkc 20>; }; &xlnx_dp_snd_codec0 { clocks = <&clkc 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp-clk.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ &amba { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &nand0 { clocks = <&clk100 &clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &qspi { clocks = <&clk300 &clk300>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; &xilinx_drm { clocks = <&drm_clock>; }; &xlnx_dp { clocks = <&dp_aclk>, <&dp_aud_clk>; }; &xlnx_dpdma { clocks = <&dpdma_clk>; }; &xlnx_dp_snd_codec0 { clocks = <&dp_aud_clk>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2017.4/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmufw: firmware { compatible = "xlnx,zynqmp-pm"; method = "smc"; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_dp_snd_card: dp_snd_card { compatible = "xlnx,dp-snd-card"; status = "disabled"; xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; }; xlnx_dp_snd_codec0: dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; status = "disabled"; clock-names = "aud_clk"; }; xlnx_dp_snd_pcm0: dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; xlnx_dp_snd_pcm1: dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; status = "disabled"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; xilinx_drm: xilinx_drm { compatible = "xlnx,drm"; status = "disabled"; xlnx,encoder-slave = <&xlnx_dp>; xlnx,connector-type = "DisplayPort"; xlnx,dp-sub = <&xlnx_dp_sub>; planes { xlnx,pixel-format = "rgb565"; plane0 { dmas = <&xlnx_dpdma 3>; dma-names = "dma0"; }; plane1 { dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; dma-names = "dma0", "dma1", "dma2"; }; }; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc","dummy","intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>, <0x0 0xff5e0000 0x0 0x1000>; reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,pinctrl-zynqmp"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dp: dp@fd4a0000 { compatible = "xlnx,v-dp"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "aclk", "aud_clk"; power-domains = <&pd_dp>; xlnx,dp-version = "v1.2"; xlnx,max-lanes = <2>; xlnx,max-link-rate = <540000>; xlnx,max-bpc = <16>; xlnx,enable-ycrcb; xlnx,colormetry = "rgb"; xlnx,bpc = <8>; xlnx,audio-chan = <2>; xlnx,dp-sub = <&xlnx_dp_sub>; xlnx,max-pclock-frequency = <300000>; }; xlnx_dp_sub: dp_sub@fd4aa000 { compatible = "xlnx,dp-sub"; status = "disabled"; reg = <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "blend", "av_buf", "aud"; xlnx,output-fmt = "rgb"; xlnx,vid-fmt = "yuyv"; xlnx,gfx-fmt = "rgb565"; power-domains = <&pd_dp>; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1232-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1254-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevB"; compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom@55 { compatible = "at,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@0 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: spi1_flash0@0 { compatible = "mtd_dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; spi1_flash0@0 { label = "spi1_flash0"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu100-revc.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2cswitch@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 0>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board_sn@0 { reg = <0x0 0x14>; }; eth_mac: eth_mac@20 { reg = <0x20 0x6>; }; board_name: board_name@d0 { reg = <0xd0 0x6>; }; board_revision: board_revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME Npt detected */ tca6416_u97: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu104-revc.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: 8t49n287@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2cswitch@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2cswitch@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; /* FIXME */ }; }; /* 6 - 7 unconnected */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zcu111-reva.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2cswitch@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; i2cswitch@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { /* i2c mw 74 0 11 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2cswitch@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/zynq/zynq-7000.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clk: clk { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clk 63>, <&clk 31>; }; &can1 { clocks = <&clk 64>, <&clk 31>; }; &cpu0 { clocks = <&clk 10>; }; &fpd_dma_chan1 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan2 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan3 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan4 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan5 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan6 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan7 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan8 { clocks = <&clk 19>, <&clk 31>; }; &gpu { clocks = <&clk 24>, <&clk 25>, <&clk 26>; }; &lpd_dma_chan1 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan2 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan3 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan4 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan5 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan6 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan7 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan8 { clocks = <&clk 68>, <&clk 31>; }; &nand0 { clocks = <&clk 60>, <&clk 31>; }; &gem0 { clocks = <&clk 31>, <&clk 49>, <&clk 45>, <&clk 49>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&clk 31>, <&clk 50>, <&clk 46>, <&clk 50>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&clk 31>, <&clk 51>, <&clk 47>, <&clk 51>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&clk 31>, <&clk 52>, <&clk 48>, <&clk 52>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&clk 31>; }; &i2c0 { clocks = <&clk 61>; }; &i2c1 { clocks = <&clk 62>; }; &perf_monitor_ocm { clocks = <&clk 31>; }; &pcie { clocks = <&clk 23>; }; &qspi { clocks = <&clk 53>, <&clk 31>; }; &sata { clocks = <&clk 22>; }; &sdhci0 { clocks = <&clk 54>, <&clk 31>; }; &sdhci1 { clocks = <&clk 55>, <&clk 31>; }; &spi0 { clocks = <&clk 58>, <&clk 31>; }; &spi1 { clocks = <&clk 59>, <&clk 31>; }; &uart0 { clocks = <&clk 56>, <&clk 31>; }; &uart1 { clocks = <&clk 57>, <&clk 31>; }; &usb0 { clocks = <&clk 32>, <&clk 34>; }; &usb1 { clocks = <&clk 33>, <&clk 34>; }; &watchdog0 { clocks = <&clk 75>; }; &xilinx_ams { clocks = <&clk 70>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&clk 17>, <&clk 16>; }; &xlnx_dpdma { clocks = <&clk 20>; }; &zynqmp_dp_snd_codec0 { clocks = <&clk 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.1/zynqmp/zynqmp.dtsi ================================================ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * SPDX-License-Identifier: GPL-2.0+ */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; /* PMU1<->APU IPI mailbox controller */ ipi_mailbox_pmu1: mailbox@ff990400 { compatible = "xlnx,zynqmp-ipi-mailbox"; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-ids = <0 4>; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; }; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <4>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&pd_dp>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevB"; compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; &qspi { flash@0 { compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash0@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash0@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 0>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { reg = <0x19>; }; dev@30 { reg = <0x30>; }; dev@35 { reg = <0x35>; }; dev@36 { reg = <0x36>; }; dev@51 { reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clk: clk { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clk 63>, <&clk 31>; }; &can1 { clocks = <&clk 64>, <&clk 31>; }; &cpu0 { clocks = <&clk 10>; }; &fpd_dma_chan1 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan2 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan3 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan4 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan5 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan6 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan7 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan8 { clocks = <&clk 19>, <&clk 31>; }; &gpu { clocks = <&clk 24>, <&clk 25>, <&clk 26>; }; &lpd_dma_chan1 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan2 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan3 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan4 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan5 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan6 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan7 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan8 { clocks = <&clk 68>, <&clk 31>; }; &nand0 { clocks = <&clk 60>, <&clk 31>; }; &gem0 { clocks = <&clk 31>, <&clk 49>, <&clk 45>, <&clk 49>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&clk 31>, <&clk 50>, <&clk 46>, <&clk 50>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&clk 31>, <&clk 51>, <&clk 47>, <&clk 51>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&clk 31>, <&clk 52>, <&clk 48>, <&clk 52>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&clk 31>; }; &i2c0 { clocks = <&clk 61>; }; &i2c1 { clocks = <&clk 62>; }; &perf_monitor_ocm { clocks = <&clk 31>; }; &pcie { clocks = <&clk 23>; }; &qspi { clocks = <&clk 53>, <&clk 31>; }; &sata { clocks = <&clk 22>; }; &sdhci0 { clocks = <&clk 54>, <&clk 31>; }; &sdhci1 { clocks = <&clk 55>, <&clk 31>; }; &spi0 { clocks = <&clk 58>, <&clk 31>; }; &spi1 { clocks = <&clk 59>, <&clk 31>; }; &ttc0 { clocks = <&clk 31>; }; &ttc1 { clocks = <&clk 31>; }; &ttc2 { clocks = <&clk 31>; }; &ttc3 { clocks = <&clk 31>; }; &uart0 { clocks = <&clk 56>, <&clk 31>; }; &uart1 { clocks = <&clk 57>, <&clk 31>; }; &usb0 { clocks = <&clk 32>, <&clk 34>; }; &usb1 { clocks = <&clk 33>, <&clk 34>; }; &watchdog0 { clocks = <&clk 75>; }; &xilinx_ams { clocks = <&clk 70>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&clk 17>, <&clk 16>; }; &xlnx_dpdma { clocks = <&clk 20>; }; &zynqmp_dp_snd_codec0 { clocks = <&clk 17>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; /* PMU1<->APU IPI mailbox controller */ ipi_mailbox_pmu1: mailbox@ff990400 { compatible = "xlnx,zynqmp-ipi-mailbox"; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-ids = <0 4>; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; }; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <4>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; sdhci0: sdhci@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: sdhci@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&pd_dp>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 0>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2cswitch@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "at,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 1 0 0 125000000>, <&lane1 1 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevB"; compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 0>; sda-gpios = <&gpio 37 0>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; }; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 0>; sda-gpios = <&gpio 7 0>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = <1>; io-standard = <1>; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* MIO on PAD */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 0>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "at,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; ina226@40 { /* u183 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 0>; sda-gpios = <&gpio 15 0>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 0>; sda-gpios = <&gpio 17 0>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = <1>; io-standard = <1>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = <1>; io-standard = <1>; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = <1>; io-standard = <1>; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 1 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 4 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "aclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { fclk0: fclk0 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 71>; }; fclk1: fclk1 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 72>; }; fclk2: fclk2 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 73>; }; fclk3: fclk3 { status = "disabled"; compatible = "xlnx,fclk"; clocks = <&clk 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clk: clk { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &can0 { clocks = <&clk 63>, <&clk 31>; }; &can1 { clocks = <&clk 64>, <&clk 31>; }; &cpu0 { clocks = <&clk 10>; }; &fpd_dma_chan1 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan2 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan3 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan4 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan5 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan6 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan7 { clocks = <&clk 19>, <&clk 31>; }; &fpd_dma_chan8 { clocks = <&clk 19>, <&clk 31>; }; &gpu { clocks = <&clk 24>, <&clk 25>, <&clk 26>; }; &lpd_dma_chan1 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan2 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan3 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan4 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan5 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan6 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan7 { clocks = <&clk 68>, <&clk 31>; }; &lpd_dma_chan8 { clocks = <&clk 68>, <&clk 31>; }; &nand0 { clocks = <&clk 60>, <&clk 31>; }; &gem0 { clocks = <&clk 31>, <&clk 104>, <&clk 45>, <&clk 49>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&clk 31>, <&clk 105>, <&clk 46>, <&clk 50>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&clk 31>, <&clk 106>, <&clk 47>, <&clk 51>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&clk 31>, <&clk 107>, <&clk 48>, <&clk 52>, <&clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&clk 31>; }; &i2c0 { clocks = <&clk 61>; }; &i2c1 { clocks = <&clk 62>; }; &perf_monitor_ocm { clocks = <&clk 31>; }; &pcie { clocks = <&clk 23>; }; &qspi { clocks = <&clk 53>, <&clk 31>; }; &sata { clocks = <&clk 22>; }; &sdhci0 { clocks = <&clk 54>, <&clk 31>; }; &sdhci1 { clocks = <&clk 55>, <&clk 31>; }; &spi0 { clocks = <&clk 58>, <&clk 31>; }; &spi1 { clocks = <&clk 59>, <&clk 31>; }; &ttc0 { clocks = <&clk 31>; }; &ttc1 { clocks = <&clk 31>; }; &ttc2 { clocks = <&clk 31>; }; &ttc3 { clocks = <&clk 31>; }; &uart0 { clocks = <&clk 56>, <&clk 31>; }; &uart1 { clocks = <&clk 57>, <&clk 31>; }; &usb0 { clocks = <&clk 32>, <&clk 34>; }; &usb1 { clocks = <&clk 33>, <&clk 34>; }; &watchdog0 { clocks = <&clk 75>; }; &lpd_watchdog { clocks = <&clk 75>; }; &xilinx_ams { clocks = <&clk 70>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&clk 17>, <&clk 16>; }; &xlnx_dpdma { clocks = <&clk 20>; }; &zynqmp_dp_snd_codec0 { clocks = <&clk 17>; }; &pcap { clocks = <&clk 41>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2018.3/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; power-domains { compatible = "xlnx,zynqmp-genpd"; pd_usb0: pd-usb0 { #power-domain-cells = <0x0>; pd-id = <0x16>; }; pd_usb1: pd-usb1 { #power-domain-cells = <0x0>; pd-id = <0x17>; }; pd_sata: pd-sata { #power-domain-cells = <0x0>; pd-id = <0x1c>; }; pd_spi0: pd-spi0 { #power-domain-cells = <0x0>; pd-id = <0x23>; }; pd_spi1: pd-spi1 { #power-domain-cells = <0x0>; pd-id = <0x24>; }; pd_uart0: pd-uart0 { #power-domain-cells = <0x0>; pd-id = <0x21>; }; pd_uart1: pd-uart1 { #power-domain-cells = <0x0>; pd-id = <0x22>; }; pd_eth0: pd-eth0 { #power-domain-cells = <0x0>; pd-id = <0x1d>; }; pd_eth1: pd-eth1 { #power-domain-cells = <0x0>; pd-id = <0x1e>; }; pd_eth2: pd-eth2 { #power-domain-cells = <0x0>; pd-id = <0x1f>; }; pd_eth3: pd-eth3 { #power-domain-cells = <0x0>; pd-id = <0x20>; }; pd_i2c0: pd-i2c0 { #power-domain-cells = <0x0>; pd-id = <0x25>; }; pd_i2c1: pd-i2c1 { #power-domain-cells = <0x0>; pd-id = <0x26>; }; pd_dp: pd-dp { #power-domain-cells = <0x0>; pd-id = <0x29>; }; pd_gdma: pd-gdma { #power-domain-cells = <0x0>; pd-id = <0x2a>; }; pd_adma: pd-adma { #power-domain-cells = <0x0>; pd-id = <0x2b>; }; pd_ttc0: pd-ttc0 { #power-domain-cells = <0x0>; pd-id = <0x18>; }; pd_ttc1: pd-ttc1 { #power-domain-cells = <0x0>; pd-id = <0x19>; }; pd_ttc2: pd-ttc2 { #power-domain-cells = <0x0>; pd-id = <0x1a>; }; pd_ttc3: pd-ttc3 { #power-domain-cells = <0x0>; pd-id = <0x1b>; }; pd_sd0: pd-sd0 { #power-domain-cells = <0x0>; pd-id = <0x27>; }; pd_sd1: pd-sd1 { #power-domain-cells = <0x0>; pd-id = <0x28>; }; pd_nand: pd-nand { #power-domain-cells = <0x0>; pd-id = <0x2c>; }; pd_qspi: pd-qspi { #power-domain-cells = <0x0>; pd-id = <0x2d>; }; pd_gpio: pd-gpio { #power-domain-cells = <0x0>; pd-id = <0x2e>; }; pd_can0: pd-can0 { #power-domain-cells = <0x0>; pd-id = <0x2f>; }; pd_can1: pd-can1 { #power-domain-cells = <0x0>; pd-id = <0x30>; }; pd_pcie: pd-pcie { #power-domain-cells = <0x0>; pd-id = <0x3b>; }; pd_gpu: pd-gpu { #power-domain-cells = <0x0>; pd-id = <0x3a 0x14 0x15>; }; }; /* PMU1<->APU IPI mailbox controller */ ipi_mailbox_pmu1: mailbox@ff990400 { compatible = "xlnx,zynqmp-ipi-mailbox"; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-ids = <0 4>; interrupt-parent = <&gic>; interrupts = <0 35 4>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; method = "smc"; }; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; rst: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_aes: zynqmp_aes { compatible = "xlnx,zynqmp-aes"; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&pd_can1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&pd_gdma>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&pd_gdma>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&pd_gdma>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&pd_gdma>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&pd_gdma>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&pd_gdma>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&pd_gdma>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&pd_gdma>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&pd_gpu>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&pd_adma>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&pd_adma>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&pd_adma>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&pd_adma>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&pd_adma>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&pd_adma>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&pd_adma>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&pd_adma>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&pd_nand>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&pd_eth0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&pd_eth1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&pd_eth2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&pd_eth3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&pd_gpio>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_i2c1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <4>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&pd_pcie>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&pd_qspi>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&rst 16>, <&rst 59>, <&rst 60>, <&rst 61>, <&rst 62>, <&rst 63>, <&rst 64>, <&rst 3>, <&rst 29>, <&rst 30>, <&rst 31>, <&rst 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&pd_sata>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&pd_sd0>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&pd_sd1>; }; pinctrl0: pinctrl@ff180000 { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; reg = <0x0 0xff180000 0x0 0x1000>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&pd_spi1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&pd_ttc3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&pd_uart1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&pd_usb1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&pd_dp>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&pd_dp>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,6-wire-mode; ti,dp83867-rxctrl-strap-quirk; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; reg = <0>; }; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <440000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; xlnx,bus-width = <64>; clocks = <&clk0212 &clk0212>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; }; }; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal SPP ITR8 HW 4.0"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333000>; }; alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333000>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333000>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; method = "smc"; #power-domain-cells = <0x1>; u-boot,dm-pre-reloc; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; power-domains = <&versal_firmware 0x18224021>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x18224035>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x18224036>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x18224037>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&versal_clk 96>, <&versal_clk 82>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-mailbox-count = <0x20>; rx-fifo-depth = <0x40>; power-domains = <&versal_firmware 0x1822401f>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&versal_clk 97>, <&versal_clk 82>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-mailbox-count = <0x20>; rx-fifo-depth = <0x40>; power-domains = <&versal_firmware 0x18224020>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x18224038>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x18224039>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x1822403a>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x1822403b>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; /* dma-coherent; */ power-domains = <&versal_firmware 0x1822403c>; }; gem0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; power-domains = <&versal_firmware 0x18224019>; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; gem1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; power-domains = <&versal_firmware 0x1822401a>; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; power-domains = <&versal_firmware 0x18224034>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ clocks = <&clk25 &clk25>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; power-domains = <&versal_firmware 0x1822402b>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <25000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; ospi: spi@f1010000 { compatible = "cadence,qspi"; status = "okay"; reg = <0x0 0xf1010000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25 &clk25>; num-cs = <1>; pinctrl-names = "default"; power-domains = <&versal_firmware 0x1822401b>; flash@0 { compatible = "m25p80"; spi-max-frequency = <25000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25 &clk25>; num-cs = <3>; power-domains = <&versal_firmware 0x1822401c>; flash@0 { compatible = "m25p80"; spi-max-frequency = <25000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; cci@fd000000 { status = "okay"; compatible = "arm,cci-500"; reg = <0x0 0xfd000000 0x0 0x10000>; ranges = <0x0 0x0 0xfd000000 0xa0000>; #address-cells = <0x1>; #size-cells = <0x1>; pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupt-parent = <&gic>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&versal_clk 59>, <&versal_clk 82>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; power-domains = <&versal_firmware 0x1822402e>; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&versal_clk 60>, <&versal_clk 82>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; power-domains = <&versal_firmware 0x1822402f>; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; power-domains = <&versal_firmware 0x18224018>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0x0 0x16 0x4>, <0x0 0x1A 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; /* dma-coherent; */ }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0x0 0xfd4d0000 0x0 0x10000>; status = "okay"; clocks = <&clk25>; }; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <0>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZC1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZC1275 RevB"; compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { no-1-8-v; }; &gem1 { psu_ethernet_1_mdio: mdio { phy1: phy@1 { device_type = "ethernet-phy"; reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; ina226@40 { /* u183 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "spi-flash"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; }; &dcc { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ ina226@40 { /* u60 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <1000>; }; ina226@41 { /* u61 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <1000>; }; ina226@42 { /* u63 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <1000>; }; ina226@43 { /* u65 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <1000>; }; ina226@44 { /* u64 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &gem3 { status = "okay"; phy-mode = "rgmii"; phy-handle = <&phy2>; phy2: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC */ }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-g-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-a2197-g-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; ina226@40 { /* u74 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <1000>; }; ina226@41 { /* u75 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <1000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u79 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <1000>; }; ina226@44 { /* u82 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; ina226@45 { /* u84 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-m-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <1>; */ }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@5d { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-p-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-a2197-p-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570BAB000299DG */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &i2c0 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; current-speed = <115200>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 71>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 72>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 73>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk 63>, <&zynqmp_clk 31>; }; &can1 { clocks = <&zynqmp_clk 64>, <&zynqmp_clk 31>; }; &cpu0 { clocks = <&zynqmp_clk 10>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &gpu { clocks = <&zynqmp_clk 24>, <&zynqmp_clk 25>, <&zynqmp_clk 26>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &nand0 { clocks = <&zynqmp_clk 60>, <&zynqmp_clk 31>; }; &gem0 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>, <&zynqmp_clk 49>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>, <&zynqmp_clk 50>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>, <&zynqmp_clk 51>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>, <&zynqmp_clk 52>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk 31>; }; &i2c0 { clocks = <&zynqmp_clk 61>; }; &i2c1 { clocks = <&zynqmp_clk 62>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk 31>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk 28>; }; &perf_monitor_cci { clocks = <&zynqmp_clk 28>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk 31>; }; &pcie { clocks = <&zynqmp_clk 23>; }; &qspi { clocks = <&zynqmp_clk 53>, <&zynqmp_clk 31>; }; &sata { clocks = <&zynqmp_clk 22>; }; &sdhci0 { clocks = <&zynqmp_clk 54>, <&zynqmp_clk 31>; }; &sdhci1 { clocks = <&zynqmp_clk 55>, <&zynqmp_clk 31>; }; &spi0 { clocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>; }; &spi1 { clocks = <&zynqmp_clk 59>, <&zynqmp_clk 31>; }; &ttc0 { clocks = <&zynqmp_clk 31>; }; &ttc1 { clocks = <&zynqmp_clk 31>; }; &ttc2 { clocks = <&zynqmp_clk 31>; }; &ttc3 { clocks = <&zynqmp_clk 31>; }; &uart0 { clocks = <&zynqmp_clk 56>, <&zynqmp_clk 31>; }; &uart1 { clocks = <&zynqmp_clk 57>, <&zynqmp_clk 31>; }; &usb0 { clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; }; &usb1 { clocks = <&zynqmp_clk 33>, <&zynqmp_clk 34>; }; &watchdog0 { clocks = <&zynqmp_clk 75>; }; &lpd_watchdog { clocks = <&zynqmp_clk 112>; }; &xilinx_ams { clocks = <&zynqmp_clk 70>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk 17>, <&zynqmp_clk 16>; }; &xlnx_dpdma { clocks = <&zynqmp_clk 20>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk 17>; }; &pcap { clocks = <&zynqmp_clk 41>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_aes: zynqmp_aes { compatible = "xlnx,zynqmp-aes"; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware 47>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware 48>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware 42>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware 58>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware 43>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware 44>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware 29>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware 30>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware 31>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware 32>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&zynqmp_firmware 46>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 37>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 38>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&zynqmp_firmware 59>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware 45>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&zynqmp_reset 16>, <&zynqmp_reset 59>, <&zynqmp_reset 60>, <&zynqmp_reset 61>, <&zynqmp_reset 62>, <&zynqmp_reset 63>, <&zynqmp_reset 64>, <&zynqmp_reset 3>, <&zynqmp_reset 29>, <&zynqmp_reset 30>, <&zynqmp_reset 31>, <&zynqmp_reset 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware 28>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware 39>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware 40>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 35>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 36>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 24>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 25>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 26>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 27>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware 33>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware 34>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware 22>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware 23>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware 41>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware 41>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,6-wire-mode; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; }; }; &dcc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &serial0 { status = "okay"; }; &serial1 { status = "disabled"; /* communication with MSP432 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "disabled"; /* u93 and u92 */ }; &ospi { status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "spi-flash"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { /* for testing purpose */ label = "ospi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { /* for testing purpose */ label = "ospi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { /* for testing purpose */ label = "ospi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { /* for testing purpose */ label = "ospi-rootfs"; reg = <0x6920000 0xa00000>; }; partition@7f40000 { label = "ospi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; &sdhci1 { /* U104 */ status = "okay"; xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &gpio { status = "okay"; }; &dcc { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ status = "okay"; xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; &sdhci1 { /* U104 */ status = "okay"; xlnx,mio_bank = <1>; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { status = "okay"; xlnx,mio_bank = <1>; }; &sdhci1 { /* U1A */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "spi-flash"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { status = "okay"; num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; spi-max-frequency = <25000000>; reg = <0>; partition@1 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &dcc { status = "okay"; }; /* SMAP via cc108 */ &can0 { status = "okay"; }; &can1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u7 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &serial0 { status = "okay"; }; &sdhci0 { /* J99 MIO28 - MIO33 */ status = "okay"; xlnx,mio_bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; /* Mutually exclusive with qspi */ &ospi { status = "okay"; /* U163/U97 MT35XU02G */ }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ status = "okay"; disable-wp; xlnx,mio_bank = <1>; /* FIXME */ }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ status = "okay"; disable-wp; xlnx,mio_bank = <1>; /* FIXME */ }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; /* FIXME */ }; phy2: phy@2 { /* VSC8531 */ reg = <2>; /* FIXME */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; num-cs = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; /* 16MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ status = "okay"; xlnx,mio_bank = <1>; /* FIXME */ }; &serial0 { status = "okay"; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ status = "okay"; xlnx,mio_bank = <1>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ status = "okay"; xlnx,mio_bank = <1>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ status = "okay"; xlnx,mio_bank = <1>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "spi-flash"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ status = "okay"; xlnx,mio_bank = <1>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@52 { compatible = "ti,ucd9248"; reg = <52>; }; hwmon@53 { compatible = "ti,ucd9248"; reg = <53>; }; hwmon@54 { compatible = "ti,ucd9248"; reg = <54>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x4d>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio_bank = <1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { psu_ethernet_1_mdio: mdio { phy1: ethernet-phy@1 { device_type = "ethernet-phy"; reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &gem3 { status = "okay"; phy-mode = "rgmii"; phy-handle = <&phy2>; phy2: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC */ }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <2000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <2000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps54012@44 { /* IRPS5401 - u53 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps54012@45 { /* IRPS5401 - u55 */ #clock-cells = <0>; compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "si5341"; reg = <0x36>; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "spi-flash"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; disable-wp; xlnx,mio_bank = <1>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &i2c0 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u160 IRPS5401 0x17/0x47 */ /* u167 IRPS5401 0x1c/0x4c */ /* u175 IRPS5401 0x1d/0x4d */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; /* R440 */ /* 0.78V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <2000>; /* R1186 */ /* 0.78V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1_clk: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* and connector J212D */ }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk 96>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk 97>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&can0_clk>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&can1_clk>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402a>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224029>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x8000>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>, <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>, <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; clock-names = "ref_clk", "pclk"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>; interrupt-map-mask = <0 0 0 7>; interrupt-parent = <&gic>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; timeout-sec = <60>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 71>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 72>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 73>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk 74>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk 63>, <&zynqmp_clk 31>; }; &can1 { clocks = <&zynqmp_clk 64>, <&zynqmp_clk 31>; }; &cpu0 { clocks = <&zynqmp_clk 10>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; }; &gpu { clocks = <&zynqmp_clk 24>, <&zynqmp_clk 25>, <&zynqmp_clk 26>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk 68>, <&zynqmp_clk 31>; }; &nand0 { clocks = <&zynqmp_clk 60>, <&zynqmp_clk 31>; }; &gem0 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>, <&zynqmp_clk 49>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>, <&zynqmp_clk 50>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>, <&zynqmp_clk 51>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>, <&zynqmp_clk 52>, <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk 31>; }; &i2c0 { clocks = <&zynqmp_clk 61>; }; &i2c1 { clocks = <&zynqmp_clk 62>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk 31>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk 28>; }; &perf_monitor_cci { clocks = <&zynqmp_clk 28>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk 31>; }; &pcie { clocks = <&zynqmp_clk 23>; }; &qspi { clocks = <&zynqmp_clk 53>, <&zynqmp_clk 31>; }; &sata { clocks = <&zynqmp_clk 22>; }; &sdhci0 { clocks = <&zynqmp_clk 54>, <&zynqmp_clk 31>; }; &sdhci1 { clocks = <&zynqmp_clk 55>, <&zynqmp_clk 31>; }; &spi0 { clocks = <&zynqmp_clk 58>, <&zynqmp_clk 31>; }; &spi1 { clocks = <&zynqmp_clk 59>, <&zynqmp_clk 31>; }; &ttc0 { clocks = <&zynqmp_clk 31>; }; &ttc1 { clocks = <&zynqmp_clk 31>; }; &ttc2 { clocks = <&zynqmp_clk 31>; }; &ttc3 { clocks = <&zynqmp_clk 31>; }; &uart0 { clocks = <&zynqmp_clk 56>, <&zynqmp_clk 31>; }; &uart1 { clocks = <&zynqmp_clk 57>, <&zynqmp_clk 31>; }; &usb0 { clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; }; &usb1 { clocks = <&zynqmp_clk 33>, <&zynqmp_clk 34>; }; &watchdog0 { clocks = <&zynqmp_clk 75>; }; &lpd_watchdog { clocks = <&zynqmp_clk 112>; }; &xilinx_ams { clocks = <&zynqmp_clk 70>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk 17>, <&zynqmp_clk 16>; }; &xlnx_dpdma { clocks = <&zynqmp_clk 20>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk 17>; }; &pcap { clocks = <&zynqmp_clk 41>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2019.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&pcap>; #address-cells = <2>; #size-cells = <2>; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_aes: zynqmp_aes { compatible = "xlnx,zynqmp-aes"; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware 47>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware 48>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware 42>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware 42>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware 58>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware 43>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware 43>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware 44>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware 29>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware 30>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware 31>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware 32>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; gpio-controller; power-domains = <&zynqmp_firmware 46>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 37>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 38>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&zynqmp_firmware 59>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware 45>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&zynqmp_reset 16>, <&zynqmp_reset 59>, <&zynqmp_reset 60>, <&zynqmp_reset 61>, <&zynqmp_reset 62>, <&zynqmp_reset 63>, <&zynqmp_reset 64>, <&zynqmp_reset 3>, <&zynqmp_reset 29>, <&zynqmp_reset 30>, <&zynqmp_reset 31>, <&zynqmp_reset 32>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware 28>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware 39>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware 40>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 35>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware 36>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 24>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 25>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 26>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware 27>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware 33>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware 34>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware 22>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware 23>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware 41>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware 41>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { hard-reset-gpios = <&reset_gpio 0 1>; }; &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &serial0 { status = "okay"; }; &serial1 { status = "disabled"; /* communication with MSP432 */ }; &ospi { status = "okay"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "disabled"; /* u93 and u92 */ }; &ospi { status = "okay"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &gpio { status = "okay"; }; &dcc { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ status = "okay"; xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio_bank = <1>; no-1-8-v; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { status = "okay"; num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &dcc { status = "okay"; }; /* SMAP via cc108 */ &can0 { status = "okay"; }; &can1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u7 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &serial0 { status = "okay"; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ no-1-8-v; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; /* Mutually exclusive with qspi */ &ospi { status = "okay"; /* U163/U97 MT35XU02G */ }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; /* FIXME */ }; phy2: phy@2 { /* VSC8531 */ reg = <2>; /* FIXME */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; num-cs = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* connector */ xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { status = "okay"; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio_bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio_bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio_bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { /* U-Boot gmii-to-rgmii bridge */ phy-mode = "gmii"; phy-handle = <&gmiitorgmii>; phy: ethernet-phy@0 { reg = <0x0>; }; gmiitorgmii: gmiitorgmii@8 { compatible = "xlnx,gmii-to-rgmii-1.0"; reg = <8>; phy-handle = <&phy>; }; /* Linux gmii-to-rgmii bridge */ mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { status = "okay"; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "si5341"; reg = <0x36>; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio_bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "si5341"; reg = <0x36>; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; disable-wp; xlnx,mio_bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &i2c0 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; /* R440 */ /* 0.78V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <2000>; /* R1186 */ /* 0.78V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* and connector J212D */ }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x8000>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>, <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>, <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; clock-names = "ref_clk", "pclk"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>; interrupt-map-mask = <0 0 0 7>; interrupt-parent = <&gic>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; timeout-sec = <60>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; }; &xlnx_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_aes: zynqmp_aes { compatible = "xlnx,zynqmp-aes"; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, <&zynqmp_reset ZYNQMP_RESET_DP>, <&zynqmp_reset ZYNQMP_RESET_GEM0>, <&zynqmp_reset ZYNQMP_RESET_GEM1>, <&zynqmp_reset ZYNQMP_RESET_GEM2>, <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Signed-off-by: Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio_bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &serial0 { status = "okay"; }; &serial1 { status = "disabled"; /* communication with MSP432 */ }; &ospi { status = "okay"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "disabled"; /* u93 and u92 */ }; &ospi { status = "okay"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &gpio { status = "okay"; }; &dcc { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ status = "okay"; xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &dcc { status = "okay"; }; &watchdog { status = "okay"; }; &qspi { status = "okay"; /* u93 and u92 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &serial0 { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio_bank = <1>; no-1-8-v; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { status = "okay"; num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &dcc { status = "okay"; }; /* SMAP via cc108 */ &can0 { status = "okay"; }; &can1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u7 */ num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &serial0 { status = "okay"; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ no-1-8-v; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; /* Mutually exclusive with qspi */ &ospi { status = "okay"; /* U163/U97 MT35XU02G */ }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { status = "okay"; phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { /* MIO35 - MIO37 */ status = "okay"; }; &serial1 { /* MIO4 - MIO7 RS232 */ status = "okay"; }; &spi0 { status = "okay"; num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { status = "okay"; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = <6>; vsc8531,tx-delay = <6>; }; }; &gem1 { status = "okay"; phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "okay"; num-cs = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* connector */ xlnx,mio_bank = <1>; /* FIXME */ no-1-8-v; }; &serial0 { status = "okay"; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { status = "okay"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &serial0 { status = "okay"; }; &serial1 { status = "disabled"; /* communication with MSP432 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { status = "okay"; num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio_bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &can1 { /* MIO40-41 */ status = "okay"; }; &dcc { status = "okay"; }; &rtc { status = "okay"; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &watchdog { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio_bank = <1>; no-1-8-v; }; &serial0 { /* PMC_MIO42/43 */ status = "okay"; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ status = "okay"; phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ status = "okay"; phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 150000000>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; io-standard = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "si5341"; reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ compatible = "silabs,si5328"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; io-standard = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; io-standard = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { status = "okay"; clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { status = "okay"; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "si5341"; reg = <0x36>; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "si5341"; reg = <0x36>; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; io-standard = ; }; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &i2c0 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { status = "okay"; u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* and connector J212D */ }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { status = "okay"; is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { status = "okay"; gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ status = "okay"; u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ status = "okay"; u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "okay"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { status = "okay"; gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ status = "okay"; clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { status = "okay"; xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { status = "okay"; dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&lane1 PHY_TYPE_USB3 0 1 26000000>; }; &usb1 { status = "okay"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "okay"; }; &xilinx_ams { status = "okay"; }; &ams_ps { status = "okay"; }; &ams_pl { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupt-parent = <&gic>; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupt-parent = <&gic>; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupt-parent = <&gic>; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupt-parent = <&gic>; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x8000>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>, <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>, <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; clock-names = "ref_clk", "pclk"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>; interrupt-map-mask = <0 0 0 7>; interrupt-parent = <&gic>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; }; &xlnx_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2020.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; xlnx_rsa: zynqmp_rsa { compatible = "xlnx,zynqmp-rsa"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_aes: zynqmp_aes { compatible = "xlnx,zynqmp-aes"; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: amba { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; serdes: zynqmp_phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, <&zynqmp_reset ZYNQMP_RESET_DP>, <&zynqmp_reset ZYNQMP_RESET_GEM0>, <&zynqmp_reset ZYNQMP_RESET_GEM1>, <&zynqmp_reset ZYNQMP_RESET_GEM2>, <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst"; lane0: lane0 { #phy-cells = <4>; }; lane1: lane1 { #phy-cells = <4>; }; lane2: lane2 { #phy-cells = <4>; }; lane3: lane3 { #phy-cells = <4>; }; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { compatible = "xlnx,video0"; }; dma-video1channel { compatible = "xlnx,video1"; }; dma-video2channel { compatible = "xlnx,video2"; }; dma-graphicschannel { compatible = "xlnx,graphics"; }; dma-audio0channel { compatible = "xlnx,audio0"; }; dma-audio1channel { compatible = "xlnx,audio1"; }; }; zynqmp_dpsub: zynqmp-display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; vid-layer { dma-names = "vid0", "vid1", "vid2"; dmas = <&xlnx_dpdma 0>, <&xlnx_dpdma 1>, <&xlnx_dpdma 2>; }; gfx-layer { dma-names = "gfx0"; dmas = <&xlnx_dpdma 3>; }; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&xlnx_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; io-standard = ; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; no-1-8-v; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = <6>; vsc8531,tx-delay = <6>; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PWM via MIO 41/FAN TACH MIO 49 - FIXME */ &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &amba { ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xfffc0000 0x10000>; ocm-sram@0 { reg = <0x0 0x10000>; }; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; io-standard = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; io-standard = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; io-standard = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; io-standard = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; io-standard = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ compatible = "idt,8t49n287"; reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5382: clock-generator@69 { /* SI5382 - u48 */ compatible = "silabs,si5382"; reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; chosen { xlnx,eeprom = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>; }; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { xlnx,eeprom = <&eeprom>; /* FIXME */ /* xlnx,fmc-eeprom = FIXME */ }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva-mlcc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP K26 RevA"; compatible = "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; si5332_1: si5332_1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; si5332_2: si5332_2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5332_3: si5332_3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; si5332_4: si5332_4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5332_5: si5332_5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { status = "okay"; /* pcie, usb3, sata */ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; clock-names = "ref0", "ref1", "ref2"; }; &uart1 { /* MIO36/MIO37 */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; }; &zynqmp_dpsub { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; maximum-speed = "super-speed"; }; &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * SD 3.0 requires level shifter and this property * should be removed if the board has level shifter and * need to work in UHS mode */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_9_grp"; function = "uart1"; }; conf { groups = "uart1_9_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_6_grp"; function = "i2c1"; }; conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO72", "MIO74"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0x8>; ti,fifo-depth = <0x01>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; usbhub: usb5744 { compatible = "microchip,usb5744"; reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01-mlcc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP K26 RevA"; compatible = "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; si5332_1: si5332_1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; si5332_2: si5332_2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5332_3: si5332_3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; si5332_4: si5332_4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5332_5: si5332_5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { status = "okay"; /* pcie, usb3, sata */ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; clock-names = "ref0", "ref1", "ref2"; }; &uart1 { /* MIO36/MIO37 */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; }; &zynqmp_dpsub { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; maximum-speed = "super-speed"; }; &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * SD 3.0 requires level shifter and this property * should be removed if the board has level shifter and * need to work in UHS mode */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_9_grp"; function = "uart1"; }; conf { groups = "uart1_9_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_6_grp"; function = "i2c1"; }; conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO72", "MIO74"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0x8>; ti,fifo-depth = <0x01>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; usbhub: usb5744 { compatible = "microchip,usb5744"; reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-reva01.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP K26 RevA"; compatible = "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &uart1 { /* MIO36/MIO37 */ status = "okay"; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ status = "okay"; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb-mlcc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revB * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP K26 Rev1.0/B"; compatible = "xlnx,zynqmp-sm-k26-rev1.0", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; si5332_1: si5332_1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; si5332_2: si5332_2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5332_3: si5332_3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; si5332_4: si5332_4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5332_5: si5332_5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &uart1 { /* MIO37/MIO38 */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; usbhub: usb5744@2d { /* u43 */ compatible = "microchip,usb5744"; reg = <0x2d>; reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &psgtr { status = "okay"; /* pcie, usb3, sata */ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; clock-names = "ref0", "ref1", "ref2"; }; &zynqmp_dpsub { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; maximum-speed = "super-speed"; }; &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * SD 3.0 requires level shifter and this property * should be removed if the board has level shifter and * need to work in UHS mode */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; clk-phase-sd-hs = <126>, <60>; clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; }; &pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_9_grp"; function = "uart1"; }; conf { groups = "uart1_9_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_6_grp"; function = "i2c1"; }; conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO72", "MIO74"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0x8>; ti,fifo-depth = <0x01>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revB * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP K26 Rev1/B"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01-mlcc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revB * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP K26 Rev1.0/B"; compatible = "xlnx,zynqmp-sm-k26-rev1.0", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; si5332_0: si5332_0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; si5332_1: si5332_1 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; si5332_2: si5332_2 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5332_3: si5332_3 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; }; si5332_4: si5332_4 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5332_5: si5332_5 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &uart1 { /* MIO37/MIO38 */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; usbhub: usb5744@2d { /* u43 */ compatible = "microchip,usb5744"; reg = <0x2d>; reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &psgtr { status = "okay"; /* pcie, usb3, sata */ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>; clock-names = "ref0", "ref1", "ref2"; }; &zynqmp_dpsub { status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; maximum-speed = "super-speed"; }; &sdhci1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * SD 3.0 requires level shifter and this property * should be removed if the board has level shifter and * need to work in UHS mode */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; clk-phase-sd-hs = <126>, <60>; clk-phase-uhs-sdr25 = <120>, <60>; clk-phase-uhs-ddr50 = <126>, <48>; }; &pinctrl0 { status = "okay"; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_9_grp"; function = "uart1"; }; conf { groups = "uart1_9_grp"; slew-rate = ; io-standard = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_6_grp"; function = "i2c1"; }; conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO72", "MIO74"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO71", "MIO73", "MIO75"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0x8>; ti,fifo-depth = <0x01>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-sm-k26-revb01.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP K26 revB * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP K26 Rev1.0/B"; compatible = "xlnx,zynqmp-sm-k26-rev1.0", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ status = "okay"; flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &spi1 { /* MIO6, 9-11 */ status = "okay"; label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { status = "okay"; gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@c0 { /* u266 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_1: clock-generator@5d { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; // FIXME not in schematics clock-frequency = <300000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 1>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>, <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>, <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; clock-names = "ref_clk", "pclk"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 1>, <0 0 0 2 &pcie_intc_0 2>, <0 0 0 3 &pcie_intc_0 3>, <0 0 0 4 &pcie_intc_0 4>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { compatible = "xlnx,zynqmp-aes"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_rsa: zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpio = <&modepin_gpio 1 0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #stream-id-cells = <1>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpsub: display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; #stream-id-cells = <1>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105-tmr.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; no-1-8-v; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = <6>; vsc8531,tx-delay = <6>; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ no-1-8-v; }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &qspi { num-cs = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci0 { /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &ospi { /* U97 MT35XU02G */ bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; sdhci-caps-mask = <0 0x200000>; sdhci-caps = <0 0>; max-frequency = <19000000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PWM via MIO 41/FAN TACH MIO 49 - FIXME */ &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &amba { ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xfffc0000 0x10000>; ocm-sram@0 { reg = <0x0 0x10000>; }; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phyc>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { /* * Enable all GTs to out from U-Boot * i2c mw 20 6 0 - setup IO to output * i2c mw 20 2 ef - setup output values on pins 0-7 * i2c mw 20 3 ff - setup output values on pins 10-17 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; /* drivers/hwmon/pmbus/Kconfig:86: be called max20751. drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o */ max20751@72 { /* u95 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; /* FIXME PMOD - j160 */ /* FIXME MSP430F - u41 - not detected */ }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* FIXME PL i2c via PCA9306 - u45 */ /* FIXME MSP430 - u41 - not detected */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { /* i2c mw 74 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { /* i2c mw 74 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator1@36 { /* SI5341 - u69 */ compatible = "si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { /* i2c mw 74 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator2@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { /* i2c mw 74 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { /* i2c mw 74 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator4@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom1; nvmem1 = &eeprom0; }; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &i2c1 { /* i2c1 MIO 24-25 */ u-boot,dm-pre-reloc; clock-frequency = <400000>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart1 { /* uart0 MIO36-37 */ u-boot,dm-pre-reloc; }; &usb0 { pinctrl-names = "default"; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35 { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36 { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@c0 { /* u266 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; si570_user1_fmc_clk: si570_user1_fmc_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570_lpddr4_clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * * Open Drain/Collector is the combination of single-ended open drain interface. * * Open Source/Emitter is the combination of single-ended open source interface. * */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume persistence */ #define GPIO_SLEEP_MAINTAIN_VALUE 0 #define GPIO_SLEEP_MAY_LOOSE_VALUE 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_ASSISTANT 0x247 /* AL Context-aware desktop assistant */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 /* Diagonal movement keys */ #define KEY_RIGHT_UP 0x266 #define KEY_RIGHT_DOWN 0x267 #define KEY_LEFT_UP 0x268 #define KEY_LEFT_DOWN 0x269 #define KEY_ROOT_MENU 0x26a /* Show Device's Root Menu */ /* Show Top Menu of the Media (e.g. DVD) */ #define KEY_MEDIA_TOP_MENU 0x26b #define KEY_NUMERIC_11 0x26c #define KEY_NUMERIC_12 0x26d /* * Toggle Audio Description: refers to an audio service that helps blind and * visually impaired consumers understand the action in a program. Note: in * some countries this is referred to as "Video Description". */ #define KEY_AUDIO_DESC 0x26e #define KEY_3D_MODE 0x26f #define KEY_NEXT_FAVORITE 0x270 #define KEY_STOP_RECORD 0x271 #define KEY_PAUSE_RECORD 0x272 #define KEY_VOD 0x273 /* Video on Demand */ #define KEY_UNMUTE 0x274 #define KEY_FASTREVERSE 0x275 #define KEY_SLOWREVERSE 0x276 /* * Control a data application associated with the currently viewed channel, * e.g. teletext or data broadcast application (MHEG, MHP, HbbTV, etc.) */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_SGMII 7 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Author: Chirag Parekh * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 as published by the Free Software Foundation. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for IO standards */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin inputs */ #define PIN_INPUT_TYPE_CMOS 0 #define PIN_INPUT_TYPE_SCHMITT 1 /* Bit values for drive control*/ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_RPU0_0 (0x18110005U) #define PM_DEV_RPU0_1 (0x18110006U) #define PM_DEV_OCM_0 (0x18314007U) #define PM_DEV_OCM_1 (0x18314008U) #define PM_DEV_OCM_2 (0x18314009U) #define PM_DEV_OCM_3 (0x1831400aU) #define PM_DEV_TCM_0_A (0x1831800bU) #define PM_DEV_TCM_0_B (0x1831800cU) #define PM_DEV_TCM_1_A (0x1831800dU) #define PM_DEV_TCM_1_B (0x1831800eU) #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_RPU 6 #define PD_RPU_0 7 #define PD_RPU_1 8 #define PD_OCM_0 11 #define PD_OCM_1 12 #define PD_OCM_2 13 #define PD_OCM_3 14 #define PD_TCM_0_A 15 #define PD_TCM_0_B 16 #define PD_TCM_1_A 17 #define PD_TCM_1_B 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>, <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>, <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; clock-names = "ref_clk", "pclk"; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { #address-cells = <1>; #size-cells = <1>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; compatible = "arm,pl353-smc-r2p1", "arm,primecell"; interrupt-parent = <&intc>; interrupts = <0 18 4>; ranges ; reg = <0xe000e000 0x1000>; nand0: flash@e1000000 { status = "disabled"; compatible = "arm,pl353-nand-r2p1"; reg = <0xe1000000 0x1000000>; #address-cells = <0x1>; #size-cells = <0x1>; }; nor0: flash@e2000000 { status = "disabled"; compatible = "cfi-flash"; reg = <0xe2000000 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2021.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { compatible = "xlnx,zynqmp-aes"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_rsa: zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: dwc3@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: dwc3@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #stream-id-cells = <1>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpsub: display@fd4a0000 { compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; interrupts = <0 119 4>; interrupt-parent = <&gic>; #stream-id-cells = <1>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105-tmr.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = <6>; vsc8531,tx-delay = <6>; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "earlycon"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; #stream-id-cells = <1>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PWM via MIO 41/FAN TACH MIO 49 - FIXME */ &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &amba { ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0xfffc0000 0x10000>; ocm-sram@0 { reg = <0x0 0x10000>; }; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; /* phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;*/ }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom1; nvmem1 = &eeprom0; }; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@c0 { /* u53 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vpp_2v5_ddr4: tps544@1x { /* u3007 */ compatible = "ti,tps544b25"; reg = <0x17>; /* FIXME wrong in schematics */ }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@c0 { /* u69 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x60>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-delay-us = <2>; phy0: ethernet-phy@1 { #phy-cells = <1>; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; }; &i2c1 { /* i2c1 MIO 24-25 */ u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "peripheral"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@c0 { /* u266 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0xc0>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; si570_user1_fmc_clk: si570_user1_fmc_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570_lpddr4_clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; #stream-id-cells = <1>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "cdns,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "cdns,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; #stream-id-cells = <1>; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; #stream-id-cells = <1>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocmc: ocmc@f800c000 { compatible = "xlnx,zynq-ocmc-1.0"; interrupt-parent = <&intc>; interrupts = <0 3 4>; reg = <0xf800c000 0x1000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { compatible = "xlnx,zynqmp-aes"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_rsa: zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; power-domains = <&zynqmp_firmware PD_PL>; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; #stream-id-cells = <4>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #stream-id-cells = <1>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp_aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; #stream-id-cells = <1>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105-tmr.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; chosen { nvmem0 = &eeprom; }; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-emu-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-net-emu-1.9", "xlnx,versal-net-emu"; model = "Xilinx Versal NET EMU 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x10000000>; device_type = "memory"; }; aliases { serial0 = &serial0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh maxcpus=4"; stdout-path = "serial0:115200"; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; clk1: clk1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; /* it doesn't matter on EMU */ }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,sbsa-uart"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET IPP/SPP OSPI * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-net-ipp-rev1.9.dtsi" / { model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; }; &ospi { status = "okay"; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30"; stdout-path = "serial0:115200"; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; clk1: clk1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; }; clk2_6: clk2_6 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <2670000>; }; clk20: clk20 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&clk25>, <&clk25>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&clk25>, <&clk25>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>; phy1: ethernet-phy@1 { reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>; phy2: ethernet-phy@2 { reg = <2>; max-speed = <100>; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&clk25>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&clk25>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&clk20>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&clk20>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&clk25>, <&clk25>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; no-1-8-v; clocks = <&clk20>, <&clk20>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; no-1-8-v; clocks = <&clk20>, <&clk20>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,sbsa-uart"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>, <&clk25>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>, <&clk25>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&clk1>, <&clk1>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&clk60>, <&clk60>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&clk60 &clk60>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; xlnx,usb-polarity = <0x00>; xlnx,usb-reset-mode = <0x00>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecc10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 139 1>, <0 140 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecd10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 143 1>, <0 144 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xece10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 147 1>, <0 148 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecf10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 164 1>, <0 165 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA-x-prc-04 revA OSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; spi1 = &spi0; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <1>; /* FIXME */ }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { status = "disabled"; /* u93 and u92 and u161 and u160 */ num-cs = <1>; is-dual = <1>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { no-1-8-v; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ no-1-8-v; }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "spi-flash"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <1>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = <6>; vsc8531,tx-delay = <6>; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revA * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revA", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <0>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,device_id = <1>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; phy2: ethernet-phy@2 { /* u134 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; }; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; &usb0 { /* PMC_MIO13_500 - PMC_MIO25 USB 2.0 */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ status = "okay"; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PWM via MIO 41/FAN TACH MIO 49 - FIXME */ &i2c0 { /* PMC_MIO46/47 */ status = "okay"; clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ status = "okay"; clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &usb0 { /* PMC_MIO_500 13 - 25 USB 2.0 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c0 { /* PMC_MIO46/47 */ clock-frequency = <400000>; }; &i2c1 { /* PMC_MIO44/45 */ clock-frequency = <400000>; /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; spi0 = &qspi; usb0 = &usb0; }; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb1; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; sw13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { xlnx,eeprom = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; phyc: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { nvmem0 = &eeprom; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; chosen { nvmem0 = &eeprom; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { nvmem0 = <&eeprom>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; chosen { nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: ethernet-phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; nvmem0 = &eeprom1; nvmem1 = &eeprom0; serial0 = &uart0; }; chosen { nvmem0 = &eeprom1; nvmem1 = &eeprom0; }; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; chosen { nvmem0 = <&eeprom>; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x6c>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5d { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-e-a2197-00-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevB System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-e-a2197-00-reva.dtsi" / { model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; /delete-node/ ina226-vcco-500; /delete-node/ ina226-vcco-501; /delete-node/ ina226-vcco-502; }; &i2c0 { i2c-mux@74 { /* u33 */ i2c@2 { /* PCIE_CLK */ /delete-node/ clock-generator@6c; }; i2c@3 { /* PMBUS2_INA226 */ /delete-node/ ina226@42; /delete-node/ ina226@43; /delete-node/ ina226@44; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; usb0 = &usb0; }; chosen { nvmem0 = <&eeprom>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &usb0 { /* USB0 MIO52-63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; chosen { nvmem0 = <&eeprom>; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &usb0 { xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; }; chosen { nvmem0 = <&eeprom>; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x60>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &usb1 { xlnx,usb-polarity = <0x0>; xlnx,usb-reset-mode = <0x0>; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 1>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <100>; reset-deassert-us = <280>; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; }; &i2c1 { /* i2c1 MIO 24-25 */ u-boot,dm-pre-reloc; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &uart1 { /* uart0 MIO36-37 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "peripheral"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; &pinctrl0 { /* required by spec */ status = "okay"; pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; mux { groups = "uart1_9_grp"; function = "uart1"; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; power-source = ; }; mux { groups = "i2c1_6_grp"; function = "i2c1"; }; }; pinctrl_i2c1_gpio: i2c1-gpio { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; power-source = ; }; mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; }; pinctrl_gem1_default: gem1-default { conf { groups = "ethernet1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO44", "MIO46", "MIO48"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO45", "MIO47", "MIO49"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; low-power-enable; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; mux { function = "ethernet1"; groups = "ethernet1_0_grp"; }; }; pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; mux { groups = "usb0_0_grp"; function = "usb0"; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; si570_user1_fmc_clk: si570_user1_fmc_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570_lpddr4_clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-net-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H #define _DT_BINDINGS_VERSAL_NET_POWER_H #include "xlnx-versal-power.h" #define PM_DEV_USB_1 (0x182240D7U) /* Remove Versal specific node IDs */ #undef PM_DEV_RPU0_0 #undef PM_DEV_RPU0_1 #undef PM_DEV_OCM_0 #undef PM_DEV_OCM_1 #undef PM_DEV_OCM_2 #undef PM_DEV_OCM_3 #undef PM_DEV_TCM_0_A #undef PM_DEV_TCM_1_A #undef PM_DEV_TCM_0_B #undef PM_DEV_TCM_1_B #undef PM_DEV_SWDT_FPD #undef PM_DEV_ADMA_0 #undef PM_DEV_ADMA_1 #undef PM_DEV_ADMA_2 #undef PM_DEV_ADMA_3 #undef PM_DEV_ADMA_4 #undef PM_DEV_ADMA_5 #undef PM_DEV_ADMA_6 #undef PM_DEV_ADMA_7 #undef PM_DEV_AI #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-versal-regnode.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H #define _DT_BINDINGS_VERSAL_REGNODE_H #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-net-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H #define _DT_BINDINGS_VERSAL_NET_RESETS_H #include "xlnx-versal-resets.h" #define VERSAL_RST_USB_1 (0xc4100c6U) /* Remove Versal specific reset IDs */ #undef VERSAL_RST_ACPU_0_POR #undef VERSAL_RST_ACPU_1_POR #undef VERSAL_RST_OCM2_POR #undef VERSAL_RST_APU #undef VERSAL_RST_ACPU_0 #undef VERSAL_RST_ACPU_1 #undef VERSAL_RST_ACPU_L2 #undef VERSAL_RST_RPU_ISLAND #undef VERSAL_RST_RPU_AMBA #undef VERSAL_RST_R5_0 #undef VERSAL_RST_R5_1 #undef VERSAL_RST_OCM2_RST #undef VERSAL_RST_I2C_PMC #undef VERSAL_RST_I2C_0 #undef VERSAL_RST_I2C_1 #undef VERSAL_RST_SWDT_FPD #undef VERSAL_RST_SWDT_LPD #undef VERSAL_RST_USB #undef VERSAL_RST_DPC #undef VERSAL_RST_DBG_TRACE #undef VERSAL_RST_DBG_TSTMP #undef VERSAL_RST_RPU0_DBG #undef VERSAL_RST_RPU1_DBG #undef VERSAL_RST_HSDP #undef VERSAL_RST_CPMDBG #undef VERSAL_RST_PCIE_CFG #undef VERSAL_RST_PCIE_CORE0 #undef VERSAL_RST_PCIE_CORE1 #undef VERSAL_RST_PCIE_DMA #undef VERSAL_RST_L2_0 #undef VERSAL_RST_L2_1 #undef VERSAL_RST_ADDR_REMAP #undef VERSAL_RST_CPI0 #undef VERSAL_RST_CPI1 #undef VERSAL_RST_XRAM #undef VERSAL_RST_AIE_ARRAY #undef VERSAL_RST_AIE_SHIM #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-versal-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H #define _DT_BINDINGS_VERSAL_RESETS_H #define VERSAL_RST_PMC_POR (0xc30c001U) #define VERSAL_RST_PMC (0xc410002U) #define VERSAL_RST_PS_POR (0xc30c003U) #define VERSAL_RST_PL_POR (0xc30c004U) #define VERSAL_RST_NOC_POR (0xc30c005U) #define VERSAL_RST_FPD_POR (0xc30c006U) #define VERSAL_RST_ACPU_0_POR (0xc30c007U) #define VERSAL_RST_ACPU_1_POR (0xc30c008U) #define VERSAL_RST_OCM2_POR (0xc30c009U) #define VERSAL_RST_PS_SRST (0xc41000aU) #define VERSAL_RST_PL_SRST (0xc41000bU) #define VERSAL_RST_NOC (0xc41000cU) #define VERSAL_RST_NPI (0xc41000dU) #define VERSAL_RST_SYS_RST_1 (0xc41000eU) #define VERSAL_RST_SYS_RST_2 (0xc41000fU) #define VERSAL_RST_SYS_RST_3 (0xc410010U) #define VERSAL_RST_FPD (0xc410011U) #define VERSAL_RST_PL0 (0xc410012U) #define VERSAL_RST_PL1 (0xc410013U) #define VERSAL_RST_PL2 (0xc410014U) #define VERSAL_RST_PL3 (0xc410015U) #define VERSAL_RST_APU (0xc410016U) #define VERSAL_RST_ACPU_0 (0xc410017U) #define VERSAL_RST_ACPU_1 (0xc410018U) #define VERSAL_RST_ACPU_L2 (0xc410019U) #define VERSAL_RST_ACPU_GIC (0xc41001aU) #define VERSAL_RST_RPU_ISLAND (0xc41001bU) #define VERSAL_RST_RPU_AMBA (0xc41001cU) #define VERSAL_RST_R5_0 (0xc41001dU) #define VERSAL_RST_R5_1 (0xc41001eU) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) #define VERSAL_RST_SYSMON_LPD (0xc410023U) #define VERSAL_RST_PDMA_RST1 (0xc410024U) #define VERSAL_RST_PDMA_RST0 (0xc410025U) #define VERSAL_RST_ADMA (0xc410026U) #define VERSAL_RST_TIMESTAMP (0xc410027U) #define VERSAL_RST_OCM (0xc410028U) #define VERSAL_RST_OCM2_RST (0xc410029U) #define VERSAL_RST_IPI (0xc41002aU) #define VERSAL_RST_SBI (0xc41002bU) #define VERSAL_RST_LPD (0xc41002cU) #define VERSAL_RST_QSPI (0xc10402dU) #define VERSAL_RST_OSPI (0xc10402eU) #define VERSAL_RST_SDIO_0 (0xc10402fU) #define VERSAL_RST_SDIO_1 (0xc104030U) #define VERSAL_RST_I2C_PMC (0xc104031U) #define VERSAL_RST_GPIO_PMC (0xc104032U) #define VERSAL_RST_GEM_0 (0xc104033U) #define VERSAL_RST_GEM_1 (0xc104034U) #define VERSAL_RST_SPARE (0xc104035U) #define VERSAL_RST_USB_0 (0xc104036U) #define VERSAL_RST_UART_0 (0xc104037U) #define VERSAL_RST_UART_1 (0xc104038U) #define VERSAL_RST_SPI_0 (0xc104039U) #define VERSAL_RST_SPI_1 (0xc10403aU) #define VERSAL_RST_CAN_FD_0 (0xc10403bU) #define VERSAL_RST_CAN_FD_1 (0xc10403cU) #define VERSAL_RST_I2C_0 (0xc10403dU) #define VERSAL_RST_I2C_1 (0xc10403eU) #define VERSAL_RST_GPIO_LPD (0xc10403fU) #define VERSAL_RST_TTC_0 (0xc104040U) #define VERSAL_RST_TTC_1 (0xc104041U) #define VERSAL_RST_TTC_2 (0xc104042U) #define VERSAL_RST_TTC_3 (0xc104043U) #define VERSAL_RST_SWDT_FPD (0xc104044U) #define VERSAL_RST_SWDT_LPD (0xc104045U) #define VERSAL_RST_USB (0xc104046U) #define VERSAL_RST_DPC (0xc208047U) #define VERSAL_RST_PMCDBG (0xc208048U) #define VERSAL_RST_DBG_TRACE (0xc208049U) #define VERSAL_RST_DBG_FPD (0xc20804aU) #define VERSAL_RST_DBG_TSTMP (0xc20804bU) #define VERSAL_RST_RPU0_DBG (0xc20804cU) #define VERSAL_RST_RPU1_DBG (0xc20804dU) #define VERSAL_RST_HSDP (0xc20804eU) #define VERSAL_RST_DBG_LPD (0xc20804fU) #define VERSAL_RST_CPM_POR (0xc30c050U) #define VERSAL_RST_CPM (0xc410051U) #define VERSAL_RST_CPMDBG (0xc208052U) #define VERSAL_RST_PCIE_CFG (0xc410053U) #define VERSAL_RST_PCIE_CORE0 (0xc410054U) #define VERSAL_RST_PCIE_CORE1 (0xc410055U) #define VERSAL_RST_PCIE_DMA (0xc410056U) #define VERSAL_RST_CMN (0xc410057U) #define VERSAL_RST_L2_0 (0xc410058U) #define VERSAL_RST_L2_1 (0xc410059U) #define VERSAL_RST_ADDR_REMAP (0xc41005aU) #define VERSAL_RST_CPI0 (0xc41005bU) #define VERSAL_RST_CPI1 (0xc41005cU) #define VERSAL_RST_XRAM (0xc30c05dU) #define VERSAL_RST_AIE_ARRAY (0xc10405eU) #define VERSAL_RST_AIE_SHIM (0xc10405fU) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" #include "include/dt-bindings/power/xlnx-versal-regnode.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_reset: reset-controller { compatible = "xlnx,versal-reset"; #reset-cells = <1>; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; resets = <&versal_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_clk USB0_BUS_REF>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; &sysmon0 { xlnx,nodeid = ; }; &sysmon1 { xlnx,nodeid = ; }; &sysmon2 { xlnx,nodeid = ; }; &sysmon3 { xlnx,nodeid = ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupts = <0 10 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,sbsa-uart"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; clock-names = "uart_clk", "apb_clk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xC0000000>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,mask_phy_reset; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; xilsem_edac: edac@f2014050 { compatible = "xlnx,versal-xilsem-edac"; status = "disabled"; reg = <0x0 0xf2014050 0x0 0xc4>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/versal-net/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; mmc0 = &sdhci1; mmc1 = &sdhci0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30"; stdout-path = "serial0:115200"; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; clk1: clk1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; }; clk2_6: clk2_6 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <2670000>; }; clk20: clk20 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <20000000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&clk100>, <&clk100>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&clk25>, <&clk25>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&clk25>, <&clk25>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>; phy1: ethernet-phy@1 { reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&clk2_6>, <&clk25>, <&clk25>, <&clk25>, <&clk25>; phy2: ethernet-phy@2 { reg = <2>; max-speed = <100>; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&clk25>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&clk25>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&clk20>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,is-stig-pgm = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&clk20>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&clk25>, <&clk25>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; no-1-8-v; clocks = <&clk20>, <&clk20>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; no-1-8-v; clocks = <&clk20>, <&clk20>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,sbsa-uart"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>, <&clk25>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>, <&clk25>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&clk1>, <&clk1>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&clk60>, <&clk60>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; xlnx,usb-polarity = <0>; xlnx,usb-reset-mode = <0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&clk60 &clk60>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; xlnx,usb-polarity = <0x00>; xlnx,usb-reset-mode = <0x00>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; snps,mask_phy_reset; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecc10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 139 1>, <0 140 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecd10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 143 1>, <0 144 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xece10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 147 1>, <0 148 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecf10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 164 1>, <0 165 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&clk25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { clock-names = "ref_clk", "pclk"; clocks = <&clkc 10>, <&clkc 43>; compatible = "xlnx,zynq-qspi-1.0"; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 19 4>; reg = <0xe000d000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,zynq-gem", "cdns,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dmac@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <4>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; interrupt-parent = <&intc>; interrupts = <0 8 4>; reg = <0xf8007000 0x100>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2022.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff990400 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; xlnx_aes: zynqmp-aes { compatible = "xlnx,zynqmp-aes"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; xlnx_keccak_384: sha384 { compatible = "xlnx,zynqmp-keccak-384"; }; xlnx_rsa: zynqmp-rsa { compatible = "xlnx,zynqmp-rsa"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; #dma-cells = <1>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "arm,mali-400", "arm,mali-utgard"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; #dma-cells = <1>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <0>; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; xlnx,device_id = <1>; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; /* snps,enable-hibernation; */ }; }; usb1: usb1@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-reset-on-resume; snps,xhci-stream-quirk; }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <2>; #size-cells = <2>; #io-channel-cells = <1>; ranges; ams_ps: ams_ps@ffa50800 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0xffa50800 0x0 0x400>; }; ams_pl: ams_pl@ffa50c00 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x0 0xffa50c00 0x0 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp_aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/ac701-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/ac701-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze ac701-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/kc705-full.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-full. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/kc705-lite.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kc705-lite. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105-tmr.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze kcu105-tmr. * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/kcu105.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* i * dts file for Xilinx Microblaze kcu105. * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/sp701-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze sp701. * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/vcu118-rev2.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx Microblaze vcu118 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-property/ pcs-handle ; /delete-property/ managed ; /delete-property/ xlnx,switch-x-sgmii ; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-emu-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-net-emu-1.9", "xlnx,versal-net-emu"; model = "Xilinx Versal NET EMU 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x10000000>; device_type = "memory"; }; aliases { serial0 = &serial0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh"; stdout-path = "serial0:115200"; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; clk1: clk1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; /* it doesn't matter on EMU */ }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET IPP/SPP OSPI * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-net-ipp-rev1.9.dtsi" / { model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; }; &ospi { status = "okay"; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; u-boot,dm-pre-reloc; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecc10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 139 1>, <0 140 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecd10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 143 1>, <0 144 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xece10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 147 1>, <0 148 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecf10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 164 1>, <0 165 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2) * * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ i2c-mux@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c@0 { #address-cells = <1>; #size-cells = <0>; qsfp56g_0: gpio@20 { /* u118 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_0_OC_B", "QSFP56G_0_PWR_EN", /* 0, 1 */ "QSFP56G_0_LED_1", "QSFP56G_0_LED_0", /* 2, 3 */ "QSFP56G_0_MODPRS_B", "QSFP56G_0_LPMODE", /* 4, 5 */ "QSFP56G_0_RESET_B", "QSFP56G_0_MODSEL_B"; /* 6, 7 */ }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; qsfp56g_1: gpio@20 { /* u117 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_1_OC_B", "QSFP56G_1_PWR_EN", /* 0, 1 */ "QSFP56G_1_LED_1", "QSFP56G_1_LED_0", /* 2, 3 */ "QSFP56G_1_MODPRS_B", "QSFP56G_1_LPMODE", /* 4, 5 */ "QSFP56G_1_RESET_B", "QSFP56G_1_MODSEL_B"; /* 6, 7 */ }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; /* J48 connector */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; /* J47 connector */ }; }; /* GPIO_DIP_SW0-1 GPIO_LED0-1 GPIO_PB0-1 GPIO_SMA */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) * * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "versal-net.dtsi" #include "versal-net-clk-ccf.dtsi" / { compatible = "xlnx,versal-net-vn-p-b2197-00-revA", "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; }; &i2c0 { /* Access via J70/J71 or J82/J83 */ clock-frequency = <100000>; }; &i2c1 { /* Access via J70/J71 or J82/J83 */ /* By default this bus should have eeprom for board identification at 0x54 */ /* SE/X-PRC card identification is also on this bus at 0x52 */ clock-frequency = <100000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <2>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { spi0 = &ospi; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>, <1>; stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" #include "include/dt-bindings/net/mscc-phy-vsc8531.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = ; vsc8531,tx-delay = ; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revA * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revA", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revB * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revB", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revB"; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* u198 - ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2000>; adi,tx-internal-delay-ps = <2000>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-virt.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Venkatesh Yadav Abbarapu */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; phy2: ethernet-phy@2 { /* u134 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; }; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <2>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; spi0 = &qspi; usb0 = &usb0; }; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb1; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "soft"; nand-ecc-algo = "bch"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 0>; sda-gpios = <&gpio0 51 0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 RevB * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PMBUS */ max20751@74 { /* u23 */ compatible = "maxim,max20751"; reg = <0x74>; }; max20751@70 { /* u89 */ compatible = "maxim,max20751"; reg = <0x70>; }; max15301@a { /* u28 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u48 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@d { /* u27 */ compatible = "maxim,max15303"; reg = <0xd>; }; max15303@e { /* u11 */ compatible = "maxim,max15303"; reg = <0xe>; }; max15303@f { /* u96 */ compatible = "maxim,max15303"; reg = <0xf>; }; max15303@11 { /* u47 */ compatible = "maxim,max15303"; reg = <0x11>; }; max15303@12 { /* u24 */ compatible = "maxim,max15303"; reg = <0x12>; }; max15301@13 { /* u29 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u51 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u30 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u102 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15301@17 { /* u50 */ compatible = "maxim,max15301"; reg = <0x17>; }; max15301@18 { /* u31 */ compatible = "maxim,max15301"; reg = <0x18>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CM_I2C */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYS_EEPROM */ eeprom: eeprom@54 { /* u101 */ compatible = "atmel,24c32"; /* 24LC32A */ reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FMC1 */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FMC2 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* ANALOG_PMBUS */ u60: ina226@40 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x40>; shunt-resistor = <1000>; }; u61: ina226@41 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x41>; shunt-resistor = <1000>; }; u63: ina226@42 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x42>; shunt-resistor = <1000>; }; u65: ina226@43 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x43>; shunt-resistor = <1000>; }; u64: ina226@44 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* ANALOG_CM_I2C */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FMC3 */ }; }; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zedboard.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Naga Sureshkumar Relli */ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; nvmem0 = &eeprom1; nvmem1 = &eeprom0; serial0 = &uart0; }; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x6c>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-e-a2197-00-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevB System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-e-a2197-00-reva.dtsi" / { model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; /delete-node/ ina226-vcco-500; /delete-node/ ina226-vcco-501; /delete-node/ ina226-vcco-502; }; &i2c0 { i2c-mux@74 { /* u33 */ i2c@2 { /* PCIE_CLK */ /delete-node/ clock-generator@6c; }; i2c@3 { /* PMBUS2_INA226 */ /delete-node/ ina226@42; /delete-node/ ina226@43; /delete-node/ ina226@44; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; usb0 = &usb0; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr_sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x60>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/net/ti-dp83867.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 1>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <100>; reset-deassert-us = <280>; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; }; &i2c1 { /* i2c1 MIO 24-25 */ u-boot,dm-pre-reloc; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x10000>; /* 256B but 64KB sector */ read-only; lock; }; partition@2250000 { label = "User"; reg = <0x2250000 0x1db0000>; /* 29.5 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &uart1 { /* uart0 MIO36-37 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "peripheral"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; &pinctrl0 { /* required by spec */ status = "okay"; pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; mux { groups = "uart1_9_grp"; function = "uart1"; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; power-source = ; }; mux { groups = "i2c1_6_grp"; function = "i2c1"; }; }; pinctrl_i2c1_gpio: i2c1-gpio { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; power-source = ; }; mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; }; pinctrl_gem1_default: gem1-default { conf { groups = "ethernet1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO44", "MIO46", "MIO48"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO45", "MIO47", "MIO49"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; low-power-enable; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; mux { function = "ethernet1"; groups = "ethernet1_0_grp"; }; }; pinctrl_usb0_default: usb0-default { conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; mux { groups = "usb0_0_grp"; function = "usb0"; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * Copyright (C) 2021-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sc-revb.dtsi" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ /delete-node/ mdio; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; adi,tx-internal-delay-ps = <2400>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revA * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; gtclk1_1: sys_clk_0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 0>; }; gtclk1_2: sys_clk_1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 1>; }; gtclk1_3: sys_clk_2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 2>; }; gtclk1_6: gtclk1_out6 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 3>; }; gtclk1_7: gtclk1_out7 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 4>; }; gtclk1_8: gtclk1_out8 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 5>; }; gtclk1_10: ps_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 6>; }; gtclk1_11: gtclk1_out11 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 7>; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir35215_46: pmic@46 { /* IR35215 - u152 */ compatible = "infineon,ir35215"; reg = <0x46>; /* i2c addr - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; irps5401_48: pmic@48 { /* IRPS5401 - u279 */ compatible = "infineon,irps5401"; reg = <0x48>; /* i2c addr 0x18 */ }; ir38064_49: regulator@49 { /* IR38064 - u295 */ compatible = "infineon,ir38064"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1d */ }; ir38060_4e: regulator@4e { /* IR38060 - u282 */ compatible = "infineon,ir38060"; reg = <0x4e>; /* i2c addr 0x1e */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* alerts coming to u233 and SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <500>; /* r440 */ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <500>; /* r1702 */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r382 */ }; vcc_ram: ina226@43 { /* u355 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2417 */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; /* r1830 */ }; vcc_psfp: ina226@45 { /* u260 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2386 */ }; vcco_hdio: ina226@46 { /* u356 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; /* r2392 */ }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* alerts coming to u233 and SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; /* r2384 */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; /* r2000 */ }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r1829 */ }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2397 */ }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2401 */ }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <500>; /* r1384 */ }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; /* r1994 */ }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; /* r2384 */ }; vcc1v1_lp4: ina226@49 { /* u306 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <500>; /* r2064 */ }; vadj_fmc: ina226@4a { /* u281 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; /* r2031 */ }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; /* r2004 */ }; lpdmgtyavtt: ina226@4c { /* u309 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; /* r1229 */ }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ }; }; i2c@4 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; rc21008a_gtclk1: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* connector j374 */ /* rc21008a at 0x9 u299 */ vc7: clock-generator@9 { compatible = "renesas,rc21008a"; reg = <0x9>; #clock-cells = <1>; clocks = <&vc7_xin>; clock-names = "xin"; }; }; fmcp1_iic: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* to j51c */ }; sfp: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* sfp+ connector J376 */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sc-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revB * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "zynqmp-sc-vek280-reva.dtsi" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SM-K24 RevA"; compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1db0000>; /* 29.5 MB */ }; }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k24-reva.dtsi" / { model = "ZynqMP SMK-K24 RevA"; compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; si570_user1_fmc_clk: si570_user1_fmc_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570_lpddr4_clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-versal-net-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_CLK_VERSAL_NET_H #define _DT_BINDINGS_CLK_VERSAL_NET_H #include #define GEM0_REF_RX 0xA9 #define GEM0_REF_TX 0xA8 #define GEM1_REF_RX 0xA2 #define GEM1_REF_TX 0xA1 #define CAN0_REF_2X 0x9E #define CAN1_REF_2X 0xAC #define FPD_WWDT 0x96 #define ACPU_0 0x98 #define ACPU_1 0x9B #define ACPU_2 0x9A #define ACPU_3 0x99 #define I3C0_REF 0x9D #define I3C1_REF 0x9F #define USB1_BUS_REF 0xAE /* Remove Versal specific node IDs */ #undef APU_PLL #undef RPU_PLL #undef CPM_PLL #undef APU_PRESRC #undef APU_POSTCLK #undef APU_PLL_OUT #undef APLL #undef RPU_PRESRC #undef RPU_POSTCLK #undef RPU_PLL_OUT #undef RPLL #undef CPM_PRESRC #undef CPM_POSTCLK #undef CPM_PLL_OUT #undef CPLL #undef APLL_TO_XPD #undef RPLL_TO_XPD #undef RCLK_PMC #undef RCLK_LPD #undef WDT #undef MUXED_IRO_DIV2 #undef MUXED_IRO_DIV4 #undef PSM_REF #undef CPM_CORE_REF #undef CPM_LSBUS_REF #undef CPM_DBG_REF #undef CPM_AUX0_REF #undef CPM_AUX1_REF #undef CPU_R5 #undef CPU_R5_CORE #undef CPU_R5_OCM #undef CPU_R5_OCM2 #undef CAN0_REF #undef CAN1_REF #undef I2C0_REF #undef I2C1_REF #undef CPM_TOPSW_REF #undef USB3_DUAL_REF #undef MUXED_IRO #undef PL_EXT #undef PL_LB #undef MIO_50_OR_51 #undef MIO_24_OR_25 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/net/mscc-phy-vsc8531.h ================================================ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Device Tree constants for Microsemi VSC8531 PHY * * Author: Nagaraju Lakkaraju * * Copyright (c) 2017 Microsemi Corporation */ #ifndef _DT_BINDINGS_MSCC_VSC8531_H #define _DT_BINDINGS_MSCC_VSC8531_H /* PHY LED Modes */ #define VSC8531_LINK_ACTIVITY 0 #define VSC8531_LINK_1000_ACTIVITY 1 #define VSC8531_LINK_100_ACTIVITY 2 #define VSC8531_LINK_10_ACTIVITY 3 #define VSC8531_LINK_100_1000_ACTIVITY 4 #define VSC8531_LINK_10_1000_ACTIVITY 5 #define VSC8531_LINK_10_100_ACTIVITY 6 #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 #define VSC8531_DUPLEX_COLLISION 8 #define VSC8531_COLLISION 9 #define VSC8531_ACTIVITY 10 #define VSC8584_100FX_1000X_ACTIVITY 11 #define VSC8531_AUTONEG_FAULT 12 #define VSC8531_SERIAL_MODE 13 #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-net-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H #define _DT_BINDINGS_VERSAL_NET_POWER_H #include #define PM_DEV_USB_1 (0x182240D7U) #define PM_DEV_FPD_SWDT_0 (0x182240DBU) #define PM_DEV_FPD_SWDT_1 (0x182240DCU) #define PM_DEV_FPD_SWDT_2 (0x182240DDU) #define PM_DEV_FPD_SWDT_3 (0x182240DEU) /* Remove Versal specific node IDs */ #undef PM_DEV_RPU0_0 #undef PM_DEV_RPU0_1 #undef PM_DEV_OCM_0 #undef PM_DEV_OCM_1 #undef PM_DEV_OCM_2 #undef PM_DEV_OCM_3 #undef PM_DEV_TCM_0_A #undef PM_DEV_TCM_1_A #undef PM_DEV_TCM_0_B #undef PM_DEV_TCM_1_B #undef PM_DEV_SWDT_FPD #undef PM_DEV_AI #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-versal-regnode.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H #define _DT_BINDINGS_VERSAL_REGNODE_H #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-net-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H #define _DT_BINDINGS_VERSAL_NET_RESETS_H #include "xlnx-versal-resets.h" #define VERSAL_RST_USB_1 (0xC1040C6U) /* Remove Versal specific reset IDs */ #undef VERSAL_RST_ACPU_0_POR #undef VERSAL_RST_ACPU_1_POR #undef VERSAL_RST_OCM2_POR #undef VERSAL_RST_APU #undef VERSAL_RST_ACPU_0 #undef VERSAL_RST_ACPU_1 #undef VERSAL_RST_ACPU_L2 #undef VERSAL_RST_RPU_ISLAND #undef VERSAL_RST_RPU_AMBA #undef VERSAL_RST_R5_0 #undef VERSAL_RST_R5_1 #undef VERSAL_RST_OCM2_RST #undef VERSAL_RST_I2C_PMC #undef VERSAL_RST_I2C_0 #undef VERSAL_RST_I2C_1 #undef VERSAL_RST_SWDT_FPD #undef VERSAL_RST_SWDT_LPD #undef VERSAL_RST_USB #undef VERSAL_RST_DPC #undef VERSAL_RST_DBG_TRACE #undef VERSAL_RST_DBG_TSTMP #undef VERSAL_RST_RPU0_DBG #undef VERSAL_RST_RPU1_DBG #undef VERSAL_RST_HSDP #undef VERSAL_RST_CPMDBG #undef VERSAL_RST_PCIE_CFG #undef VERSAL_RST_PCIE_CORE0 #undef VERSAL_RST_PCIE_CORE1 #undef VERSAL_RST_PCIE_DMA #undef VERSAL_RST_L2_0 #undef VERSAL_RST_L2_1 #undef VERSAL_RST_ADDR_REMAP #undef VERSAL_RST_CPI0 #undef VERSAL_RST_CPI1 #undef VERSAL_RST_XRAM #undef VERSAL_RST_AIE_ARRAY #undef VERSAL_RST_AIE_SHIM #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-versal-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H #define _DT_BINDINGS_VERSAL_RESETS_H #define VERSAL_RST_PMC_POR (0xc30c001U) #define VERSAL_RST_PMC (0xc410002U) #define VERSAL_RST_PS_POR (0xc30c003U) #define VERSAL_RST_PL_POR (0xc30c004U) #define VERSAL_RST_NOC_POR (0xc30c005U) #define VERSAL_RST_FPD_POR (0xc30c006U) #define VERSAL_RST_ACPU_0_POR (0xc30c007U) #define VERSAL_RST_ACPU_1_POR (0xc30c008U) #define VERSAL_RST_OCM2_POR (0xc30c009U) #define VERSAL_RST_PS_SRST (0xc41000aU) #define VERSAL_RST_PL_SRST (0xc41000bU) #define VERSAL_RST_NOC (0xc41000cU) #define VERSAL_RST_NPI (0xc41000dU) #define VERSAL_RST_SYS_RST_1 (0xc41000eU) #define VERSAL_RST_SYS_RST_2 (0xc41000fU) #define VERSAL_RST_SYS_RST_3 (0xc410010U) #define VERSAL_RST_FPD (0xc410011U) #define VERSAL_RST_PL0 (0xc410012U) #define VERSAL_RST_PL1 (0xc410013U) #define VERSAL_RST_PL2 (0xc410014U) #define VERSAL_RST_PL3 (0xc410015U) #define VERSAL_RST_APU (0xc410016U) #define VERSAL_RST_ACPU_0 (0xc410017U) #define VERSAL_RST_ACPU_1 (0xc410018U) #define VERSAL_RST_ACPU_L2 (0xc410019U) #define VERSAL_RST_ACPU_GIC (0xc41001aU) #define VERSAL_RST_RPU_ISLAND (0xc41001bU) #define VERSAL_RST_RPU_AMBA (0xc41001cU) #define VERSAL_RST_R5_0 (0xc41001dU) #define VERSAL_RST_R5_1 (0xc41001eU) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) #define VERSAL_RST_SYSMON_LPD (0xc410023U) #define VERSAL_RST_PDMA_RST1 (0xc410024U) #define VERSAL_RST_PDMA_RST0 (0xc410025U) #define VERSAL_RST_ADMA (0xc410026U) #define VERSAL_RST_TIMESTAMP (0xc410027U) #define VERSAL_RST_OCM (0xc410028U) #define VERSAL_RST_OCM2_RST (0xc410029U) #define VERSAL_RST_IPI (0xc41002aU) #define VERSAL_RST_SBI (0xc41002bU) #define VERSAL_RST_LPD (0xc41002cU) #define VERSAL_RST_QSPI (0xc10402dU) #define VERSAL_RST_OSPI (0xc10402eU) #define VERSAL_RST_SDIO_0 (0xc10402fU) #define VERSAL_RST_SDIO_1 (0xc104030U) #define VERSAL_RST_I2C_PMC (0xc104031U) #define VERSAL_RST_GPIO_PMC (0xc104032U) #define VERSAL_RST_GEM_0 (0xc104033U) #define VERSAL_RST_GEM_1 (0xc104034U) #define VERSAL_RST_SPARE (0xc104035U) #define VERSAL_RST_USB_0 (0xc104036U) #define VERSAL_RST_UART_0 (0xc104037U) #define VERSAL_RST_UART_1 (0xc104038U) #define VERSAL_RST_SPI_0 (0xc104039U) #define VERSAL_RST_SPI_1 (0xc10403aU) #define VERSAL_RST_CAN_FD_0 (0xc10403bU) #define VERSAL_RST_CAN_FD_1 (0xc10403cU) #define VERSAL_RST_I2C_0 (0xc10403dU) #define VERSAL_RST_I2C_1 (0xc10403eU) #define VERSAL_RST_GPIO_LPD (0xc10403fU) #define VERSAL_RST_TTC_0 (0xc104040U) #define VERSAL_RST_TTC_1 (0xc104041U) #define VERSAL_RST_TTC_2 (0xc104042U) #define VERSAL_RST_TTC_3 (0xc104043U) #define VERSAL_RST_SWDT_FPD (0xc104044U) #define VERSAL_RST_SWDT_LPD (0xc104045U) #define VERSAL_RST_USB (0xc104046U) #define VERSAL_RST_DPC (0xc208047U) #define VERSAL_RST_PMCDBG (0xc208048U) #define VERSAL_RST_DBG_TRACE (0xc208049U) #define VERSAL_RST_DBG_FPD (0xc20804aU) #define VERSAL_RST_DBG_TSTMP (0xc20804bU) #define VERSAL_RST_RPU0_DBG (0xc20804cU) #define VERSAL_RST_RPU1_DBG (0xc20804dU) #define VERSAL_RST_HSDP (0xc20804eU) #define VERSAL_RST_DBG_LPD (0xc20804fU) #define VERSAL_RST_CPM_POR (0xc30c050U) #define VERSAL_RST_CPM (0xc410051U) #define VERSAL_RST_CPMDBG (0xc208052U) #define VERSAL_RST_PCIE_CFG (0xc410053U) #define VERSAL_RST_PCIE_CORE0 (0xc410054U) #define VERSAL_RST_PCIE_CORE1 (0xc410055U) #define VERSAL_RST_PCIE_DMA (0xc410056U) #define VERSAL_RST_CMN (0xc410057U) #define VERSAL_RST_L2_0 (0xc410058U) #define VERSAL_RST_L2_1 (0xc410059U) #define VERSAL_RST_ADDR_REMAP (0xc41005aU) #define VERSAL_RST_CPI0 (0xc41005bU) #define VERSAL_RST_CPI1 (0xc41005cU) #define VERSAL_RST_XRAM (0xc30c05dU) #define VERSAL_RST_AIE_ARRAY (0xc10405eU) #define VERSAL_RST_AIE_SHIM (0xc10405fU) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" #include "include/dt-bindings/power/xlnx-versal-regnode.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_reset: reset-controller { compatible = "xlnx,versal-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,versal-pinctrl"; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; resets = <&versal_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_clk USB0_BUS_REF>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; &sysmon0 { xlnx,nodeid = ; }; &sysmon1 { xlnx,nodeid = ; }; &sysmon2 { xlnx,nodeid = ; }; &sysmon3 { xlnx,nodeid = ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal_fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; status = "disabled"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupts = <0 10 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xC0000000>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: pci-interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 0x64 1>, <0 0x6D 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; xilsem_edac: edac@f2014050 { compatible = "xlnx,versal-xilsem-edac"; status = "disabled"; reg = <0x0 0xf2014050 0x0 0xc4>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN0_REF_2X>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN1_REF_2X>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; versal_net_power: zynqmp-power { /* untested */ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_sec_cfg: versal-sec-cfg { /* untested */ compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_net_clk ACPU_0>; }; &cpu100 { clocks = <&versal_net_clk ACPU_0>; }; &cpu200 { clocks = <&versal_net_clk ACPU_0>; }; &cpu300 { clocks = <&versal_net_clk ACPU_0>; }; &cpu10000 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10100 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10200 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10300 { clocks = <&versal_net_clk ACPU_1>; }; &cpu20000 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20100 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20200 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20300 { clocks = <&versal_net_clk ACPU_2>; }; &cpu30000 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30100 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30200 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30300 { clocks = <&versal_net_clk ACPU_3>; }; &can0 { clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &adma0 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; &adma1 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; &adma2 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; &adma3 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; &adma4 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; &adma5 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; &adma6 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; &adma7 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_net_clk OSPI_REF>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET fixed clock * * (C) Copyright 2022, Xilinx, Inc. * * Michal Simek */ #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk150: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; clk160: clk160 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <160000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk450: clk450 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <450000000>; }; clk1200: clk1200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1200000000>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; u-boot,dm-pre-reloc; method = "smc"; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; }; }; &adma0 { clocks = <&clk450>, <&clk450>; }; &adma1 { clocks = <&clk450>, <&clk450>; }; &adma2 { clocks = <&clk450>, <&clk450>; }; &adma3 { clocks = <&clk450>, <&clk450>; }; &adma4 { clocks = <&clk450>, <&clk450>; }; &adma5 { clocks = <&clk450>, <&clk450>; }; &adma6 { clocks = <&clk450>, <&clk450>; }; &adma7 { clocks = <&clk450>, <&clk450>; }; &can0 { clocks = <&clk160>, <&clk160>; }; &can1 { clocks = <&clk160>, <&clk160>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gpio0 { clocks = <&clk100>; }; &gpio1 { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &i3c0 { clocks = <&clk100>; }; &i3c1 { clocks = <&clk100>; }; &ospi { clocks = <&clk200>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &qspi { clocks = <&clk300>, <&clk300>; }; &rtc { /* Nothing */ }; &sdhci0 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &sdhci1 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &serial0 { clocks = <&clk100>, <&clk100>; clock = <1000000>; }; &serial1 { clocks = <&clk100>, <&clk100>; clock = <100000000>; }; &spi0 { clocks = <&clk200>, <&clk200>; }; &spi1 { clocks = <&clk200>, <&clk200>; }; &ttc0 { clocks = <&clk150>; }; &usb0 { clocks = <&clk60>, <&clk60>; }; &dwc3_0 { /* Nothing */ }; &usb1 { clocks = <&clk60>, <&clk60>; }; &dwc3_1 { /* Nothing */ }; &wwdt0 { clocks = <&clk150>; }; &wwdt1 { clocks = <&clk150>; }; &wwdt2 { clocks = <&clk150>; }; &wwdt3 { clocks = <&clk150>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; u-boot,dm-pre-reloc; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <1>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,refclk_fladj; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecc10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 139 1>, <0 140 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecd10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 143 1>, <0 144 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xece10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 147 1>, <0 148 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt-1.0"; reg = <0 0xecf10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 164 1>, <0 165 1>; timeout-sec = <30>; pretimeout-sec = <25>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/versal-net/versal-net.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net"; model = "Xilinx Versal NET"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; cluster2 { core0 { cpu = <&cpu20000>; }; core1 { cpu = <&cpu20100>; }; core2 { cpu = <&cpu20200>; }; core3 { cpu = <&cpu20300>; }; }; cluster3 { core0 { cpu = <&cpu30000>; }; core1 { cpu = <&cpu30100>; }; core2 { cpu = <&cpu30200>; }; core3 { cpu = <&cpu30300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; operating-points-v2 = <&cpu_opp_table>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-1066000000 { opp-hz = /bits/ 64 <1066000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1866000000 { opp-hz = /bits/ 64 <1866000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1999000000 { opp-hz = /bits/ 64 <1999000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2050000000 { opp-hz = /bits/ 64 <2050000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2100000000 { opp-hz = /bits/ 64 <2100000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2200000000 { opp-hz = /bits/ 64 <2200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; i2c0 = &i2c0; i2c1 = &i2c1; rtc = &rtc; usb0 = &usb0; usb1 = &usb1; spi0 = &ospi; spi1 = &qspi; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; #address-cells = <2>; #size-cells = <2>; ranges; its: gic-its@e2040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0xe2040000 0 0x20000>; }; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 20 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 180 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i3c0: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 21 4>; }; i3c1: i3c-master@f1958000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1958000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 22 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; /* u-boot specific */ /* cdns,is-stig-pgm = <1>; - unused - checking with Sai */ cdns,trigger-address = <0xc0000000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */ interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-net-5.1-emmc", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; serial1: serial@f1930000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; smmu: iommu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; dma-coherent; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; }; ttc1: timer@f1dd0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; timer-width = <32>; reg = <0x0 0xf1dd0000 0x0 0x1000>; }; ttc2: timer@f1de0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 49 4>, <0 50 4>, <0 51 4>; timer-width = <32>; reg = <0x0 0xf1de0000 0x0 0x1000>; }; ttc3: timer@f1df0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 52 4>, <0 53 4>, <0 54 4>; timer-width = <32>; reg = <0x0 0xf1df0000 0x0 0x1000>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; /*phy-names = "usb3-phy";- checking with Pyiush */ }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; /* phy-names = "usb3-phy"; - checking with Pyiush */ }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xecc10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 139 1>, <0 140 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xecd10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 143 1>, <0 144 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xece10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 147 1>, <0 148 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt-1.0"; status = "disabled"; reg = <0 0xecf10000 0 0x10000>; interrupt-names = "wdt", "wwdt_reset_pending"; interrupts = <0 164 1>, <0 165 1>; timeout-sec = <30>; pretimeout-sec = <25>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/zynq/skeleton.dtsi ================================================ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { compatible = "xlnx,zynq-qspi-1.0"; reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; clocks = <&clkc 10>, <&clkc 43>; clock-names = "ref_clk", "pclk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; /* * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", * "dma4", "dma5", "dma6", "dma7"; */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; dp_aclk: dp_aclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_pcap { clocks = <&zynqmp_clk PCAP>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp_ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem_firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse_dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse_usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse_usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse_usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse_usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse_usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse_usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse_usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse_usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse_miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse_chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse_pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse_sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse_spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse_ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse_ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; clock-names = "ref_clk"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; }; usb1: usb@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; reg-names = "ams-base"; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; ams_ps: ams_ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; ams_pl: ams_pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp_aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp_dp_snd_card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/ac701-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/kc705-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105-tmr.dtsi ================================================ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/kcu105.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/sp701-rev1.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/vcu118-rev2.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-property/ pcs-handle ; /delete-property/ managed ; /delete-property/ xlnx,switch-x-sgmii ; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &uart1 { /* uart1 MIO40-41 */ u-boot,dm-pre-reloc; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-emu-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-net-emu-1.9", "xlnx,versal-net-emu"; model = "Xilinx Versal NET EMU 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x10000000>; device_type = "memory"; }; aliases { serial0 = &serial0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh"; stdout-path = "serial0:115200"; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; clk1: clk1 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; /* it doesn't matter on EMU */ }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET IPP/SPP OSPI * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-net-ipp-rev1.9.dtsi" / { model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; }; &ospi { status = "okay"; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref-clk { compatible = "fixed-clock"; u-boot,dm-pre-reloc; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; no-wp; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2) * * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ i2c-mux@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c@0 { #address-cells = <1>; #size-cells = <0>; qsfp56g_0: gpio@20 { /* u118 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_0_OC_B", "QSFP56G_0_PWR_EN", /* 0, 1 */ "QSFP56G_0_LED_1", "QSFP56G_0_LED_0", /* 2, 3 */ "QSFP56G_0_MODPRS_B", "QSFP56G_0_LPMODE", /* 4, 5 */ "QSFP56G_0_RESET_B", "QSFP56G_0_MODSEL_B"; /* 6, 7 */ }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; qsfp56g_1: gpio@20 { /* u117 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_1_OC_B", "QSFP56G_1_PWR_EN", /* 0, 1 */ "QSFP56G_1_LED_1", "QSFP56G_1_LED_0", /* 2, 3 */ "QSFP56G_1_MODPRS_B", "QSFP56G_1_LPMODE", /* 4, 5 */ "QSFP56G_1_RESET_B", "QSFP56G_1_MODSEL_B"; /* 6, 7 */ }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; /* J48 connector */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; /* J47 connector */ }; }; /* GPIO_DIP_SW0-1 GPIO_LED0-1 GPIO_PB0-1 GPIO_SMA */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) * * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net-vn-p-b2197-00-revA", "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; }; &i2c0 { /* Access via J70/J71 or J82/J83 */ clock-frequency = <100000>; }; &i2c1 { /* Access via J70/J71 or J82/J83 */ /* By default this bus should have eeprom for board identification at 0x54 */ /* SE/X-PRC card identification is also on this bus at 0x52 */ clock-frequency = <100000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-net-vn-x-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal Net VNX board * * (C) Copyright 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-net-vn-x-b2197-00-revA", "xlnx,versal-net-vn-x-b2197-00", "xlnx,versal-net"; model = "Xilinx Versal Net VNX"; aliases { nvmem0 = &eeprom0; }; }; &adma0 { status = "okay"; }; &adma1 { status = "okay"; }; &adma2 { status = "okay"; }; &adma3 { status = "okay"; }; &adma4 { status = "okay"; }; &adma5 { status = "okay"; }; &adma6 { status = "okay"; }; &adma7 { status = "okay"; }; &lpd_wwdt0 { status = "okay"; }; &gem1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy>; phy-mode = "rmii"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy { reg = <4>; }; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; eeprom0: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; u-boot,dm-pre-reloc; }; }; &i2c1 { status = "okay"; eeprom1: eeprom@55 { compatible = "st,24c128", "atmel,24c128"; reg = <0x55>; u-boot,dm-pre-reloc; }; }; &ospi { status = "okay"; is-dual = <0>; is-stacked = <1>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; reset-names = "qspi"; #address-cells = <1>; #size-cells = <0>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x8000000>; }; }; }; }; &sdhci1 { status = "okay"; non-removable; disable-wp; bus-width = <8>; no-1-8-v; }; &serial0 { status = "okay"; }; &serial1 { status = "okay"; }; &spi1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; num-cs = <3>; }; &usb1 { status = "okay"; }; &dwc3_1 { status = "okay"; snps,refclk_fladj; snps,mask_phy_reset; phy-names = "usb3-phy"; }; &wwdt0 { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <2>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { spi0 = &ospi; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ phy1: phy@1 { reg = <2>; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; is-dual = <0>; is-stacked = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>, <1>; stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" #include "include/dt-bindings/net/mscc-phy-vsc8531.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; vsc8531,rx-delay = ; vsc8531,tx-delay = ; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; aliases { serial2 = &dcc; }; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revA * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revA", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revB * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revB", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revB"; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* u198 - ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2000>; adi,tx-internal-delay-ps = <2000>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-virt.dtsi ================================================ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; phy2: ethernet-phy@2 { /* u134 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; }; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <2>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; is-dual = <1>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; spi0 = &qspi; usb0 = &usb0; }; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb1; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ #include / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <1>; num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-reva.dtsi ================================================ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-revb.dtsi ================================================ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { is-dual = <1>; num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zedboard.dtsi ================================================ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { u-boot,dm-pre-reloc; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { u-boot,dm-pre-reloc; }; &uart1 { u-boot,dm-pre-reloc; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; nvmem0 = &eeprom1; nvmem1 = &eeprom0; serial0 = &uart0; }; }; &i2c0 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; u-boot,dm-pre-reloc; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; u-boot,dm-pre-reloc; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570_ddrdimm1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570_hsdp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570_zsfp_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570_user1_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; clock_8t49n287: clock-generator@6c { /* u39 8T49N240 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x6c>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-e-a2197-00-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevB System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-e-a2197-00-reva.dtsi" / { model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; /delete-node/ ina226-vcco-500; /delete-node/ ina226-vcco-501; /delete-node/ ina226-vcco-502; }; &i2c0 { i2c-mux@74 { /* u33 */ i2c@2 { /* PCIE_CLK */ /delete-node/ clock-generator@6c; }; i2c@3 { /* PMBUS2_INA226 */ /delete-node/ ina226@42; /delete-node/ ina226@43; /delete-node/ ina226@44; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; usb0 = &usb0; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { is-dual = <1>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; }; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0x60>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/net/ti-dp83867.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 1>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <100>; reset-deassert-us = <280>; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { /* i2c1 MIO 24-25 */ u-boot,dm-pre-reloc; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ u-boot,dm-pre-reloc; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "mt25qu512a", "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &uart1 { /* uart0 MIO36-37 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { /* required by spec */ status = "okay"; pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; mux { groups = "uart1_9_grp"; function = "uart1"; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; power-source = ; }; mux { groups = "i2c1_6_grp"; function = "i2c1"; }; }; pinctrl_i2c1_gpio: i2c1-gpio { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; power-source = ; }; mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; }; pinctrl_gem1_default: gem1-default { conf { groups = "ethernet1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO44", "MIO46", "MIO48"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO45", "MIO47", "MIO49"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; low-power-enable; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; mux { function = "ethernet1"; groups = "ethernet1_0_grp"; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * Copyright (C) 2021-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sc-revb.dtsi" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ /delete-node/ mdio; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; adi,tx-internal-delay-ps = <2400>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revA * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; gtclk1_1: sys_clk_0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 0>; }; gtclk1_2: sys_clk_1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 1>; }; gtclk1_3: sys_clk_2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 2>; }; gtclk1_6: gtclk1_out6 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 3>; }; gtclk1_7: gtclk1_out7 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 4>; }; gtclk1_8: gtclk1_out8 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 5>; }; gtclk1_10: ps_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 6>; }; gtclk1_11: gtclk1_out11 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 7>; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir35215_46: pmic@46 { /* IR35215 - u152 */ compatible = "infineon,ir35215"; reg = <0x46>; /* i2c addr - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; irps5401_48: pmic@48 { /* IRPS5401 - u279 */ compatible = "infineon,irps5401"; reg = <0x48>; /* i2c addr 0x18 */ }; ir38064_49: regulator@49 { /* IR38064 - u295 */ compatible = "infineon,ir38064"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1d */ }; ir38060_4e: regulator@4e { /* IR38060 - u282 */ compatible = "infineon,ir38060"; reg = <0x4e>; /* i2c addr 0x1e */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* alerts coming to u233 and SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <500>; /* r440 */ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <500>; /* r1702 */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r382 */ }; vcc_ram: ina226@43 { /* u355 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2417 */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; /* r1830 */ }; vcc_psfp: ina226@45 { /* u260 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2386 */ }; vcco_hdio: ina226@46 { /* u356 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; /* r2392 */ }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* alerts coming to u233 and SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; /* r2384 */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; /* r2000 */ }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r1829 */ }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2397 */ }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2401 */ }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <500>; /* r1384 */ }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; /* r1994 */ }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; /* r2384 */ }; vcc1v1_lp4: ina226@49 { /* u306 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <500>; /* r2064 */ }; vadj_fmc: ina226@4a { /* u281 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; /* r2031 */ }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; /* r2004 */ }; lpdmgtyavtt: ina226@4c { /* u309 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; /* r1229 */ }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ }; }; i2c@4 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; rc21008a_gtclk1: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* connector j374 */ /* rc21008a at 0x9 u299 */ vc7: clock-generator@9 { compatible = "renesas,rc21008a"; reg = <0x9>; #clock-cells = <1>; clocks = <&vc7_xin>; clock-names = "xin"; }; }; fmcp1_iic: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* to j51c */ }; sfp: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* sfp+ connector J376 */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sc-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revB * * (C) Copyright 2022, Advanced Micro Devices, Inc * * Michal Simek */ #include "zynqmp-sc-vek280-reva.dtsi" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SM-K24 RevA/B/1"; compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pmu_region: pmu@7ff00000 { reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { u-boot,dm-pre-reloc; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ u-boot,dm-pre-reloc; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k24-reva.dtsi" / { model = "ZynqMP SMK-K24 RevA"; compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; si570_user1_fmc_clk: si570_user1_fmc_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570_ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570_lpddr4_clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570_lpddr4_clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570_lpddr4_clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ u-boot,dm-pre-reloc; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-versal-net-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_CLK_VERSAL_NET_H #define _DT_BINDINGS_CLK_VERSAL_NET_H #include #define GEM0_REF_RX 0xA9 #define GEM0_REF_TX 0xA8 #define GEM1_REF_RX 0xA2 #define GEM1_REF_TX 0xA1 #define CAN0_REF_2X 0x9E #define CAN1_REF_2X 0xAC #define FPD_WWDT 0x96 #define ACPU_0 0x98 #define ACPU_1 0x9B #define ACPU_2 0x9A #define ACPU_3 0x99 #define I3C0_REF 0x9D #define I3C1_REF 0x9F #define USB1_BUS_REF 0xAE #define LPD_WWDT 0xAD /* Remove Versal specific node IDs */ #undef APU_PLL #undef RPU_PLL #undef CPM_PLL #undef APU_PRESRC #undef APU_POSTCLK #undef APU_PLL_OUT #undef APLL #undef RPU_PRESRC #undef RPU_POSTCLK #undef RPU_PLL_OUT #undef RPLL #undef CPM_PRESRC #undef CPM_POSTCLK #undef CPM_PLL_OUT #undef CPLL #undef APLL_TO_XPD #undef RPLL_TO_XPD #undef RCLK_PMC #undef RCLK_LPD #undef WDT #undef MUXED_IRO_DIV2 #undef MUXED_IRO_DIV4 #undef PSM_REF #undef CPM_CORE_REF #undef CPM_LSBUS_REF #undef CPM_DBG_REF #undef CPM_AUX0_REF #undef CPM_AUX1_REF #undef CPU_R5 #undef CPU_R5_CORE #undef CPU_R5_OCM #undef CPU_R5_OCM2 #undef CAN0_REF #undef CAN1_REF #undef I2C0_REF #undef I2C1_REF #undef CPM_TOPSW_REF #undef USB3_DUAL_REF #undef MUXED_IRO #undef PL_EXT #undef PL_LB #undef MIO_50_OR_51 #undef MIO_24_OR_25 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/net/mscc-phy-vsc8531.h ================================================ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Device Tree constants for Microsemi VSC8531 PHY * * Author: Nagaraju Lakkaraju * * Copyright (c) 2017 Microsemi Corporation */ #ifndef _DT_BINDINGS_MSCC_VSC8531_H #define _DT_BINDINGS_MSCC_VSC8531_H /* PHY LED Modes */ #define VSC8531_LINK_ACTIVITY 0 #define VSC8531_LINK_1000_ACTIVITY 1 #define VSC8531_LINK_100_ACTIVITY 2 #define VSC8531_LINK_10_ACTIVITY 3 #define VSC8531_LINK_100_1000_ACTIVITY 4 #define VSC8531_LINK_10_1000_ACTIVITY 5 #define VSC8531_LINK_10_100_ACTIVITY 6 #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 #define VSC8531_DUPLEX_COLLISION 8 #define VSC8531_COLLISION 9 #define VSC8531_ACTIVITY 10 #define VSC8584_100FX_1000X_ACTIVITY 11 #define VSC8531_AUTONEG_FAULT 12 #define VSC8531_SERIAL_MODE 13 #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-net-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H #define _DT_BINDINGS_VERSAL_NET_POWER_H #include #define PM_DEV_USB_1 (0x182240D7U) #define PM_DEV_FPD_SWDT_0 (0x182240DBU) #define PM_DEV_FPD_SWDT_1 (0x182240DCU) #define PM_DEV_FPD_SWDT_2 (0x182240DDU) #define PM_DEV_FPD_SWDT_3 (0x182240DEU) #define PM_DEV_TCM_A_0A (0x183180CBU) #define PM_DEV_TCM_A_0B (0x183180CCU) #define PM_DEV_TCM_A_0C (0x183180CDU) #define PM_DEV_RPU_A_0 (0x181100BFU) #define PM_DEV_LPD_SWDT_0 (0x182240D9U) #define PM_DEV_LPD_SWDT_1 (0x182240DAU) /* Remove Versal specific node IDs */ #undef PM_DEV_RPU0_0 #undef PM_DEV_RPU0_1 #undef PM_DEV_OCM_0 #undef PM_DEV_OCM_1 #undef PM_DEV_OCM_2 #undef PM_DEV_OCM_3 #undef PM_DEV_TCM_0_A #undef PM_DEV_TCM_1_A #undef PM_DEV_TCM_0_B #undef PM_DEV_TCM_1_B #undef PM_DEV_SWDT_FPD #undef PM_DEV_AI #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-versal-regnode.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H #define _DT_BINDINGS_VERSAL_REGNODE_H #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-versal-net-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H #define _DT_BINDINGS_VERSAL_NET_RESETS_H #include "xlnx-versal-resets.h" #define VERSAL_RST_USB_1 (0xC1040C6U) /* Remove Versal specific reset IDs */ #undef VERSAL_RST_ACPU_0_POR #undef VERSAL_RST_ACPU_1_POR #undef VERSAL_RST_OCM2_POR #undef VERSAL_RST_APU #undef VERSAL_RST_ACPU_0 #undef VERSAL_RST_ACPU_1 #undef VERSAL_RST_ACPU_L2 #undef VERSAL_RST_RPU_ISLAND #undef VERSAL_RST_RPU_AMBA #undef VERSAL_RST_R5_0 #undef VERSAL_RST_R5_1 #undef VERSAL_RST_OCM2_RST #undef VERSAL_RST_I2C_PMC #undef VERSAL_RST_I2C_0 #undef VERSAL_RST_I2C_1 #undef VERSAL_RST_SWDT_FPD #undef VERSAL_RST_SWDT_LPD #undef VERSAL_RST_USB #undef VERSAL_RST_DPC #undef VERSAL_RST_DBG_TRACE #undef VERSAL_RST_DBG_TSTMP #undef VERSAL_RST_RPU0_DBG #undef VERSAL_RST_RPU1_DBG #undef VERSAL_RST_HSDP #undef VERSAL_RST_CPMDBG #undef VERSAL_RST_PCIE_CFG #undef VERSAL_RST_PCIE_CORE0 #undef VERSAL_RST_PCIE_CORE1 #undef VERSAL_RST_PCIE_DMA #undef VERSAL_RST_L2_0 #undef VERSAL_RST_L2_1 #undef VERSAL_RST_ADDR_REMAP #undef VERSAL_RST_CPI0 #undef VERSAL_RST_CPI1 #undef VERSAL_RST_XRAM #undef VERSAL_RST_AIE_ARRAY #undef VERSAL_RST_AIE_SHIM #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-versal-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H #define _DT_BINDINGS_VERSAL_RESETS_H #define VERSAL_RST_PMC_POR (0xc30c001U) #define VERSAL_RST_PMC (0xc410002U) #define VERSAL_RST_PS_POR (0xc30c003U) #define VERSAL_RST_PL_POR (0xc30c004U) #define VERSAL_RST_NOC_POR (0xc30c005U) #define VERSAL_RST_FPD_POR (0xc30c006U) #define VERSAL_RST_ACPU_0_POR (0xc30c007U) #define VERSAL_RST_ACPU_1_POR (0xc30c008U) #define VERSAL_RST_OCM2_POR (0xc30c009U) #define VERSAL_RST_PS_SRST (0xc41000aU) #define VERSAL_RST_PL_SRST (0xc41000bU) #define VERSAL_RST_NOC (0xc41000cU) #define VERSAL_RST_NPI (0xc41000dU) #define VERSAL_RST_SYS_RST_1 (0xc41000eU) #define VERSAL_RST_SYS_RST_2 (0xc41000fU) #define VERSAL_RST_SYS_RST_3 (0xc410010U) #define VERSAL_RST_FPD (0xc410011U) #define VERSAL_RST_PL0 (0xc410012U) #define VERSAL_RST_PL1 (0xc410013U) #define VERSAL_RST_PL2 (0xc410014U) #define VERSAL_RST_PL3 (0xc410015U) #define VERSAL_RST_APU (0xc410016U) #define VERSAL_RST_ACPU_0 (0xc410017U) #define VERSAL_RST_ACPU_1 (0xc410018U) #define VERSAL_RST_ACPU_L2 (0xc410019U) #define VERSAL_RST_ACPU_GIC (0xc41001aU) #define VERSAL_RST_RPU_ISLAND (0xc41001bU) #define VERSAL_RST_RPU_AMBA (0xc41001cU) #define VERSAL_RST_R5_0 (0xc41001dU) #define VERSAL_RST_R5_1 (0xc41001eU) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) #define VERSAL_RST_SYSMON_LPD (0xc410023U) #define VERSAL_RST_PDMA_RST1 (0xc410024U) #define VERSAL_RST_PDMA_RST0 (0xc410025U) #define VERSAL_RST_ADMA (0xc410026U) #define VERSAL_RST_TIMESTAMP (0xc410027U) #define VERSAL_RST_OCM (0xc410028U) #define VERSAL_RST_OCM2_RST (0xc410029U) #define VERSAL_RST_IPI (0xc41002aU) #define VERSAL_RST_SBI (0xc41002bU) #define VERSAL_RST_LPD (0xc41002cU) #define VERSAL_RST_QSPI (0xc10402dU) #define VERSAL_RST_OSPI (0xc10402eU) #define VERSAL_RST_SDIO_0 (0xc10402fU) #define VERSAL_RST_SDIO_1 (0xc104030U) #define VERSAL_RST_I2C_PMC (0xc104031U) #define VERSAL_RST_GPIO_PMC (0xc104032U) #define VERSAL_RST_GEM_0 (0xc104033U) #define VERSAL_RST_GEM_1 (0xc104034U) #define VERSAL_RST_SPARE (0xc104035U) #define VERSAL_RST_USB_0 (0xc104036U) #define VERSAL_RST_UART_0 (0xc104037U) #define VERSAL_RST_UART_1 (0xc104038U) #define VERSAL_RST_SPI_0 (0xc104039U) #define VERSAL_RST_SPI_1 (0xc10403aU) #define VERSAL_RST_CAN_FD_0 (0xc10403bU) #define VERSAL_RST_CAN_FD_1 (0xc10403cU) #define VERSAL_RST_I2C_0 (0xc10403dU) #define VERSAL_RST_I2C_1 (0xc10403eU) #define VERSAL_RST_GPIO_LPD (0xc10403fU) #define VERSAL_RST_TTC_0 (0xc104040U) #define VERSAL_RST_TTC_1 (0xc104041U) #define VERSAL_RST_TTC_2 (0xc104042U) #define VERSAL_RST_TTC_3 (0xc104043U) #define VERSAL_RST_SWDT_FPD (0xc104044U) #define VERSAL_RST_SWDT_LPD (0xc104045U) #define VERSAL_RST_USB (0xc104046U) #define VERSAL_RST_DPC (0xc208047U) #define VERSAL_RST_PMCDBG (0xc208048U) #define VERSAL_RST_DBG_TRACE (0xc208049U) #define VERSAL_RST_DBG_FPD (0xc20804aU) #define VERSAL_RST_DBG_TSTMP (0xc20804bU) #define VERSAL_RST_RPU0_DBG (0xc20804cU) #define VERSAL_RST_RPU1_DBG (0xc20804dU) #define VERSAL_RST_HSDP (0xc20804eU) #define VERSAL_RST_DBG_LPD (0xc20804fU) #define VERSAL_RST_CPM_POR (0xc30c050U) #define VERSAL_RST_CPM (0xc410051U) #define VERSAL_RST_CPMDBG (0xc208052U) #define VERSAL_RST_PCIE_CFG (0xc410053U) #define VERSAL_RST_PCIE_CORE0 (0xc410054U) #define VERSAL_RST_PCIE_CORE1 (0xc410055U) #define VERSAL_RST_PCIE_DMA (0xc410056U) #define VERSAL_RST_CMN (0xc410057U) #define VERSAL_RST_L2_0 (0xc410058U) #define VERSAL_RST_L2_1 (0xc410059U) #define VERSAL_RST_ADDR_REMAP (0xc41005aU) #define VERSAL_RST_CPI0 (0xc41005bU) #define VERSAL_RST_CPI1 (0xc41005cU) #define VERSAL_RST_XRAM (0xc30c05dU) #define VERSAL_RST_AIE_ARRAY (0xc10405eU) #define VERSAL_RST_AIE_SHIM (0xc10405fU) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" #include "include/dt-bindings/power/xlnx-versal-regnode.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; }; versal_reset: reset-controller { compatible = "xlnx,versal-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,versal-pinctrl"; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; resets = <&versal_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_clk USB0_BUS_REF>; }; &watchdog { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; &sysmon0 { xlnx,nodeid = ; }; &sysmon1 { xlnx,nodeid = ; }; &sysmon2 { xlnx,nodeid = ; }; &sysmon3 { xlnx,nodeid = ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: gic-its@f9020000 { compatible = "arm,gic-v3-its"; status = "disabled"; msi-controller; msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; apm: performance-monitor@f0920000 { compatible = "xlnx,flexnoc-pm-2.7"; status = "disabled"; reg-names = "funnel", "baselpd", "basefpd"; reg = <0x0 0xf0920000 0x0 0x1000>, <0x0 0xf0980000 0x0 0x9000>, <0x0 0xf0b80000 0x0 0x9000>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <0>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <1>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <2>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc-edac"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "ddrmc_base", "ddrmc_noc_base"; interrupts = <0 147 4>; xlnx,mc-id = <3>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupts = <0 10 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; u-boot,dm-pre-reloc; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>, <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xC0000000>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>, <0 125 4>; clock-names = "ref_clk", "pclk"; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 0x16 4>, <0 0x1A 4>, <0x0 0x4a 0x4>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; cpm5_pcie: pcie@fcdd0000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm5-host"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_1 0>, <0 0 0 2 &pcie_intc_1 1>, <0 0 0 3 &pcie_intc_1 2>, <0 0 0 4 &pcie_intc_1 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, <0x00 0xfce20000 0x00 0x1000000>; reg-names = "cpm_slcr", "cfg", "cpm_csr"; pcie_intc_1: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; timeout-sec = <30>; }; xilsem_edac: edac@f2014050 { compatible = "xlnx,versal-xilsem-edac"; status = "disabled"; reg = <0x0 0xf2014050 0x0 0xc4>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { ref_clk: ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN0_REF_2X>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN1_REF_2X>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <1>; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; versal_net_power: zynqmp-power { /* untested */ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_sec_cfg: versal-sec-cfg { /* untested */ compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_net_clk ACPU_0>; }; &cpu100 { clocks = <&versal_net_clk ACPU_0>; }; &cpu200 { clocks = <&versal_net_clk ACPU_0>; }; &cpu300 { clocks = <&versal_net_clk ACPU_0>; }; &cpu10000 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10100 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10200 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10300 { clocks = <&versal_net_clk ACPU_1>; }; &cpu20000 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20100 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20200 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20300 { clocks = <&versal_net_clk ACPU_2>; }; &cpu30000 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30100 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30200 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30300 { clocks = <&versal_net_clk ACPU_3>; }; &can0 { clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &adma0 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; &adma1 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; &adma2 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; &adma3 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; &adma4 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; &adma5 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; &adma6 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; &adma7 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_net_clk OSPI_REF>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; &lpd_wwdt0 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; &lpd_wwdt1 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET fixed clock * * (C) Copyright 2022, Xilinx, Inc. * * Michal Simek */ #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk150: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; clk160: clk160 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <160000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk450: clk450 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <450000000>; }; clk1200: clk1200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1200000000>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; u-boot,dm-pre-reloc; method = "smc"; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; }; }; &adma0 { clocks = <&clk450>, <&clk450>; }; &adma1 { clocks = <&clk450>, <&clk450>; }; &adma2 { clocks = <&clk450>, <&clk450>; }; &adma3 { clocks = <&clk450>, <&clk450>; }; &adma4 { clocks = <&clk450>, <&clk450>; }; &adma5 { clocks = <&clk450>, <&clk450>; }; &adma6 { clocks = <&clk450>, <&clk450>; }; &adma7 { clocks = <&clk450>, <&clk450>; }; &can0 { clocks = <&clk160>, <&clk160>; }; &can1 { clocks = <&clk160>, <&clk160>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gpio0 { clocks = <&clk100>; }; &gpio1 { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &i3c0 { clocks = <&clk100>; }; &i3c1 { clocks = <&clk100>; }; &ospi { clocks = <&clk200>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &qspi { clocks = <&clk300>, <&clk300>; }; &rtc { /* Nothing */ }; &sdhci0 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &sdhci1 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &serial0 { clocks = <&clk100>, <&clk100>; clock = <1000000>; }; &serial1 { clocks = <&clk100>, <&clk100>; clock = <100000000>; }; &spi0 { clocks = <&clk200>, <&clk200>; }; &spi1 { clocks = <&clk200>, <&clk200>; }; &ttc0 { clocks = <&clk150>; }; &usb0 { clocks = <&clk60>, <&clk60>; }; &dwc3_0 { /* Nothing */ }; &usb1 { clocks = <&clk60>, <&clk60>; }; &dwc3_1 { /* Nothing */ }; &wwdt0 { clocks = <&clk150>; }; &wwdt1 { clocks = <&clk150>; }; &wwdt2 { clocks = <&clk150>; }; &wwdt3 { clocks = <&clk150>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; u-boot,dm-pre-reloc; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware"; interrupt-parent = <&gic>; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,versal-net-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; is-dual = <0>; is-stacked = <0>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; no-wp; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: dwc3@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: dwc3@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/versal-net/versal-net.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net"; model = "Xilinx Versal NET"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; cluster2 { core0 { cpu = <&cpu20000>; }; core1 { cpu = <&cpu20100>; }; core2 { cpu = <&cpu20200>; }; core3 { cpu = <&cpu20300>; }; }; cluster3 { core0 { cpu = <&cpu30000>; }; core1 { cpu = <&cpu30100>; }; core2 { cpu = <&cpu30200>; }; core3 { cpu = <&cpu30300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-1066000000 { opp-hz = /bits/ 64 <1066000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1866000000 { opp-hz = /bits/ 64 <1866000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1999000000 { opp-hz = /bits/ 64 <1999000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2050000000 { opp-hz = /bits/ 64 <2050000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2100000000 { opp-hz = /bits/ 64 <2100000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2200000000 { opp-hz = /bits/ 64 <2200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; i2c0 = &i2c0; i2c1 = &i2c1; rtc = &rtc; usb0 = &usb0; usb1 = &usb1; spi0 = &ospi; spi1 = &qspi; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; #address-cells = <2>; #size-cells = <2>; ranges; its: msi-controller@e2040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0xe2040000 0 0x20000>; }; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 20 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 180 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i3c0: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 21 4>; }; i3c1: i3c-master@f1958000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1958000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 22 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; /* u-boot specific */ /* cdns,is-stig-pgm = <1>; - unused - checking with Sai */ cdns,trigger-address = <0xc0000000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */ interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-net-emmc"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; serial0: serial@f1920000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; serial1: serial@f1930000 { u-boot,dm-pre-reloc; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; smmu: iommu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; dma-coherent; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; status = "disabled"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 202 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; }; ttc1: timer@f1dd0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; timer-width = <32>; reg = <0x0 0xf1dd0000 0x0 0x1000>; }; ttc2: timer@f1de0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 49 4>, <0 50 4>, <0 51 4>; timer-width = <32>; reg = <0x0 0xf1de0000 0x0 0x1000>; }; ttc3: timer@f1df0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 52 4>, <0 53 4>, <0 54 4>; timer-width = <32>; reg = <0x0 0xf1df0000 0x0 0x1000>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3", "otg", "usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /*phy-names = "usb3-phy";- checking with Pyiush */ }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; interrupt-names = "usb-wakeup"; interrupts = <0 99 4>; #address-cells = <2>; #size-cells = <2>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /* phy-names = "usb3-phy"; - checking with Pyiush */ }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt0: watchdog@ea420000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea420000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt1: watchdog@ea430000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea430000 0 0x10000>; timeout-sec = <30>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/zynq/skeleton.dtsi ================================================ /* * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { compatible = "xlnx,zynq-qspi-1.0"; reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; clocks = <&clkc 10>, <&clkc 43>; clock-names = "ref_clk", "pclk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; /* * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", * "dma4", "dma5", "dma6", "dma7"; */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { fclk0: fclk0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL0_REF>; }; fclk1: fclk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL1_REF>; }; fclk2: fclk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL2_REF>; }; fclk3: fclk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&zynqmp_clk PL3_REF>; }; pss_ref_clk: pss_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { u-boot,dm-pre-reloc; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2023.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp-ipi { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { u-boot,dm-pre-reloc; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; u-boot,dm-pre-reloc; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; nvmem-firmware { compatible = "xlnx,zynqmp-nvmem-fw"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse-dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse-usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse-usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse-usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse-usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse-usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse-usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse-usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse-usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse-miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse-chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse-pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse-sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse-spkid@5c { reg = <0x5c 0x4>; }; efuse_ppk0hash: efuse-ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse-ppk1hash@d0 { reg = <0xd0 0x30>; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; edac { compatible = "arm,cortex-a53-edac"; }; fpga_full: fpga-full { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; }; usb1: usb@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg", "hiber"; interrupts = <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp-aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp-dp-snd-card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/ac701-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/kc705-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105-tmr.dtsi ================================================ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/kcu105.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/sp701-rev1.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/vcu118-rev2.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-property/ pcs-handle ; /delete-property/ managed ; /delete-property/ xlnx,switch-x-sgmii ; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &uart1 { /* uart1 MIO40-41 */ bootph-all; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-emb-plus-ve2302-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal Embedded+ VE2302 revA * * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-emb-plus-ve2302-revA", "xlnx,versal-emb-plus-ve2302", "xlnx,versal"; model = "Xilinx Versal Embedded+ VE2302 revA"; chosen { bootargs = "earlycon clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; i2c0 = &i2c0; }; /* For extension board */ onewire { compatible = "w1-gpio"; gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; }; }; &gpio0 { gpio-line-names = "GPIO_LED2", "GPIO_LED3", "GPIO_LED4", "", "1WIRE", /* 0 - 4 */ "", "FUSA", "", "EGPIO", "AGPIO", /* 5 - 9 */ "I2C0_SCL", "I2C0_SDA", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "3V3_MON_N", /* 20 - 24 */ "3V3_MON_P", /* 25, MIO end and EMIO start */ "", "", "", /* 26 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", ""; /* 55 - 57 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-emu-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-net-emu-1.9", "xlnx,versal-net-emu"; model = "Xilinx Versal NET EMU 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x10000000>; device_type = "memory"; }; aliases { serial0 = &serial0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh"; stdout-path = "serial0:115200"; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; clk1: clk1 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; /* it doesn't matter on EMU */ }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET IPP/SPP OSPI * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-net-ipp-rev1.9.dtsi" / { model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; }; &ospi { status = "okay"; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; serail2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; bootph-all; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; broken-flash-reset; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2) * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ i2c-mux@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c@0 { #address-cells = <1>; #size-cells = <0>; qsfp56g_0: gpio@20 { /* u118 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_0_OC_B", "QSFP56G_0_PWR_EN", /* 0, 1 */ "QSFP56G_0_LED_1", "QSFP56G_0_LED_0", /* 2, 3 */ "QSFP56G_0_MODPRS_B", "QSFP56G_0_LPMODE", /* 4, 5 */ "QSFP56G_0_RESET_B", "QSFP56G_0_MODSEL_B"; /* 6, 7 */ }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; qsfp56g_1: gpio@20 { /* u117 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_1_OC_B", "QSFP56G_1_PWR_EN", /* 0, 1 */ "QSFP56G_1_LED_1", "QSFP56G_1_LED_0", /* 2, 3 */ "QSFP56G_1_MODPRS_B", "QSFP56G_1_LPMODE", /* 4, 5 */ "QSFP56G_1_RESET_B", "QSFP56G_1_MODSEL_B"; /* 6, 7 */ }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; /* J48 connector */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; /* J47 connector */ }; }; /* GPIO_DIP_SW0-1 GPIO_LED0-1 GPIO_PB0-1 GPIO_SMA */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-p-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net-vn-p-b2197-00-revA", "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; }; &i2c0 { /* Access via J70/J71 or J82/J83 */ clock-frequency = <100000>; }; &i2c1 { /* Access via J70/J71 or J82/J83 */ /* By default this bus should have eeprom for board identification at 0x54 */ /* SE/X-PRC card identification is also on this bus at 0x52 */ clock-frequency = <100000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-net-vn-x-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal Net VNX board * * (C) Copyright 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-net-vn-x-b2197-00-revA", "xlnx,versal-net-vn-x-b2197-00", "xlnx,versal-net"; model = "Xilinx Versal Net VNX"; aliases { nvmem0 = &eeprom0; }; }; &adma0 { status = "okay"; }; &adma1 { status = "okay"; }; &adma2 { status = "okay"; }; &adma3 { status = "okay"; }; &adma4 { status = "okay"; }; &adma5 { status = "okay"; }; &adma6 { status = "okay"; }; &adma7 { status = "okay"; }; &lpd_wwdt0 { status = "okay"; }; &gem1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy>; phy-mode = "rmii"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy { reg = <4>; }; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; eeprom0: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; bootph-all; }; }; &i2c1 { status = "okay"; eeprom1: eeprom@55 { compatible = "st,24c128", "atmel,24c128"; reg = <0x55>; bootph-all; }; }; &ospi { status = "okay"; is-dual = <0>; is-stacked = <1>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; reset-names = "qspi"; #address-cells = <1>; #size-cells = <0>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x8000000>; }; }; }; }; &sdhci1 { status = "okay"; non-removable; disable-wp; bus-width = <8>; no-1-8-v; }; &serial0 { status = "okay"; }; &serial1 { status = "okay"; }; &spi1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; num-cs = <3>; }; &usb1 { status = "okay"; }; &dwc3_1 { status = "okay"; snps,refclk_fladj; snps,mask_phy_reset; phy-names = "usb3-phy"; }; &wwdt0 { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { spi0 = &ospi; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { reg = <2>; }; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>, <1>; stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" #include "include/dt-bindings/net/mscc-phy-vsc8531.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; rx-internal-delay-ps = <2600>; tx-internal-delay-ps = <2600>; }; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; aliases { serial2 = &dcc; }; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revA * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revA", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revB * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revB", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revB"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* u198 - ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2000>; adi,tx-internal-delay-ps = <2000>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-virt.dtsi ================================================ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; phy2: ethernet-phy@2 { /* u134 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; }; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <2>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; spi0 = &qspi; usb0 = &usb0; }; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb1; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ #include / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { bootph-all; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { bootph-all; is-dual = <1>; num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-reva.dtsi ================================================ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-revb.dtsi ================================================ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zedboard.dtsi ================================================ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { bootph-all; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; }; &uart1 { bootph-all; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; nvmem0 = &eeprom1; nvmem1 = &eeprom0; serial0 = &uart0; }; }; &i2c0 { bootph-all; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; bootph-all; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; bootph-all; reg = <0x50>; }; }; }; }; &i2c1 { bootph-all; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; bootph-all; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; bootph-all; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; ref_clk: ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570-ddrdimm1-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570-lpddr4-clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570-lpddr4-clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570-hsdp-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570-zsfp-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570-user1-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u39 8T49N240 */ }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; silabs,skip-recall; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-e-a2197-00-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevB System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-e-a2197-00-reva.dtsi" / { model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; /delete-node/ ina226-vcco-500; /delete-node/ ina226-vcco-501; /delete-node/ ina226-vcco-502; }; &i2c0 { i2c-mux@74 { /* u33 */ i2c@2 { /* PCIE_CLK */ /delete-node/ clock-generator@6c; }; i2c@3 { /* PMBUS2_INA226 */ /delete-node/ ina226@42; /delete-node/ ina226@43; /delete-node/ ina226@44; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; usb0 = &usb0; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; }; ref_clk: ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4-dimm1-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4-dimm2-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u39 8T49N240 - pcie clocking 3 */ }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/net/ti-dp83867.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 1>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <100>; reset-deassert-us = <280>; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { /* i2c1 MIO 24-25 */ bootph-all; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &uart1 { /* uart0 MIO36-37 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { /* required by spec */ status = "okay"; pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; mux { groups = "uart1_9_grp"; function = "uart1"; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; power-source = ; }; mux { groups = "i2c1_6_grp"; function = "i2c1"; }; }; pinctrl_i2c1_gpio: i2c1-gpio { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; power-source = ; }; mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; }; pinctrl_gem1_default: gem1-default { conf { groups = "ethernet1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO44", "MIO46", "MIO48"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO45", "MIO47", "MIO49"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; low-power-enable; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; mux { function = "ethernet1"; groups = "ethernet1_0_grp"; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * Copyright (C) 2021-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sc-revb.dtsi" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ /delete-node/ mdio; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; adi,tx-internal-delay-ps = <2400>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revA * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; gtclk1_1: sys-clk-0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 0>; }; gtclk1_2: sys-clk-1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 1>; }; gtclk1_3: sys-clk-2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 2>; }; gtclk1_6: gtclk1-out6 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 3>; }; gtclk1_7: gtclk1-out7 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 4>; }; gtclk1_8: gtclk1-out8 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 5>; }; gtclk1_10: ps-ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 6>; }; gtclk1_11: gtclk1-out11 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 7>; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir35215_46: pmic@46 { /* IR35215 - u152 */ compatible = "infineon,ir35215"; reg = <0x46>; /* i2c addr - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; irps5401_48: pmic@48 { /* IRPS5401 - u279 */ compatible = "infineon,irps5401"; reg = <0x48>; /* i2c addr 0x18 */ }; ir38064_49: regulator@49 { /* IR38064 - u295 */ compatible = "infineon,ir38064"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1d */ }; ir38060_4e: regulator@4e { /* IR38060 - u282 */ compatible = "infineon,ir38060"; reg = <0x4e>; /* i2c addr 0x1e */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* alerts coming to u233 and SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <500>; /* r440 */ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <500>; /* r1702 */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r382 */ }; vcc_ram: ina226@43 { /* u355 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2417 */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; /* r1830 */ }; vcc_psfp: ina226@45 { /* u260 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2386 */ }; vcco_hdio: ina226@46 { /* u356 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; /* r2392 */ }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* alerts coming to u233 and SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; /* r2384 */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; /* r2000 */ }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r1829 */ }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2397 */ }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2401 */ }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <500>; /* r1384 */ }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; /* r1994 */ }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; /* r2384 */ }; vcc1v1_lp4: ina226@49 { /* u306 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <500>; /* r2064 */ }; vadj_fmc: ina226@4a { /* u281 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; /* r2031 */ }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; /* r2004 */ }; lpdmgtyavtt: ina226@4c { /* u309 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; /* r1229 */ }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ }; }; i2c@4 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; rc21008a_gtclk1: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* connector j374 */ /* rc21008a at 0x9 u299 */ vc7: clock-generator@9 { compatible = "renesas,rc21008a"; reg = <0x9>; #clock-cells = <1>; clocks = <&vc7_xin>; clock-names = "xin"; }; }; fmcp1_iic: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* to j51c */ }; sfp: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* sfp+ connector J376 */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sc-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revB * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "zynqmp-sc-vek280-reva.dtsi" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SM-K24 RevA/B/1"; compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pmu_region: pmu@7ff00000 { reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k24-reva.dtsi" / { model = "ZynqMP SMK-K24 RevA"; compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; si570_user1_fmc_clk: si570-user1-fmc-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570-ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570-lpddr4-clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570-lpddr4-clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570-lpddr4-clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; button-16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-versal-net-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_CLK_VERSAL_NET_H #define _DT_BINDINGS_CLK_VERSAL_NET_H #include #define GEM0_REF_RX 0xA9 #define GEM0_REF_TX 0xA8 #define GEM1_REF_RX 0xA2 #define GEM1_REF_TX 0xA1 #define CAN0_REF_2X 0x9E #define CAN1_REF_2X 0xAC #define FPD_WWDT 0x96 #define ACPU_0 0x98 #define ACPU_1 0x9B #define ACPU_2 0x9A #define ACPU_3 0x99 #define I3C0_REF 0x9D #define I3C1_REF 0x9F #define USB1_BUS_REF 0xAE #define LPD_WWDT 0xAD /* Remove Versal specific node IDs */ #undef APU_PLL #undef RPU_PLL #undef CPM_PLL #undef APU_PRESRC #undef APU_POSTCLK #undef APU_PLL_OUT #undef APLL #undef RPU_PRESRC #undef RPU_POSTCLK #undef RPU_PLL_OUT #undef RPLL #undef CPM_PRESRC #undef CPM_POSTCLK #undef CPM_PLL_OUT #undef CPLL #undef APLL_TO_XPD #undef RPLL_TO_XPD #undef RCLK_PMC #undef RCLK_LPD #undef WDT #undef MUXED_IRO_DIV2 #undef MUXED_IRO_DIV4 #undef PSM_REF #undef CPM_CORE_REF #undef CPM_LSBUS_REF #undef CPM_DBG_REF #undef CPM_AUX0_REF #undef CPM_AUX1_REF #undef CPU_R5 #undef CPU_R5_CORE #undef CPU_R5_OCM #undef CPU_R5_OCM2 #undef CAN0_REF #undef CAN1_REF #undef I2C0_REF #undef I2C1_REF #undef CPM_TOPSW_REF #undef USB3_DUAL_REF #undef MUXED_IRO #undef PL_EXT #undef PL_LB #undef MIO_50_OR_51 #undef MIO_24_OR_25 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/net/mscc-phy-vsc8531.h ================================================ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Device Tree constants for Microsemi VSC8531 PHY * * Author: Nagaraju Lakkaraju * * Copyright (c) 2017 Microsemi Corporation */ #ifndef _DT_BINDINGS_MSCC_VSC8531_H #define _DT_BINDINGS_MSCC_VSC8531_H /* PHY LED Modes */ #define VSC8531_LINK_ACTIVITY 0 #define VSC8531_LINK_1000_ACTIVITY 1 #define VSC8531_LINK_100_ACTIVITY 2 #define VSC8531_LINK_10_ACTIVITY 3 #define VSC8531_LINK_100_1000_ACTIVITY 4 #define VSC8531_LINK_10_1000_ACTIVITY 5 #define VSC8531_LINK_10_100_ACTIVITY 6 #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 #define VSC8531_DUPLEX_COLLISION 8 #define VSC8531_COLLISION 9 #define VSC8531_ACTIVITY 10 #define VSC8584_100FX_1000X_ACTIVITY 11 #define VSC8531_AUTONEG_FAULT 12 #define VSC8531_SERIAL_MODE 13 #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-net-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H #define _DT_BINDINGS_VERSAL_NET_POWER_H #include #define PM_DEV_USB_1 (0x182240D7U) #define PM_DEV_FPD_SWDT_0 (0x182240DBU) #define PM_DEV_FPD_SWDT_1 (0x182240DCU) #define PM_DEV_FPD_SWDT_2 (0x182240DDU) #define PM_DEV_FPD_SWDT_3 (0x182240DEU) #define PM_DEV_TCM_A_0A (0x183180CBU) #define PM_DEV_TCM_A_0B (0x183180CCU) #define PM_DEV_TCM_A_0C (0x183180CDU) #define PM_DEV_RPU_A_0 (0x181100BFU) #define PM_DEV_LPD_SWDT_0 (0x182240D9U) #define PM_DEV_LPD_SWDT_1 (0x182240DAU) /* Remove Versal specific node IDs */ #undef PM_DEV_RPU0_0 #undef PM_DEV_RPU0_1 #undef PM_DEV_OCM_0 #undef PM_DEV_OCM_1 #undef PM_DEV_OCM_2 #undef PM_DEV_OCM_3 #undef PM_DEV_TCM_0_A #undef PM_DEV_TCM_1_A #undef PM_DEV_TCM_0_B #undef PM_DEV_TCM_1_B #undef PM_DEV_SWDT_FPD #undef PM_DEV_AI #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_LPD (0x18224028U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-versal-regnode.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H #define _DT_BINDINGS_VERSAL_REGNODE_H #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-versal-net-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H #define _DT_BINDINGS_VERSAL_NET_RESETS_H #include "xlnx-versal-resets.h" #define VERSAL_RST_USB_1 (0xC1040C6U) /* Remove Versal specific reset IDs */ #undef VERSAL_RST_ACPU_0_POR #undef VERSAL_RST_ACPU_1_POR #undef VERSAL_RST_OCM2_POR #undef VERSAL_RST_APU #undef VERSAL_RST_ACPU_0 #undef VERSAL_RST_ACPU_1 #undef VERSAL_RST_ACPU_L2 #undef VERSAL_RST_RPU_ISLAND #undef VERSAL_RST_RPU_AMBA #undef VERSAL_RST_R5_0 #undef VERSAL_RST_R5_1 #undef VERSAL_RST_OCM2_RST #undef VERSAL_RST_I2C_PMC #undef VERSAL_RST_I2C_0 #undef VERSAL_RST_I2C_1 #undef VERSAL_RST_SWDT_FPD #undef VERSAL_RST_SWDT_LPD #undef VERSAL_RST_USB #undef VERSAL_RST_DPC #undef VERSAL_RST_DBG_TRACE #undef VERSAL_RST_DBG_TSTMP #undef VERSAL_RST_RPU0_DBG #undef VERSAL_RST_RPU1_DBG #undef VERSAL_RST_HSDP #undef VERSAL_RST_CPMDBG #undef VERSAL_RST_PCIE_CFG #undef VERSAL_RST_PCIE_CORE0 #undef VERSAL_RST_PCIE_CORE1 #undef VERSAL_RST_PCIE_DMA #undef VERSAL_RST_L2_0 #undef VERSAL_RST_L2_1 #undef VERSAL_RST_ADDR_REMAP #undef VERSAL_RST_CPI0 #undef VERSAL_RST_CPI1 #undef VERSAL_RST_XRAM #undef VERSAL_RST_AIE_ARRAY #undef VERSAL_RST_AIE_SHIM #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-versal-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H #define _DT_BINDINGS_VERSAL_RESETS_H #define VERSAL_RST_PMC_POR (0xc30c001U) #define VERSAL_RST_PMC (0xc410002U) #define VERSAL_RST_PS_POR (0xc30c003U) #define VERSAL_RST_PL_POR (0xc30c004U) #define VERSAL_RST_NOC_POR (0xc30c005U) #define VERSAL_RST_FPD_POR (0xc30c006U) #define VERSAL_RST_ACPU_0_POR (0xc30c007U) #define VERSAL_RST_ACPU_1_POR (0xc30c008U) #define VERSAL_RST_OCM2_POR (0xc30c009U) #define VERSAL_RST_PS_SRST (0xc41000aU) #define VERSAL_RST_PL_SRST (0xc41000bU) #define VERSAL_RST_NOC (0xc41000cU) #define VERSAL_RST_NPI (0xc41000dU) #define VERSAL_RST_SYS_RST_1 (0xc41000eU) #define VERSAL_RST_SYS_RST_2 (0xc41000fU) #define VERSAL_RST_SYS_RST_3 (0xc410010U) #define VERSAL_RST_FPD (0xc410011U) #define VERSAL_RST_PL0 (0xc410012U) #define VERSAL_RST_PL1 (0xc410013U) #define VERSAL_RST_PL2 (0xc410014U) #define VERSAL_RST_PL3 (0xc410015U) #define VERSAL_RST_APU (0xc410016U) #define VERSAL_RST_ACPU_0 (0xc410017U) #define VERSAL_RST_ACPU_1 (0xc410018U) #define VERSAL_RST_ACPU_L2 (0xc410019U) #define VERSAL_RST_ACPU_GIC (0xc41001aU) #define VERSAL_RST_RPU_ISLAND (0xc41001bU) #define VERSAL_RST_RPU_AMBA (0xc41001cU) #define VERSAL_RST_R5_0 (0xc41001dU) #define VERSAL_RST_R5_1 (0xc41001eU) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) #define VERSAL_RST_SYSMON_LPD (0xc410023U) #define VERSAL_RST_PDMA_RST1 (0xc410024U) #define VERSAL_RST_PDMA_RST0 (0xc410025U) #define VERSAL_RST_ADMA (0xc410026U) #define VERSAL_RST_TIMESTAMP (0xc410027U) #define VERSAL_RST_OCM (0xc410028U) #define VERSAL_RST_OCM2_RST (0xc410029U) #define VERSAL_RST_IPI (0xc41002aU) #define VERSAL_RST_SBI (0xc41002bU) #define VERSAL_RST_LPD (0xc41002cU) #define VERSAL_RST_QSPI (0xc10402dU) #define VERSAL_RST_OSPI (0xc10402eU) #define VERSAL_RST_SDIO_0 (0xc10402fU) #define VERSAL_RST_SDIO_1 (0xc104030U) #define VERSAL_RST_I2C_PMC (0xc104031U) #define VERSAL_RST_GPIO_PMC (0xc104032U) #define VERSAL_RST_GEM_0 (0xc104033U) #define VERSAL_RST_GEM_1 (0xc104034U) #define VERSAL_RST_SPARE (0xc104035U) #define VERSAL_RST_USB_0 (0xc104036U) #define VERSAL_RST_UART_0 (0xc104037U) #define VERSAL_RST_UART_1 (0xc104038U) #define VERSAL_RST_SPI_0 (0xc104039U) #define VERSAL_RST_SPI_1 (0xc10403aU) #define VERSAL_RST_CAN_FD_0 (0xc10403bU) #define VERSAL_RST_CAN_FD_1 (0xc10403cU) #define VERSAL_RST_I2C_0 (0xc10403dU) #define VERSAL_RST_I2C_1 (0xc10403eU) #define VERSAL_RST_GPIO_LPD (0xc10403fU) #define VERSAL_RST_TTC_0 (0xc104040U) #define VERSAL_RST_TTC_1 (0xc104041U) #define VERSAL_RST_TTC_2 (0xc104042U) #define VERSAL_RST_TTC_3 (0xc104043U) #define VERSAL_RST_SWDT_FPD (0xc104044U) #define VERSAL_RST_SWDT_LPD (0xc104045U) #define VERSAL_RST_USB (0xc104046U) #define VERSAL_RST_DPC (0xc208047U) #define VERSAL_RST_PMCDBG (0xc208048U) #define VERSAL_RST_DBG_TRACE (0xc208049U) #define VERSAL_RST_DBG_FPD (0xc20804aU) #define VERSAL_RST_DBG_TSTMP (0xc20804bU) #define VERSAL_RST_RPU0_DBG (0xc20804cU) #define VERSAL_RST_RPU1_DBG (0xc20804dU) #define VERSAL_RST_HSDP (0xc20804eU) #define VERSAL_RST_DBG_LPD (0xc20804fU) #define VERSAL_RST_CPM_POR (0xc30c050U) #define VERSAL_RST_CPM (0xc410051U) #define VERSAL_RST_CPMDBG (0xc208052U) #define VERSAL_RST_PCIE_CFG (0xc410053U) #define VERSAL_RST_PCIE_CORE0 (0xc410054U) #define VERSAL_RST_PCIE_CORE1 (0xc410055U) #define VERSAL_RST_PCIE_DMA (0xc410056U) #define VERSAL_RST_CMN (0xc410057U) #define VERSAL_RST_L2_0 (0xc410058U) #define VERSAL_RST_L2_1 (0xc410059U) #define VERSAL_RST_ADDR_REMAP (0xc41005aU) #define VERSAL_RST_CPI0 (0xc41005bU) #define VERSAL_RST_CPI1 (0xc41005cU) #define VERSAL_RST_XRAM (0xc30c05dU) #define VERSAL_RST_AIE_ARRAY (0xc10405eU) #define VERSAL_RST_AIE_SHIM (0xc10405fU) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" #include "include/dt-bindings/power/xlnx-versal-regnode.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { pl_alt_ref_clk: pl_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; }; versal_reset: reset-controller { compatible = "xlnx,versal-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,versal-pinctrl"; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; resets = <&versal_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_clk USB0_BUS_REF>; }; &watchdog { clocks = <&versal_clk FPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; &watchdog1 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_LPD>; }; &sysmon0 { xlnx,nodeid = ; }; &sysmon1 { xlnx,nodeid = ; }; &sysmon2 { xlnx,nodeid = ; }; &sysmon3 { xlnx,nodeid = ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; bootph-all; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: msi-controller@f9020000 { compatible = "arm,gic-v3-its"; status = "disabled"; msi-controller; #msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma-controller@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x210>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma-controller@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x212>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma-controller@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x214>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma-controller@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x216>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma-controller@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x218>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma-controller@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21a>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma-controller@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21c>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma-controller@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21e>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupts = <0 10 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; bootph-all; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; bootph-all; }; smmu: iommu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xC0000000>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>; clock-names = "ref_clk", "pclk"; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 0x16 4>, <0 0x16 4>, <0 0x1a 4>, <0x0 0x4a 0x4>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; cpm5_pcie: pcie@fcdd0000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm5-host"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_1 0>, <0 0 0 2 &pcie_intc_1 1>, <0 0 0 3 &pcie_intc_1 2>, <0 0 0 4 &pcie_intc_1 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, <0x00 0xfce20000 0x00 0x1000000>; reg-names = "cpm_slcr", "cfg", "cpm_csr"; pcie_intc_1: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; timeout-sec = <30>; }; watchdog1: watchdog@ff120000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xff120000 0 0x10000>; timeout-sec = <30>; }; xilsem_edac: edac@f2014050 { compatible = "xlnx,versal-xilsem-edac"; status = "disabled"; reg = <0x0 0xf2014050 0x0 0xc4>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN0_REF_2X>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN1_REF_2X>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; versal_net_power: zynqmp-power { /* untested */ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_sec_cfg: versal-sec-cfg { /* untested */ compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_net_clk ACPU_0>; }; &cpu100 { clocks = <&versal_net_clk ACPU_0>; }; &cpu200 { clocks = <&versal_net_clk ACPU_0>; }; &cpu300 { clocks = <&versal_net_clk ACPU_0>; }; &cpu10000 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10100 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10200 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10300 { clocks = <&versal_net_clk ACPU_1>; }; &cpu20000 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20100 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20200 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20300 { clocks = <&versal_net_clk ACPU_2>; }; &cpu30000 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30100 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30200 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30300 { clocks = <&versal_net_clk ACPU_3>; }; &can0 { clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &adma0 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; &adma1 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; &adma2 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; &adma3 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; &adma4 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; &adma5 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; &adma6 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; &adma7 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_net_clk OSPI_REF>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; &lpd_wwdt0 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; &lpd_wwdt1 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET fixed clock * * (C) Copyright 2022-2024, Xilinx, Inc. * * Michal Simek */ #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk150: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; clk160: clk160 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <160000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk450: clk450 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <450000000>; }; clk1200: clk1200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1200000000>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; }; }; &adma0 { clocks = <&clk450>, <&clk450>; }; &adma1 { clocks = <&clk450>, <&clk450>; }; &adma2 { clocks = <&clk450>, <&clk450>; }; &adma3 { clocks = <&clk450>, <&clk450>; }; &adma4 { clocks = <&clk450>, <&clk450>; }; &adma5 { clocks = <&clk450>, <&clk450>; }; &adma6 { clocks = <&clk450>, <&clk450>; }; &adma7 { clocks = <&clk450>, <&clk450>; }; &can0 { clocks = <&clk160>, <&clk160>; }; &can1 { clocks = <&clk160>, <&clk160>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gpio0 { clocks = <&clk100>; }; &gpio1 { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &i3c0 { clocks = <&clk100>; }; &i3c1 { clocks = <&clk100>; }; &ospi { clocks = <&clk200>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &qspi { clocks = <&clk300>, <&clk300>; }; &rtc { /* Nothing */ }; &sdhci0 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &sdhci1 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &serial0 { clocks = <&clk100>, <&clk100>; clock = <1000000>; }; &serial1 { clocks = <&clk100>, <&clk100>; clock = <100000000>; }; &spi0 { clocks = <&clk200>, <&clk200>; }; &spi1 { clocks = <&clk200>, <&clk200>; }; &ttc0 { clocks = <&clk150>; }; &usb0 { clocks = <&clk60>, <&clk60>; }; &dwc3_0 { /* Nothing */ }; &usb1 { clocks = <&clk60>, <&clk60>; }; &dwc3_1 { /* Nothing */ }; &wwdt0 { clocks = <&clk150>; }; &wwdt1 { clocks = <&clk150>; }; &wwdt2 { clocks = <&clk150>; }; &wwdt3 { clocks = <&clk150>; }; &lpd_wwdt0 { clocks = <&clk150>; }; &lpd_wwdt1 { clocks = <&clk150>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; bootph-all; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; broken-flash-reset; no-wp; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/versal-net/versal-net.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net"; model = "Xilinx Versal NET"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; cluster2 { core0 { cpu = <&cpu20000>; }; core1 { cpu = <&cpu20100>; }; core2 { cpu = <&cpu20200>; }; core3 { cpu = <&cpu20300>; }; }; cluster3 { core0 { cpu = <&cpu30000>; }; core1 { cpu = <&cpu30100>; }; core2 { cpu = <&cpu30200>; }; core3 { cpu = <&cpu30300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-1066000000 { opp-hz = /bits/ 64 <1066000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1866000000 { opp-hz = /bits/ 64 <1866000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1999000000 { opp-hz = /bits/ 64 <1999000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2050000000 { opp-hz = /bits/ 64 <2050000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2100000000 { opp-hz = /bits/ 64 <2100000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2200000000 { opp-hz = /bits/ 64 <2200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; i2c0 = &i2c0; i2c1 = &i2c1; rtc = &rtc; usb0 = &usb0; usb1 = &usb1; spi0 = &ospi; spi1 = &qspi; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; #address-cells = <2>; #size-cells = <2>; ranges; its: msi-controller@e2040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0xe2040000 0 0x20000>; }; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 20 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 180 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i3c0: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 21 4>; }; i3c1: i3c-master@f1958000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1958000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 22 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; /* u-boot specific */ /* cdns,is-stig-pgm = <1>; - unused - checking with Sai */ cdns,trigger-address = <0xc0000000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */ interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-net-emmc"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; smmu: iommu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; dma-coherent; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; status = "disabled"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 202 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; }; ttc1: timer@f1dd0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; timer-width = <32>; reg = <0x0 0xf1dd0000 0x0 0x1000>; }; ttc2: timer@f1de0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 49 4>, <0 50 4>, <0 51 4>; timer-width = <32>; reg = <0x0 0xf1de0000 0x0 0x1000>; }; ttc3: timer@f1df0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 52 4>, <0 53 4>, <0 54 4>; timer-width = <32>; reg = <0x0 0xf1df0000 0x0 0x1000>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /*phy-names = "usb3-phy";- checking with Pyiush */ }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; interrupt-names = "usb-wakeup"; interrupts = <0 99 4>; #address-cells = <2>; #size-cells = <2>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /* phy-names = "usb3-phy"; - checking with Pyiush */ }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt0: watchdog@ea420000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea420000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt1: watchdog@ea430000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea430000 0 0x10000>; timeout-sec = <30>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/zynq/skeleton.dtsi ================================================ /* * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x3000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { compatible = "xlnx,zynq-qspi-1.0"; reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; clocks = <&clkc 10>, <&clkc 43>; clock-names = "ref_clk", "pclk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { bootph-all; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { bootph-all; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; /* * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", * "dma4", "dma5", "dma6", "dma7"; */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { bootph-all; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; bootph-all; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse-dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse-usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse-usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse-usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse-usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse-usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse-usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse-usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse-usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse-miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse-chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse-pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse-sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse-spkid@5c { reg = <0x5c 0x4>; }; efuse_aeskey: efuse-aeskey@60 { reg = <0x60 0x20>; }; efuse_ppk0hash: efuse-ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse-ppk1hash@d0 { reg = <0xd0 0x30>; }; efuse_pufuser: efuse-pufuser@100 { reg = <0x100 0x7F>; }; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 65 4>, <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; }; usb1: usb@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 70 4>, <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp-aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp-dp-snd-card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/ac701-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ltc2954: ltc2954 { /* U7 */ compatible = "lltc,ltc2954", "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 26 GPIO_ACTIVE_LOW>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; /* MIO on PAD */ kill-gpios = <&gpio 34 GPIO_ACTIVE_LOW>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-full.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernet_0 { phy-handle = <&phy0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/kc705-lite.dtsi ================================================ &iic_main { #address-cells = <1>; #size-cells = <0>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; &axi_ethernetlite { phy-handle = <&phy0>; axi_ethernetlite_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105-tmr.dtsi ================================================ &tmr_0_MB1_axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/kcu105.dtsi ================================================ &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/sp701-rev1.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; ti,rx-internal-delay = <0x3>; ti,tx-internal-delay = <0x3>; ti,fifo-depth = <0x1>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/vcu118-rev2.0.dtsi ================================================ &axi_ethernet_0 { phy-handle = <&phy0>; /delete-property/ pcs-handle ; /delete-property/ managed ; /delete-property/ xlnx,switch-x-sgmii ; /delete-node/ mdio; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@3 { device_type = "ethernet-phy"; ti,sgmii-ref-clock-output-enable; ti,dp83867-rxctrl-strap-quirk; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; reg = <3>; }; }; }; &axi_iic_0 { #address-cells = <1>; #size-cells = <0>; i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; }; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-a2197-sc-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller RevA"; compatible = "xlnx,versal-sc-revA", "xlnx,versal-sc", "xlnx,zynqmp"; /* SC Bank 43 FIXME no idea what they do VCCO_500_RBIAS, VCCO_501_RBIAS, VCCO_502_RBIAS SYSCTLR_GPIO0 - 5 - conneced to versal */ /* cpu thermal for MAX6643 fan control */ leds { compatible = "gpio-leds"; dc38_led { label = "ds38-green"; /* sc AB11 500_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc37_led { label = "ds37-green"; /* sc AD10 501_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; dc36_led { label = "ds36-green"; /* sc AD11 502_RBIAS_LED */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; /* FIXME */ }; }; }; /* usb - type C - pl and micro usb 2.0, gt */ /* Feb 28/2019 version */ &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &uart1 { /* uart1 MIO40-41 */ bootph-all; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* TODO USB0 MIO52-63 USB1 MIO64-75 */ /*eth MDIO 76/77 eth reset MIO42 marwell m88e1512 - SGMII */ &gem0 { phy-handle = <&phy0>; /* phy-mode = "sgmii"; DTG generates this properly */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: phy@21 { reg = <21>; /* FIXME */ /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5- 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 0 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@c0 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681"; /* FIXME no linux driver */ reg = <0xc0>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <10000000>; /* 10 ohm */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* FIXME connection to Samtec J212D */ }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@5d { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@5d { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@5d { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "LPDDR4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */ clock-frequency = <33333333>; clock-output-names = "HSDP_SI570"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-emb-plus-ve2302-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal Embedded+ VE2302 revA * * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-emb-plus-ve2302-revA", "xlnx,versal-emb-plus-ve2302", "xlnx,versal"; model = "Xilinx Versal Embedded+ VE2302 revA"; chosen { bootargs = "earlycon clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; i2c0 = &i2c0; }; /* For extension board */ onewire { compatible = "w1-gpio"; gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; }; }; &gpio0 { gpio-line-names = "GPIO_LED2", "GPIO_LED3", "GPIO_LED4", "", "1WIRE", /* 0 - 4 */ "", "FUSA", "", "EGPIO", "AGPIO", /* 5 - 9 */ "I2C0_SCL", "I2C0_SDA", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "3V3_MON_N", /* 20 - 24 */ "3V3_MON_P", /* 25, MIO end and EMIO start */ "", "", "", /* 26 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", ""; /* 55 - 57 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-emu-itr8-cn13940875.dtsi ================================================ / { compatible = "xlnx,versal-emu-itr8", "xlnx,versal-emu", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal EMU ITR8 HW 4.0"; aliases { serial0 = &serial0; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,9600n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:9600"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; clk0212: clk0212 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <212000>; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; }; &timer { clock-frequency = <440000>; }; &serial0 { status = "okay"; clocks = <&clk0212 &clk0212>; current-speed = <9600>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk0212 &clk0212>; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-emu-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-net-emu-1.9", "xlnx,versal-net-emu"; model = "Xilinx Versal NET EMU 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x10000000>; device_type = "memory"; }; aliases { serial0 = &serial0; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 rdinit=/bin/sh"; stdout-path = "serial0:115200"; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; clk1: clk1 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; /* it doesn't matter on EMU */ }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&clk1>, <&clk1>; clock = <1000000>; current-speed = <115200>; skip-init; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-ipp-rev1.9-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET IPP/SPP OSPI * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-net-ipp-rev1.9.dtsi" / { model = "Xilinx Versal NET SPP 5.0/IPP 1.9 OSPI"; }; &ospi { status = "okay"; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; serail2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; bootph-all; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; broken-flash-reset; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva-pl.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197 (Tenzing2) * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ i2c-mux@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c@0 { #address-cells = <1>; #size-cells = <0>; qsfp56g_0: gpio@20 { /* u118 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_0_OC_B", "QSFP56G_0_PWR_EN", /* 0, 1 */ "QSFP56G_0_LED_1", "QSFP56G_0_LED_0", /* 2, 3 */ "QSFP56G_0_MODPRS_B", "QSFP56G_0_LPMODE", /* 4, 5 */ "QSFP56G_0_RESET_B", "QSFP56G_0_MODSEL_B"; /* 6, 7 */ }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; qsfp56g_1: gpio@20 { /* u117 */ compatible = "ti,tca6408"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; gpio-line-names = "QSFP56G_1_OC_B", "QSFP56G_1_PWR_EN", /* 0, 1 */ "QSFP56G_1_LED_1", "QSFP56G_1_LED_0", /* 2, 3 */ "QSFP56G_1_MODPRS_B", "QSFP56G_1_LPMODE", /* 4, 5 */ "QSFP56G_1_RESET_B", "QSFP56G_1_MODSEL_B"; /* 6, 7 */ }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; /* J48 connector */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; /* J47 connector */ }; }; /* GPIO_DIP_SW0-1 GPIO_LED0-1 GPIO_PB0-1 GPIO_SMA */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-p-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VN-P-B2197-00 (Tenzing2) * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net-vn-p-b2197-00-revA", "xlnx,versal-net-vn-p-b2197-00", "xlnx,versal-net"; }; &i2c0 { /* Access via J70/J71 or J82/J83 */ clock-frequency = <100000>; }; &i2c1 { /* Access via J70/J71 or J82/J83 */ /* By default this bus should have eeprom for board identification at 0x54 */ /* SE/X-PRC card identification is also on this bus at 0x52 */ clock-frequency = <100000>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-net-vn-x-b2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal Net VNX board * * (C) Copyright 2022, Xilinx, Inc. * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-net-vn-x-b2197-00-revA", "xlnx,versal-net-vn-x-b2197-00", "xlnx,versal-net"; model = "Xilinx Versal Net VNX"; aliases { nvmem0 = &eeprom0; }; }; &adma0 { status = "okay"; }; &adma1 { status = "okay"; }; &adma2 { status = "okay"; }; &adma3 { status = "okay"; }; &adma4 { status = "okay"; }; &adma5 { status = "okay"; }; &adma6 { status = "okay"; }; &adma7 { status = "okay"; }; &lpd_wwdt0 { status = "okay"; }; &gem1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy>; phy-mode = "rmii"; mdio { #address-cells = <1>; #size-cells = <0>; phy: ethernet-phy { reg = <4>; }; }; }; &gpio0 { status = "okay"; }; &gpio1 { status = "okay"; }; &i2c0 { status = "okay"; eeprom0: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; bootph-all; }; }; &i2c1 { status = "okay"; eeprom1: eeprom@55 { compatible = "st,24c128", "atmel,24c128"; reg = <0x55>; bootph-all; }; }; &ospi { status = "okay"; is-dual = <0>; is-stacked = <1>; reset-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; reset-names = "qspi"; #address-cells = <1>; #size-cells = <0>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <5000000>; broken-flash-reset; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x8000000>; }; }; }; }; &sdhci1 { status = "okay"; non-removable; disable-wp; bus-width = <8>; no-1-8-v; }; &serial0 { status = "okay"; }; &serial1 { status = "okay"; }; &spi1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; num-cs = <3>; }; &usb1 { status = "okay"; }; &dwc3_1 { status = "okay"; snps,refclk_fladj; snps,mask_phy_reset; phy-names = "usb3-phy"; }; &wwdt0 { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-spp-itr8-cn13940875.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-spp-itr8-cn13940875", "xlnx,versal-spp-itr8", "xlnx,versal"; model = "Xilinx Versal SPP ITR8 HW 4.0"; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; spi0 = &qspi; spi1 = &ospi; spi2 = &spi0; spi3 = &spi1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; usb0 = &usb0; }; memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>; }; chosen { bootargs = "rdinit=/bin/sh console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=1"; stdout-path = "serial0:115200"; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; }; &timer { clock-frequency = <2720000>; }; &serial0 { status = "okay"; clocks = <&clk25 &clk25>; }; &lpd_dma_chan0 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan1 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan2 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan3 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan4 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan5 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan6 { status = "okay"; clocks = <&clk100 &clk100>; }; &lpd_dma_chan7 { status = "okay"; clocks = <&clk100 &clk100>; }; &usb0 { status = "okay"; clocks = <&clk125 &clk125>; }; &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; maximum-speed = "high-speed"; }; &gem0 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &gem1 { status = "okay"; clocks = <&clk125 &clk125 &clk125 &clk125>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &sdhci0 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &sdhci1 { status = "okay"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; }; &qspi { status = "okay"; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot-boot.bin"; reg = <0x0 0x6400000>; }; partition@6400000 { label = "qspi-linux"; reg = <0x6400000 0x500000>; }; partition@6900000 { label = "qspi-device-tree"; reg = <0x6900000 0x20000>; }; partition@6920000 { label = "qspi-rootfs"; reg = <0x6920000 0x5E0000>; }; partition@7f40000 { label = "qspi-bootenv"; reg = <0x7f40000 0x40000>; }; }; }; }; &ospi { status = "disabled"; clocks = <&clk125 &clk125>; bus-num = <2>; num-cs = <1>; cdns,fifo-depth = <508>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0x00000000>; flash@0 { compatible = "n25q512a", "micron,m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; &spi0 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <1>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; &spi1 { status = "okay"; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80", "spi-flash"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; &i2c0 { status = "okay"; clocks = <&clk100 &clk100>; }; &i2c1 { status = "okay"; clocks = <&clk100 &clk100>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-v350-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal v350 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-v350-revA", "xlnx,versal"; model = "Xilinx Versal v350 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF010000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &dcc { status = "okay"; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA OSPI"; aliases { spi0 = &ospi; }; }; /* Mutually exclusive */ &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; gpio0 = &gpio; spi0 = &qspi; usb0 = &usb0; }; }; &dcc { status = "okay"; }; &qspi { num-cs = <0x1>; is-dual = <0x1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "spi-flash"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; phy1: phy@1 { reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; phy2: phy@2 { reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; /* FIXME - Remove if board is fixed */ }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-01 revA (SE1) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-01-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-01 revA QSPI"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &sdhci1 { /* U104 */ xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy1>; /* u128 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; phy2: phy@2 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &gem1 { phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &i2c1 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U116 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; /* FIXME - U117 and U118 */ }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-02 revA (SE2) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-02-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-02 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy0>; /* u9 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { /* Marvell 88E1512; U9 */ reg = <1>; }; }; }; &sdhci0 { xlnx,mio-bank = <1>; }; &sdhci1 { /* U1A */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &dwc3_0 { /* U4 */ dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "high-speed"; }; &i2c0 { clock-frequency = <400000>; /* U12 Catalyst EEPROM - AT24 should be equivalent */ eeprom_versal: eeprom@51 { compatible = "atmel,24c128"; reg = <0x51>; }; /* FIXME - U13 and U15 */ }; &spi0 { num-cs = <1>; flash@0 { /* U18 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x200000>; }; }; }; &spi1 { num-cs = <3>; /* FIXME - check SPI1_SS0-2_B */ flash@0 { /* U19 */ #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst26vf016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <25000000>; reg = <0>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-03 revA (SE3) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-03-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-03 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { can0 = &can0; can1 = &can1; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &serial0; spi0 = &qspi; spi1 = &spi0; }; }; &i2c0 { clock-frequency = <400000>; /* Must be enabled via J90/J91 */ eeprom_versal: eeprom@51 { /* U2 - 128kb RM24C128DS */ compatible = "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 64Mb */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x800000>; }; }; }; &sdhci0 { /* J99 MIO28 - MIO33 */ xlnx,mio-bank = <1>; /* FIXME */ }; &sdhci1 { /* EMMC IS21ES08G 200MHz MIO40 - MIO49 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U6 - IS25LQ032B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lq032b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi" / { chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { spi0 = &ospi; }; }; &qspi { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-04 revA (SE4) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-04-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-04 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; spi1 = &spi0; usb0 = &usb0; }; }; &gem1 { phy-handle = <&phy1>; /* u175 */ phy-mode = "rgmii-id"; /* RTL8211DN */ mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { reg = <2>; }; }; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { /* U153 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &i2c1 { clock-frequency = <400000>; eeprom: eeprom@51 { /* U155 */ compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 512MB */ reg = <0>, <1>; stacked-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x20000000>; }; }; }; &sdhci1 { /* J3 MIO26, MIO29 - MIO33 */ disable-wp; xlnx,mio-bank = <1>; /* FIXME */ }; &spi0 { num-cs = <1>; flash@0 { /* U171 - IS25LP016B - 16Mb */ #address-cells = <1>; #size-cells = <1>; compatible = "issi,is25lp016b", "m25p80", "jedec,spi-nor"; spi-max-frequency = <104000000>; reg = <0>; partition@0 { label = "spi0-flash0"; reg = <0 0x200000>; }; }; }; &dwc3_0 { /* USB 2.0 host - U99 */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal X-PRC-05 revA (SE5) * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vc-p-a2197-00-reva.dtsi" #include "include/dt-bindings/net/mscc-phy-vsc8531.h" / { compatible = "xlnx,versal-vc-p-a2197-00-revA-x-prc-05-revA", "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA - x-prc-05 revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; mmc0 = &sdhci0; mmc1 = &sdhci1; spi0 = &qspi; usb0 = &usb0; }; }; &gem0 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { /* 88e1510 */ reg = <1>; }; phy2: phy@2 { /* VSC8531 */ reg = <2>; rx-internal-delay-ps = <2600>; tx-internal-delay-ps = <2600>; }; }; }; &gem1 { phy-handle = <&phy2>; phy-mode = "rgmii-id"; }; &i2c0 { clock-frequency = <400000>; eeprom_versal: eeprom@51 { compatible = "st,24c128", "atmel,24c128"; reg = <0x51>; }; }; &qspi { num-cs = <0x1>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; flash@0 { /* MX25U12835 128Mbit */ #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 16MB */ reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <104000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x1000000>; }; }; }; &sdhci0 { /* emmc0 */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME */ }; &sdhci1 { /* connector */ xlnx,mio-bank = <1>; /* FIXME */ }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vc-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal-vc-p-a2197-00-revA", "xlnx,versal-vc-p-a2197-00", "xlnx,versal-vc-p-a2197", "xlnx,versal"; model = "Xilinx Versal A2197 Processor board revA"; aliases { serial2 = &dcc; }; }; &dcc { status = "okay"; }; &sdhci0 { no-1-8-v; }; &sdhci1 { no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-01-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-02-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1-x-ebm-03-revA", "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1 (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vck190-rev1.1", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board rev1.1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-01-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-01-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (QSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-02-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-02-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (EMMC)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck190 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva-x-ebm-03-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA-x-ebm-03-revA", "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA (OSPI)"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck190-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VCK190 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vck190-revA", "xlnx,versal"; model = "Xilinx Versal vck190 Eval board revA"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vck5000-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vck5000 revA * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vck5000-revA", "xlnx,versal"; model = "Xilinx Versal vck5000 board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; spi0 = &ospi; }; }; &ospi { bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <0x1>; #size-cells = <0x1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; }; &dcc { status = "okay"; }; &serial1 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revA * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revA", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VEK280 revB * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vek280-revB", "xlnx,versal-vek280", "xlnx,versal"; model = "Xilinx Versal vek280 Eval board revB"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* VADJ_FMC_EN - LPD MIO23 */ /* FAN - LPD MIO21/22 */ /* VCC_PL_EN - LPD MIO20 */ /* PCIE_PERST - LPD MIO18/19 */ /* SD_BUSPWR - PMC MIO51 */ /* PCIE_WAKE - PMC MIO50 */ /* VCCPSLP_EN - PMC MIO49 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* PCIE_PWRBRK - PMC MIO38 */ /* ZU4_TRIGGER - PMC MIO37 */ /* VCC_AUX_1V2 - MIO11 */ &ospi { /* PMC MIO0-10, 12, U297 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #stream-id-cells = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* u198 - ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2000>; adi,tx-internal-delay-ps = <2000>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vhk158-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VHK158 revA * * (C) Copyright 2022-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/net/ti-dp83867.h" / { compatible = "xlnx,versal-vhk158-revA", "xlnx,versal-vhk158", "xlnx,versal"; model = "Xilinx Versal vhk158 Eval board revA"; memory: memory@0 { device_type = "memory"; reg = <0 0 0 0x80000000>, <0x8 0x0 0x7 0x80000000>; /* 32GB */ }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &ospi; usb0 = &usb0; rtc0 = &rtc; }; }; /* ZU4_TRIGGER - PMC MIO37 */ /* PCIE_PWRBRK - PMC MIO38 */ /* I2C SYSMON - PMC MIO39 - 41 */ /* VCCPSLP_EN - PMC MIO49 */ /* PCIE_WAKE - PMC MIO50 */ /* SOC_EN - LPD MIO13 */ /* PSFP_EN - LPD MIO15 */ /* AUX_1V2_EN - LPD MIO16 */ /* HBM_EN - LPD MIO17 */ /* PCIE_PERST - LPD MIO18/19 */ /* VCC_PL_EN - LPD MIO20 */ /* FAN - LPD MIO21/22 */ /* VADJ_FMC_EN - LPD MIO23 */ &ospi { /* PMC MIO0 - 12, U297 MT35XU02G */ status = "okay"; compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-virt.dtsi ================================================ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-virt", "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal Virtual"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu@1 { compatible = "arm,cortex-a72", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <1>; }; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; clk2: clk2 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <2670000>; }; clk25: clk25 { bootph-all; compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <25000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; clock-frequency = <2720000>; }; amba_apu: amba_apu { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0x0 0xf9000000 0x0 0x80000>, /* GICD */ <0x0 0xf9080000 0x0 0x80000>; /* GICR */ interrupt-controller; interrupt-parent = <&gic>; interrupts = <0x1 0x9 4>; }; }; amba: amba { bootph-all; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "apb_clk"; clocks = <&clk25 &clk25>; current-speed = <115200>; }; lpd_dma_chan1: dma@ffa80000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 60 4>; /* iommus = <&smmu 0x210>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan2: dma@ffa90000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 61 4>; /* iommus = <&smmu 0x212>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan3: dma@ffaa0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 62 4>; /* iommus = <&smmu 0x214>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff060000 0x0 0x6000>; interrupts = <0 20 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "okay"; clock-names = "can_clk", "s_axi_aclk"; clocks = <&clk100 &clk100>; reg = <0x0 0xff070000 0x0 0x6000>; interrupts = <0 21 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x20>; rx-fifo-depth = <0x40>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 14 4>; reg = <0x0 0xff020000 0x0 0x1000>; scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom1: eeprom@53 { reg = <0x53>; compatible = "at,24c08"; }; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "okay"; clock-frequency = <400000>; interrupt-parent = <&gic>; interrupts = <0 15 4>; reg = <0x0 0xff030000 0x0 0x1000>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&clk25>; eeprom2: eeprom@55 { compatible = "atmel,24c128"; reg = <0x55>; }; }; gpio: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "okay"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 13 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0b0000 0x0 0x1000>; gpio-controller; clocks = <&clk25>; }; lpd_dma_chan4: dma@ffab0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 63 4>; /* iommus = <&smmu 0x216>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan5: dma@ffac0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 64 4>; /* iommus = <&smmu 0x218>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan6: dma@ffad0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 65 4>; /* iommus = <&smmu 0x21a>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan7: dma@ffae0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 66 4>; /* iommus = <&smmu 0x21c>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; lpd_dma_chan8: dma@ffaf0000 { status = "okay"; compatible = "xlnx,zynqmp-dma-1.0"; clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 67 4>; /* iommus = <&smmu 0x21e>; */ xlnx,bus-width = <64>; clocks = <&clk100 &clk100>; }; ethernet0: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 56 4>, <0x0 56 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x234>; */ phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0x0>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; ethernet1: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0x0 58 4>, <0x0 58 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk"; clocks = <&clk2 &clk125 &clk125 &clk125>; #address-cells = <0x1>; #size-cells = <0x0>; /* iommus = <&smmu 0x235>; */ phy-handle = <&phy1>; phy-mode = "rgmii-id"; phy1: phy@1 { reg = <0x1>; max-speed = <100>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,rxctrl-strap-worka; }; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "okay"; reg = <0x0 0xf12a0000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 142 4>, <0 143 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "okay"; clock-names = "ref_clk", "pclk"; interrupt-parent = <&gic>; interrupts = <0 125 4>, <0 125 4>; num-cs = <0x1>; reg = <0x0 0xf1030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; /* iommus = <&smmu 0x244>; */ clocks = <&clk125 &clk125>; is-dual = <1>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "n25q512a", "micron,m25p80"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 16 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <1>; pinctrl-names = "default"; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x100000>; }; }; }; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&clk125 &clk125>; num-cs = <3>; flash@0 { compatible = "m25p80"; spi-max-frequency = <50000000>; reg = <0x0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0x0 0x84000>; }; }; }; }; sdhci0: sdhci@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 126 4>, <0 126 4>; reg = <0x0 0xf1040000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x242>; */ }; sdhci1: sdhci@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "okay"; interrupt-parent = <&gic>; interrupts = <0 128 4>, <0 128 4>; reg = <0x0 0xf1050000 0x0 0x10000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk25 &clk25>; xlnx,mio_bank = <0>; /* iommus = <&smmu 0x243>; */ }; usb0: usb0@ff9d0000 { compatible = "xlnx,versal-dwc3"; #address-cells = <0x2>; #size-cells = <0x2>; status = "okay"; reg = <0x0 0xff9d0000 0x0 0x100>; ranges; clock-names = "bus_clk", "ref_clk"; clocks = <&clk125 &clk125>; dwc3@fe200000 { compatible = "snps,dwc3"; status = "okay"; reg = <0x0 0xfe200000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0x0 0x16 0x4>, <0x0 0x45 0x4>; /* iommus = <&smmu 0x230>; */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; }; }; aliases { serial0 = &serial0; ethernet0 = ðernet0; ethernet1 = ðernet1; qspi = &qspi; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused maxcpus=2"; stdout-path = "serial0:115200"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-01-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-02-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 rev1.1 with X-EBM-03-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-rev1.1.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1-x-ebm-03-revA", "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1 (OSPI)"; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-rev1.1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 rev1.1 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-rev1.1", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board rev1.1"; }; &sdhci1 { /* PMC_MIO26-36/51 */ clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-01-revA module * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-01-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (QSPI)"; }; &qspi { #include "versal-x-ebm-01-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-02-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-02-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (EMMC)"; }; &sdhci1 { #include "versal-x-ebm-02-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vmk180 revA with X-EBM-03-revA module * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "versal-vmk180-reva.dtsi" / { compatible = "xlnx,versal-vmk180-revA-x-ebm-03-revA", "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA (OSPI)"; aliases { spi0 = &ospi; }; }; &ospi { #include "versal-x-ebm-03-reva.dtsi" }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vmk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal VMK180 revA * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { compatible = "xlnx,versal-vmk180-revA", "xlnx,versal"; model = "Xilinx Versal vmk180 Eval board revA"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; ethernet1 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; }; /* PMC_MIO 0 -12 - configuration header QSPI/OSPI/EMMC */ /* FIXME PMC_MIO37 ZU4_TRIGGER/PMC_MIO37/38 PCIE */ &dcc { status = "okay"; }; &sdhci1 { /* PMC_MIO26-36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; &gem0 { /* PMC_MIO_48, LPD_MIO0-11/24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { /* u198 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 48 GPIO_ACTIVE_LOW>; }; phy2: ethernet-phy@2 { /* u134 */ #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <2>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; reset-assert-us = <100>; reset-deassert-us = <280>; reset-gpios = <&gpio1 49 GPIO_ACTIVE_LOW>; }; }; }; &gem1 { /* PMC_MIO_49, LPD_MIO12-23 */ phy-handle = <&phy2>; /* u134 */ phy-mode = "rgmii-id"; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vp-x-a2785-00 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vp-x-a2785-00 Eval board revA"; compatible = "xlnx,versal-vp-x-a2785-00-revA", "xlnx,versal-vp-x-a2785-00", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ status = "okay"; /* u93 and u92 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ status = "okay"; xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ status = "okay"; phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revA"; compatible = "xlnx,versal-vpk120-revA", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk120-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk120 revB * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk120 Eval board revB"; compatible = "xlnx,versal-vpk120-revB", "xlnx,versal-vpk120", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; /* PCIe at MIO 38/39/40/50 */ &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-vpk180-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal vpk180 revA * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Xilinx Versal vpk180 Eval board revA"; compatible = "xlnx,versal-vpk180-revA", "xlnx,versal-vpk180", "xlnx,versal"; chosen { bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused"; stdout-path = "serial0:115200"; }; aliases { serial0 = &serial0; serial2 = &dcc; ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; spi0 = &qspi; usb0 = &usb0; rtc0 = &rtc; }; /* Missing any LED for heartbeat */ }; &qspi { /* PMC_MIO_500 0 - 12 */ num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <35000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; }; &dwc3_0 { /* USB 2.0 host */ dr_mode = "host"; maximum-speed = "high-speed"; /* FIXME */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,usb3_lpm_capable; }; &sdhci1 { /* PMC_MIO_501 26 - 36/51 */ xlnx,mio-bank = <1>; no-1-8-v; clk-phase-sd-hs = <111>, <48>; clk-phase-uhs-sdr25 = <114>, <48>; clk-phase-uhs-ddr50 = <126>, <36>; }; &i2c1 { /* PMC_MIO44/45 */ /* Use for storing information about board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; &gem0 { /* PMC_MIO_48 - reset, LPD_MIO0-11 , mdio LPD_MIO24/25 */ phy-handle = <&phy1>; /* u198 */ phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <0xb>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; &gpio0 { /* FIXME Fill names when versal starts */ }; &gpio1 { /* FIXME Fill names when versal starts */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-01 revA for vck190/vmk180 * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ num-cs = <2>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; #address-cells = <1>; #size-cells = <0>; flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80", "jedec,spi-nor"; /* 256MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <150000000>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x10000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-02 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ /* emmc MIO 0-13 - MTFC8GAKAJCN */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/versal-x-ebm-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx X-EBM-03 revA for vck190/vmk180 * * (C) Copyright 2020-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" /* U97 MT35XU02G */ compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; bus-num = <2>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "mt35xu02g", "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0x0>; cdns,tshsl-ns = <0x0>; cdns,tsd2d-ns = <0x0>; cdns,tchsh-ns = <0x1>; cdns,tslch-ns = <0x1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; no-wp; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_LOW>; partition@0 { label = "spi0-flash0"; reg = <0x0 0x8000000>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; spi0 = &qspi; usb0 = &usb0; }; clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_si5338_3: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_8_grp"; function = "uart0"; }; conf { groups = "uart0_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO34"; bias-high-impedance; }; conf-tx { pins = "MIO35"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; io-standard = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio0_wp_0_grp"; function = "sdio0_wp"; }; conf-wp { groups = "sdio0_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_38_grp"; }; conf { groups = "gpio0_38_grp"; bias-disable; slew-rate = ; io-standard = ; }; }; }; &psgtr { status = "okay"; /* dp, usb3, sata */ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>; clock-names = "ref1", "ref2", "ref3"; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* eMMC */ &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; bus-width = <8>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; usb0 = &usb1; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem2 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem2_default>; phy0: ethernet-phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &nand0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; arasan,has-mdma; nand@0 { reg = <0x0>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; nand@1 { reg = <0x1>; #address-cells = <0x2>; #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; partition@0 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand1-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x0 0x1c00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand1-misc"; reg = <0x0 0x3400000 0xfcc00000>; }; }; }; &pinctrl0 { status = "okay"; pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO38"; bias-high-impedance; }; conf-tx { pins = "MIO39"; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_8_grp"; }; conf { groups = "can1_8_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO33"; bias-high-impedance; }; conf-tx { pins = "MIO32"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_1_grp"; function = "i2c0"; }; conf { groups = "i2c0_1_grp"; bias-pull-up; slew-rate = ; io-standard = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; }; conf { groups = "gpio0_6_grp", "gpio0_7_grp"; slew-rate = ; io-standard = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO41"; bias-high-impedance; }; conf-tx { pins = "MIO40"; bias-disable; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; io-standard = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem2_default: gem2-default { mux { function = "ethernet2"; groups = "ethernet2_0_grp"; }; conf { groups = "ethernet2_0_grp"; slew-rate = ; io-standard = ; }; conf-rx { pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56", "MIO57"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio2"; groups = "mdio2_0_grp"; }; conf-mdio { groups = "mdio2_0_grp"; slew-rate = ; io-standard = ; bias-disable; }; }; pinctrl_nand0_default: nand0-default { mux { groups = "nand0_0_grp"; function = "nand0"; }; conf { groups = "nand0_0_grp"; bias-pull-up; }; mux-ce { groups = "nand0_ce_0_grp"; function = "nand0_ce"; }; conf-ce { groups = "nand0_ce_0_grp"; bias-pull-up; }; mux-rb { groups = "nand0_rb_0_grp"; function = "nand0_rb"; }; conf-rb { groups = "nand0_rb_0_grp"; bias-pull-up; }; mux-dqs { groups = "nand0_dqs_0_grp"; function = "nand0_dqs"; }; conf-dqs { groups = "nand0_dqs_0_grp"; bias-pull-up; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_0_grp"; function = "spi0"; }; conf { groups = "spi0_0_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_0_grp", "spi0_ss_1_grp", "spi0_ss_2_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_3_grp"; function = "spi1"; }; conf { groups = "spi1_3_grp"; bias-disable; slew-rate = ; io-standard = ; }; mux-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_9_grp", "spi1_ss_10_grp", "spi1_ss_11_grp"; bias-disable; }; }; }; &spi0 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { compatible = "sst,sst25wf080", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "spi0-data"; reg = <0x0 0x100000>; }; }; }; &spi1 { num-cs = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "spi1-data"; reg = <0x0 0x84000>; }; }; }; /* ULPI SMSC USB3320 */ &usb1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; }; &dwc3_1 { dr_mode = "host"; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc702.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ #include / { model = "Zynq ZC702 Development Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-14 { label = "sw14"; gpios = <&gpio0 12 0>; linux,code = <108>; /* down */ wakeup-source; autorepeat; }; switch-13 { label = "sw13"; gpios = <&gpio0 14 0>; linux,code = <103>; /* up */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds23 { label = "ds23"; gpios = <&gpio0 10 0>; linux,default-trigger = "heartbeat"; }; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &can0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_default>; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; phy-reset-gpio = <&gpio0 11 0>; phy-reset-active-low; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "right"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; hwmon@34 { compatible = "ti,ucd9248"; reg = <0x34>; }; hwmon@35 { compatible = "ti,ucd9248"; reg = <0x35>; }; hwmon@36 { compatible = "ti,ucd9248"; reg = <0x36>; }; }; }; }; &pinctrl0 { pinctrl_can0_default: can0-default { mux { function = "can0"; groups = "can0_9_grp"; }; conf { groups = "can0_9_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO46"; bias-high-impedance; }; conf-tx { pins = "MIO47"; bias-disable; }; }; pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp", "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14"; bias-pull-up; }; conf-pull-none { pins = "MIO7", "MIO8"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; }; conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { bootph-all; is-dual = <0>; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zc706.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * Copyright (C) 2012 National Instruments Corp. */ / { model = "Zynq ZC706 Development Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; spi0 = &qspi; mmc0 = &sdhci0; }; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; ethernet_phy: ethernet-phy@7 { reg = <7>; device_type = "ethernet-phy"; }; }; &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio0_default>; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0_default>; i2c-mux@74 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; si570: clock-generator@5d { #clock-cells = <0>; compatible = "silabs,si570"; temperature-stability = <50>; reg = <0x5d>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; adv7511: hdmi-tx@39 { compatible = "adi,adv7511"; reg = <0x39>; adi,input-depth = <8>; adi,input-colorspace = "yuv422"; adi,input-clock = "1x"; adi,input-style = <3>; adi,input-justification = "evenly"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ucd90120@65 { compatible = "ti,ucd90120"; reg = <0x65>; }; }; }; }; &pinctrl0 { pinctrl_gem0_default: gem0-default { mux { function = "ethernet0"; groups = "ethernet0_0_grp"; }; conf { groups = "ethernet0_0_grp"; slew-rate = <0>; power-source = <4>; }; conf-rx { pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; low-power-enable; bias-disable; }; mux-mdio { function = "mdio0"; groups = "mdio0_0_grp"; }; conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; }; pinctrl_gpio0_default: gpio0-default { mux { function = "gpio0"; groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; }; conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; power-source = <1>; }; conf-pull-up { pins = "MIO46", "MIO47"; bias-pull-up; }; conf-pull-none { pins = "MIO7"; bias-disable; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_10_grp"; function = "i2c0"; }; conf { groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_2_grp"; function = "sdio0"; }; conf { groups = "sdio0_2_grp"; slew-rate = <0>; power-source = <1>; bias-disable; }; mux-cd { groups = "gpio0_14_grp"; function = "sdio0_cd"; }; conf-cd { groups = "gpio0_14_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; mux-wp { groups = "gpio0_15_grp"; function = "sdio0_wp"; }; conf-wp { groups = "gpio0_15_grp"; bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_10_grp"; function = "uart1"; }; conf { groups = "uart1_10_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO49"; bias-high-impedance; }; conf-tx { pins = "MIO48"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0>; power-source = <1>; }; conf-rx { pins = "MIO29", "MIO31", "MIO36"; bias-high-impedance; }; conf-tx { pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", "MIO35", "MIO37", "MIO38", "MIO39"; bias-disable; }; }; }; &qspi { bootph-all; is-dual = <1>; num-cs = <2>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@c00000 { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { bootph-all; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; }; &watchdog0 { reset-on-timeout; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-reva.dtsi ================================================ / { model = "ZynqMP ZCU100 RevA"; compatible = "xlnx,zynqmp-zcu100-revA", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 39 1>; /* shared with pmic IRQ */ /* uboot: gpio input 39 */ linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO7 */ label = "vbus_det"; gpios = <&gpio 7 0>; default-state = "on"; }; }; clk3_6: clk3_6 { /* for spi uart max3107 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <3600000>; }; ltc2952: ltc2952 { /* U7 */ compatible = "lltc,ltc2952"; status = "disabled"; trigger-gpios = <&gpio 23 1>; /* INT line - input */ watchdog-gpios = <&gpio 24 0>; /* FIXME Bogus - set it up to max3107 */ kill-gpios = <&gpio 25 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&max3107 1 1>; /* WIFI_EN */ }; }; &i2c0 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <39 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* * SYSMON */ }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * EEPROM with globally unique ID (will provide MAC address) */ eeprom@50 { /* u35 - 24aa02E48T */ compatible = "atmel,24c02"; /* 8 blocks 50-57 - works */ reg = <0x50>; /* low 3 bits: don't care */ }; }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 - U5 * 100kHz - this is default freq for us */ /* FIXME 0x2c 0x2d - disabled because of SMBUS */ }; }; }; &qspi { flash@0 { /* single x4 - 16 MB flash at U13 */ compatible = "n25q128a13", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@qspi-fsbl-uboot { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x9E0000>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; xlnx,mio-bank = <0>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; max-frequency = <16000000>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { max3107: max3107@0 { /* I'm assuming no offset...? */ compatible = "maxim,max3107"; spi-max-frequency = <26000000>; reg = <0>; interrupt-parent = <&gpio>; interrupts = <77 8>; clocks = <&clk3_6>; clock-names = "osc"; gpio-controller; #gpio-cells = <2>; }; }; &dwc3_0 { dr_mode = "peripheral"; /* phy-names = "usb3-phy"; phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; &dwc3_1 { dr_mode = "host"; /* phy-names = "usb3-phy"; phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>; */ maximum-speed = "high-speed"; /* super-speed */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-revb.dtsi ================================================ / { model = "ZynqMP ZCU100 RevB"; compatible = "xlnx,zynqmp-zcu100-revB", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; /* shared with pmic IRQ */ linux,code = <108>; /* down */ gpio-key,wakeup; /* FIXME test this */ autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; /* uboot: gpio toggle 20 */ linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; /* FIXME this is not correct - used fixed-regulator for it */ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; ltc2952: ltc2952 { /* U7 */ /* * FIXME this is ltc2954 not ltc2952 - try this driver and * maybe just extend compatible string. */ compatible = "lltc,ltc2954", "lltc,ltc2952"; trigger-gpios = <&gpio 26 1>; /* INT line - input */ /* If there is HW watchdog on mezzanine this signal should be connected there */ watchdog-gpios = <&gpio 35 0>; /* FIXME - unconnected MIO pin now */ kill-gpios = <&gpio 34 1>; /* KILL signal - output */ }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &pmufw { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmu_default>; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 0>; sda-gpios = <&gpio 5 0>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { /* i2c mw 75 0 1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ }; i2csw_1: i2c@1 { /* i2c mw 75 0 2 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ }; i2csw_2: i2c@2 { /* i2c mw 75 0 4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ }; i2csw_3: i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ }; i2csw_4: i2c@4 { /* i2c mw 75 0 10 */ #address-cells = <1>; #size-cells = <0>; reg = <0x4>; /* Comment it out because will be pre-programmed at the factory */ pmic: tps65086x@5e { // Custom TI PMIC u33 compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <23 1>; /* shared with pmic IRQ */ #gpio-cells = <2>; gpio-controller; /* sys-supply = <&some_reg>; // spec 12V buck1 5V0 buck2 PSINTLP (no idea) buck3 VCC_PSDDR 1V1 buck4 3V3 buck5 1V2 buck6 VCC_PSAUX 1V8 vin-sm0-supply = <&some_reg>; vin-sm1-supply = <&some_reg>; vin-sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; vinldo678-supply = <...>; vinldo9-supply = <...>; regulators { sys_reg: sys { regulator-name = "vdd_sys"; regulator-boot-on; regulator-always-on; }; sm0_reg: sm0 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm1_reg: sm1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; sm2_reg: sm2 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; ldo0_reg: ldo0 { regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; ldo1_reg: ldo1 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo2_reg: ldo2 { regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; ldo3_reg: ldo3 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo4_reg: ldo4 { regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; ldo5_reg: ldo5 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo6_reg: ldo6 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo7_reg: ldo7 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo8_reg: ldo8 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; ldo9_reg: ldo9 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; // FIXME look at this one ldo_rtc { regulator-name = "vdd_rtc_out,vdd_cell"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; */ }; }; i2csw_5: i2c@5 { /* i2c mw 75 0 20 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { /* i2c mw 75 0 40 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { /* i2c mw 75 0 80 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = <1>; power-source = <1>; }; }; pinctrl_pmu_default: pmu-default { mux { groups = "pmu0_8_grp"; function = "pmu0"; }; conf { groups = "pmu0_8_grp"; bias-pull-up; slew-rate = <1>; power-source = <1>; }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &dwc3_0 { dr_mode = "peripheral"; phy-names = "usb3-phy"; phys = <&lane2 4 0 0 26000000>; maximum-speed = "super-speed"; }; &dwc3_1 { dr_mode = "host"; phy-names = "usb3-phy"; phys = <&lane3 4 1 0 26000000>; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; usb0 = &usb0; usb1 = &usb1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; iio-hwmon { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; led-vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; si5335_0: si5335_0 { /* clk0_usb - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; si5335_1: si5335_1 { /* clk1_dp - u23 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 IRQ_TYPE_LEVEL_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ u35: ina226@40 { /* u35 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_1_grp"; function = "i2c1"; }; conf { groups = "i2c1_1_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; }; conf { groups = "gpio0_4_grp", "gpio0_5_grp"; slew-rate = ; power-source = ; }; }; pinctrl_sdhci0_default: sdhci0-default { mux { groups = "sdio0_3_grp"; function = "sdio0"; }; conf { groups = "sdio0_3_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio0_cd_0_grp"; function = "sdio0_cd"; }; conf-cd { groups = "sdio0_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_2_grp"; function = "sdio1"; }; conf { groups = "sdio1_2_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_spi0_default: spi0-default { mux { groups = "spi0_3_grp"; function = "spi0"; }; conf { groups = "spi0_3_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi0_ss_9_grp"; function = "spi0_ss"; }; conf-cs { groups = "spi0_ss_9_grp"; bias-disable; }; }; pinctrl_spi1_default: spi1-default { mux { groups = "spi1_0_grp"; function = "spi1"; }; conf { groups = "spi1_0_grp"; bias-disable; slew-rate = ; power-source = ; }; mux-cs { groups = "spi1_ss_0_grp"; function = "spi1_ss"; }; conf-cs { groups = "spi1_ss_0_grp"; bias-disable; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_0_grp"; function = "uart0"; }; conf { groups = "uart0_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO3"; bias-high-impedance; }; conf-tx { pins = "MIO2"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_0_grp"; function = "uart1"; }; conf { groups = "uart1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO1"; bias-high-impedance; }; conf-tx { pins = "MIO0"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_usb1_default: usb1-default { mux { groups = "usb1_0_grp"; function = "usb1"; }; conf { groups = "usb1_0_grp"; power-source = ; }; conf-rx { pins = "MIO64", "MIO65", "MIO67"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &psgtr { /* usb3, dp */ clocks = <&si5335_0>, <&si5335_1>; clock-names = "ref0", "ref1"; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; /* ULPI SMSC USB3320 */ &usb0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; /delete-property/ reset-gpios; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "super-speed"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; }; &dwc3_1 { dr_mode = "host"; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-revb.dtsi" / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3", "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "", "", "", "", "", "", "", "", ""; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS", "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN", "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN", "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", ""; }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 FIXME - not detected */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_4: out@4 { /* refclk4 for PS-GT, used for PCIE slot */ reg = <4>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 for PS-GT, used for PCIE */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf-sw { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22", "MIO23"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO38"; bias-disable; }; }; }; &psgtr { /* pcie, sata, usb3, dp */ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref0", "ref1", "ref2", "ref3"; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zcu102-reva.dtsi" / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; }; &gem3 { phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; /* Cleanup from RevA */ /delete-node/ ethernet-phy@21; }; }; /* Fix collision with u61 */ &i2c0 { i2c-mux@75 { i2c@2 { max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; /delete-node/ max15303@20; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu104-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU104 RevC"; compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; ina226 { compatible = "iio-hwmon"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clock_8t49n287_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clock_8t49n287_3: clk27 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* 8T49N287 - u182 */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x43>; /* pmbus / i2c 0x13 */ }; irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ compatible = "infineon,irps5401"; reg = <0x44>; /* pmbus / i2c 0x14 */ }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; u183: ina226@40 { /* u183 */ compatible = "ti,ina226"; #io-channel-cells = <1>; reg = <0x40>; shunt-resistor = <5000>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 4, 6 not connected */ }; }; &pinctrl0 { status = "okay"; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; drive-strength = <12>; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { no-1-8-v; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; xlnx,mio-bank = <1>; disable-wp; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u76 { compatible = "iio-hwmon"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; refhdmi: refhdmi { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <114285000>; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_default>; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ u76: ina226@40 { /* u76 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u76"; reg = <0x40>; shunt-resistor = <5000>; }; u77: ina226@41 { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x41>; shunt-resistor = <5000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u87: ina226@43 { /* u87 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u87"; reg = <0x43>; shunt-resistor = <5000>; }; u85: ina226@44 { /* u85 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u85"; reg = <0x44>; shunt-resistor = <5000>; }; u86: ina226@45 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u86"; reg = <0x45>; shunt-resistor = <5000>; }; u93: ina226@46 { /* u93 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u93"; reg = <0x46>; shunt-resistor = <5000>; }; u88: ina226@47 { /* u88 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u88"; reg = <0x47>; shunt-resistor = <5000>; }; u15: ina226@4a { /* u15 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u15"; reg = <0x4a>; shunt-resistor = <5000>; }; u92: ina226@4b { /* u92 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u92"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ u79: ina226@40 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x40>; shunt-resistor = <2000>; }; u81: ina226@41 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u81"; reg = <0x41>; shunt-resistor = <5000>; }; u80: ina226@42 { /* u80 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u80"; reg = <0x42>; shunt-resistor = <5000>; }; u84: ina226@43 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x43>; shunt-resistor = <5000>; }; u16: ina226@44 { /* u16 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u16"; reg = <0x44>; shunt-resistor = <5000>; }; u65: ina226@45 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x45>; shunt-resistor = <5000>; }; u74: ina226@46 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x46>; shunt-resistor = <5000>; }; u75: ina226@47 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_7: out@7 { /* refclk7 PL CLK74 */ reg = <7>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ compatible = "silabs,si5328"; reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; clocks = <&refhdmi>; clock-names = "xtal"; clock-output-names = "si5328"; si5328_clk: clk0@0 { reg = <0>; clock-frequency = <27000000>; }; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_uart1_default: uart1-default { mux { groups = "uart1_5_grp"; function = "uart1"; }; conf { groups = "uart1_5_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO21"; bias-high-impedance; }; conf-tx { pins = "MIO20"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_can1_default: can1-default { mux { function = "can1"; groups = "can1_6_grp"; }; conf { groups = "can1_6_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO25"; bias-high-impedance; }; conf-tx { pins = "MIO24"; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, sata, usb3, dp */ clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-u67 { compatible = "iio-hwmon"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &gem3 { phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_default>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ u67: ina226@40 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u67"; reg = <0x40>; shunt-resistor = <2000>; }; u59: ina226@41 { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u59"; reg = <0x41>; shunt-resistor = <5000>; }; u61: ina226@42 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u61"; reg = <0x42>; shunt-resistor = <5000>; }; u60: ina226@43 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u60"; reg = <0x43>; shunt-resistor = <5000>; }; u64: ina226@45 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u64"; reg = <0x45>; shunt-resistor = <5000>; }; u69: ina226@46 { /* u69 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u69"; reg = <0x46>; shunt-resistor = <2000>; }; u66: ina226@47 { /* u66 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u66"; reg = <0x47>; shunt-resistor = <5000>; }; u65: ina226@48 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u65"; reg = <0x48>; shunt-resistor = <5000>; }; u63: ina226@49 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u63"; reg = <0x49>; shunt-resistor = <5000>; }; u3: ina226@4a { /* u3 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u3"; reg = <0x4a>; shunt-resistor = <5000>; }; u71: ina226@4b { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u71"; reg = <0x4b>; shunt-resistor = <5000>; }; u77: ina226@4c { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u77"; reg = <0x4c>; shunt-resistor = <5000>; }; u73: ina226@4d { /* u73 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u73"; reg = <0x4d>; shunt-resistor = <5000>; }; u79: ina226@4e { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */ compatible = "infineon,irps5401"; reg = <0x43>; }; irps5401_44: irps5401@44 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x44>; }; irps5401_45: irps5401@45 { /* IRPS5401 - u57 */ compatible = "infineon,irps5401"; reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_0: out@0 { /* refclk0 for PS-GT, used for DP */ reg = <0>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user"; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SI5382 - u48 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { /* i2c mw 75 0 8 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ dev@19 { /* u-boot detection FIXME */ compatible = "xxx"; reg = <0x19>; }; dev@30 { /* u-boot detection */ compatible = "xxx"; reg = <0x30>; }; dev@35 { /* u-boot detection */ compatible = "xxx"; reg = <0x35>; }; dev@36 { /* u-boot detection */ compatible = "xxx"; reg = <0x36>; }; dev@51 { /* u-boot detection - maybe SPD */ compatible = "xxx"; reg = <0x51>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; pinctrl_uart0_default: uart0-default { mux { groups = "uart0_4_grp"; function = "uart0"; }; conf { groups = "uart0_4_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO18"; bias-high-impedance; }; conf-tx { pins = "MIO19"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; power-source = ; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; drive-strength = <12>; slew-rate = ; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; drive-strength = <4>; slew-rate = ; }; }; pinctrl_gem3_default: gem3-default { mux { function = "ethernet3"; groups = "ethernet3_0_grp"; }; conf { groups = "ethernet3_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", "MIO75"; bias-high-impedance; low-power-disable; }; conf-tx { pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", "MIO69"; bias-disable; low-power-enable; }; mux-mdio { function = "mdio3"; groups = "mdio3_0_grp"; }; conf-mdio { groups = "mdio3_0_grp"; slew-rate = ; power-source = ; bias-disable; }; }; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_gpio_default: gpio-default { mux { function = "gpio0"; groups = "gpio0_22_grp", "gpio0_23_grp"; }; conf { groups = "gpio0_22_grp", "gpio0_23_grp"; slew-rate = ; power-source = ; }; mux-msp { function = "gpio0"; groups = "gpio0_13_grp", "gpio0_38_grp"; }; conf-msp { groups = "gpio0_13_grp", "gpio0_38_grp"; slew-rate = ; power-source = ; }; conf-pull-up { pins = "MIO22"; bias-pull-up; }; conf-pull-none { pins = "MIO13", "MIO23", "MIO38"; bias-disable; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &psgtr { /* nc, dp, usb3, sata */ clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref1", "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0_default>; }; /* ULPI SMSC USB3320 */ &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1275 RevA"; compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1275-revb.dtsi ================================================ /* * dts file for Xilinx ZynqMP ZCU1275 RevB * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu * * SPDX-License-Identifier: GPL-2.0+ */ / { model = "ZynqMP ZCU1275 RevB"; compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@100000 { /* for testing purpose */ label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@600000 { /* for testing purpose */ label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@620000 { /* for testing purpose */ label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; }; }; &sdhci1 { /* * 1.0 revision has level shifter and this property should be * removed for supporting UHS mode */ no-1-8-v; }; &gem1 { mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu1285-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU1285 RevA * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZCU1285 RevA"; compatible = "xlnx,zynqmp-zcu1285-revA", "xlnx,zynqmp-zcu1285", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; mmc0 = &sdhci1; ethernet0 = &gem1; /* EMIO */ i2c = &i2c0; /* EMIO */ }; }; &dcc { status = "okay"; }; &i2c0 { clock-frequency = <400000>; }; &gem1 { mdio { phy1: ethernet-phy@1 { reg = <1>; /* KSZ9031RNXIC on AES-FMC-NETW1-G */ rxc-skew-ps = <1800>; /* Skew control of RX_CLK pad output */ txc-skew-ps = <1800>; /* Skew control of GTX_CLK pad input */ txen-skew-ps = <900>; /* Skew control of TX_CTL pad input */ rxdv-skew-ps = <0>; /* Skew control of RX_CTL pad output */ rxd0-skew-ps = <0>; /* Skew control of RXD0 pad output */ rxd1-skew-ps = <0>; /* Skew control of RXD1 pad output */ rxd2-skew-ps = <0>; /* Skew control of RXD2 pad output */ rxd3-skew-ps = <0>; /* Skew control of RXD3 pad output */ txd0-skew-ps = <900>; /* Skew control of TXD0 pad input */ txd1-skew-ps = <900>; /* Skew control of TXD1 pad input */ txd2-skew-ps = <900>; /* Skew control of TXD2 pad input */ txd3-skew-ps = <900>; /* Skew control of TXD3 pad input */ }; }; }; &qspi { flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sdhci1 { /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu208-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU208 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU208 RevA"; compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu216-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU216 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU216 RevA"; compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; }; &psgtr { /* nc, nc, usb3, sata */ clocks = <&si5341 0 2>, <&si5341 0 3>; clock-names = "ref2", "ref3"; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "", "", "", /* 25 - 29 */ "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */ "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5341: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u43 */ compatible = "silabs,si5341"; reg = <0x36>; #clock-cells = <2>; #address-cells = <1>; #size-cells = <0>; clocks = <&ref48>; clock-names = "xtal"; clock-output-names = "si5341"; si5341_2: out@2 { /* refclk2 for PS-GT, used for USB3 */ reg = <2>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_3: out@3 { /* refclk3 for PS-GT, used for SATA */ reg = <3>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_5: out@5 { /* refclk5 PL CLK100 */ reg = <5>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_6: out@6 { /* refclk6 PL CLK125 */ reg = <6>; always-on; /* assigned-clocks does not enable, so do it here */ }; si5341_9: out@9 { /* refclk9 used for PS_REF_CLK 33.3 MHz */ reg = <9>; always-on; /* assigned-clocks does not enable, so do it here */ }; }; }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u409B */ reg = <0x5b>; }; }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_user_c1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c1"; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* MSP430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; &sata { /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; phy-names = "sata-phy"; phys = <&psgtr 3 PHY_TYPE_SATA 1 3>; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; xlnx,mio-bank = <1>; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; maximum-speed = "super-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu670-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR), ZCU670-LD (57DR) * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevA"; compatible = "xlnx,zynqmp-zcu670-revA", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zcu670-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP ZCU670 RevB"; compatible = "xlnx,zynqmp-zcu670-revB", "xlnx,zynqmp-zcu670", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; }; gpio-keys { compatible = "gpio-keys"; autorepeat; switch-1 { label = "sw1"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; /* DS1 */ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram-ps { compatible = "iio-hwmon"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; /* 48MHz reference crystal */ ref48: ref48M { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; }; si5381_6: si5381_6 { /* refclk_usb3 - u43 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; }; }; }; &gpio { gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */ "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */ "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */ "", "", "BUTTON", "LED", "", /* 20 - 24 */ "", "PMU_INPUT", "SFP3_TX_DISABLE", "SFP2_TX_DISABLE", "SFP1_TX_DISABLE", /* 25 - 29 */ "SFP0_TX_DISABLE", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */ "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */ "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "SD_PWR_RST", "", /* 40 - 44 */ "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */ "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */ "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */ "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */ "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */ "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */ "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */ "SI5381_INT_ALM", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */ "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */ }; i2c-mux@75 { /* u17 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <5000>; }; vccint_io_bram_ps: ina226@41 { /* u57 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-io-bram-ps"; reg = <0x41>; shunt-resistor = <5000>; }; vcc1v8: ina226@42 { /* u60 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v8"; reg = <0x42>; shunt-resistor = <2000>; }; vcc1v2: ina226@43 { /* u58 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2"; reg = <0x43>; shunt-resistor = <5000>; }; vadj_fmc: ina226@45 { /* u62 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavcc: ina226@46 { /* u67 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtavcc"; reg = <0x46>; shunt-resistor = <2000>; }; mgt1v2: ina226@47 { /* u63 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v2"; reg = <0x47>; shunt-resistor = <5000>; /* Not in schematics */ }; mgt1v8: ina226@48 { /* u64 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgt1v8"; reg = <0x48>; shunt-resistor = <5000>; }; vccint_ams: ina226@49 { /* u61 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint-ams"; reg = <0x49>; shunt-resistor = <5000>; }; dac_avtt: ina226@4a { /* u59 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avtt"; reg = <0x4a>; shunt-resistor = <5000>; }; dac_avccaux: ina226@4b { /* u124 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avccaux"; reg = <0x4b>; shunt-resistor = <5000>; }; adc_avcc: ina226@4c { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avcc"; reg = <0x4c>; shunt-resistor = <5000>; }; adc_avccaux: ina226@4d { /* u71 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-adc-avccaux"; reg = <0x4d>; shunt-resistor = <5000>; }; dac_avcc: ina226@4e { /* u77 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-dac-avcc"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u104 - ir35215 0x10/0x40 */ /* u127 - ir38164 0x1b/0x4b */ /* u112 - ir38164 0x13/0x43 */ /* u123 - ir38164 0x1c/0x4c */ irps5401_44: irps5401@44 { /* IRPS5401 - u53 */ compatible = "infineon,irps5401"; reg = <0x44>; /* i2c addr 0x14 */ }; irps5401_45: irps5401@45 { /* IRPS5401 - u55 */ compatible = "infineon,irps5401"; reg = <0x45>; /* i2c addr 0x15 */ }; /* J21 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; /* u38 MPS430 */ }; &i2c1 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c_eeprom: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u21 */ compatible = "atmel,24c128"; reg = <0x54>; }; }; i2c_si5381: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SI5381 - u43 */ /*si5381: clock-generator@68 { reg = <0x68>; };*/ }; i2c_si570_user_c0: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; clock-output-names = "si570_user_c0"; }; }; i2c_si570_mgt: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; i2c_8a34001: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* U409B - 8a34001 */ }; i2c_clk104: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* CLK104_SDA */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* RFMCP connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u22 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c_si570_psrefclk: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si570_3: clock-generator@5d { /* USER SI570 PSREFCLK - u130 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "si570_ps_ref_clk"; silabs,skip-recall; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; /* u38 MPS430 */ }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_3_grp"; function = "i2c0"; }; conf { groups = "i2c0_3_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; }; conf { groups = "gpio0_14_grp", "gpio0_15_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_4_grp"; function = "i2c1"; }; conf { groups = "i2c1_4_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; }; conf { groups = "gpio0_16_grp", "gpio0_17_grp"; slew-rate = ; power-source = ; }; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 2Gb */ #address-cells = <1>; #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; }; /* SD1 with level shifter */ &sdhci1 { disable-wp; /* * This property should be removed for supporting UHS mode */ no-1-8-v; xlnx,mio-bank = <1>; clk-phase-sd-hs = <120>, <60>; clk-phase-uhs-sdr25 = <132>, <60>; clk-phase-uhs-ddr50 = <153>, <48>; }; &psgtr { /* hspc_dp4, hspc_dp5, usb3, hspc_dp6 */ clocks = <&si5381_6>; clock-names = "ref2"; }; /* ULPI SMSC USB3320 */ &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; }; &dwc3_0 { dr_mode = "host"; snps,usb3_lpm_capable; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zedboard.dtsi ================================================ / { model = "Zynq Zed Development Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; usb_phy0: phy0@e0002000 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &clkc { ps-clk-frequency = <33333333>; }; &gem0 { phy-handle = <ðernet_phy>; ethernet_phy: ethernet-phy@0 { reg = <0>; device_type = "ethernet-phy"; }; }; &qspi { bootph-all; num-cs = <1>; flash@0 { compatible = "n25q128a11", "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #address-cells = <1>; #size-cells = <1>; partition@qspi-fsbl-uboot { label = "qspi-fsbl-uboot"; reg = <0x0 0x100000>; }; partition@qspi-linux { label = "qspi-linux"; reg = <0x100000 0x500000>; }; partition@qspi-device-tree { label = "qspi-device-tree"; reg = <0x600000 0x20000>; }; partition@qspi-rootfs { label = "qspi-rootfs"; reg = <0x620000 0x5E0000>; }; partition@qspi-bitstream { label = "qspi-bitstream"; reg = <0xC00000 0x400000>; }; }; }; &sdhci0 { bootph-all; }; &uart1 { bootph-all; }; &usb0 { dr_mode = "host"; usb-phy = <&usb_phy0>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-a2197-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "Versal System Controller on a2197 board RevA"; compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; nvmem0 = &eeprom1; nvmem1 = &eeprom0; serial0 = &uart0; }; }; &i2c0 { bootph-all; clock-frequency = <400000>; i2c-mux@74 { /* this cover MGT board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; bootph-all; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; bootph-all; reg = <0x50>; }; }; }; }; &i2c1 { bootph-all; clock-frequency = <400000>; i2c-mux@74 { /* This cover processor board */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; bootph-all; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; bootph-all; reg = <0x50>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-e-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_ebm; nvmem2 = &eeprom_fmc1; nvmem3 = &eeprom_fmc2; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; ref_clk: ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; si570_ddrdimm1_clk: si570-ddrdimm1-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; si570_lpddr4_clk2: si570-lpddr4-clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk2>; }; si570_lpddr4_clk1: si570-lpddr4-clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4clk1>; }; si570_hsdp_clk: si570-hsdp-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si570_zsfp_clk: si570-zsfp-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_zsfp>; }; si570_user1_clk: si570-user1-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_user1>; }; si5332_1: si5332_1 { /* u142 - GEM0 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; /* GEM SGMII */ &psgtr { status = "okay"; /* gem0 */ clocks = <&si5332_1>; clock-names = "ref0"; }; &gem0 { phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { /* u131 M88E1512 */ reg = <0>; }; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULLSPD", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* u152 IR35215 0x16/0x46 vcc_soc */ /* u179 ir38164 0x19/0x49 vcco_500 */ /* u181 ir38164 0x1a/0x4a vcco_501 */ /* u183 ir38164 0x1b/0x4b vcco_502 */ /* u185 ir38164 0x1e/0x4e vadj_fmc */ /* u187 ir38164 0x1F/0x4f mgtyavcc */ /* u189 ir38164 0x20/0x50 mgtyavtt */ /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */ /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* pmbus / i2c 0x17 */ }; irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* pmbus / i2c 0x1c */ }; irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* pmbus / i2c 0x1d */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; shunt-resistor = <500>; /* R440 */ /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; shunt-resistor = <500>; /* R1702 */ /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pmc"; reg = <0x42>; shunt-resistor = <5000>; /* R1214 */ /* 0.78V @ 500mA */ }; vcc_ram: ina226@43 { /* u162 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; /* r1221 */ /* 0.78V @ 4A */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-pslp"; reg = <0x44>; shunt-resistor = <5000>; /* R1216 */ /* 0.78V @ 1A */ }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-psfp"; reg = <0x45>; shunt-resistor = <5000>; /* R1219 */ /* 0.78V @ 2A */ }; }; i2c@2 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* u39 8T49N240 */ }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux"; reg = <0x40>; shunt-resistor = <5000>; /* R382 */ /* 1.5V @ 3A */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vccaux-pmc"; reg = <0x41>; shunt-resistor = <5000>; /* R1246 */ /* 1.5V @ 500mA */ }; vcco_500: ina226@42 { /* u178 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-500"; reg = <0x42>; shunt-resistor = <2000>; /* R1300 */ /* 3.3V @ 5A */ }; vcco_501: ina226@43 { /* u180 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-501"; reg = <0x43>; shunt-resistor = <2000>; /* R1313 */ /* 3.3V @ 5A */ }; vcco_502: ina226@44 { /* u182 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-502"; reg = <0x44>; shunt-resistor = <2000>; /* R1330 */ /* 3.3V @ 5A */ }; vcco_503: ina226@45 { /* u172 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcco-503"; reg = <0x45>; shunt-resistor = <5000>; /* R1229 */ /* 1.8V @ 2A */ }; vcc_1v8: ina226@46 { /* u173 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v8"; reg = <0x46>; shunt-resistor = <5000>; /* R400 */ /* 1.8V @ 6A */ }; vcc_3v3: ina226@47 { /* u174 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-3v3"; reg = <0x47>; shunt-resistor = <5000>; /* R1232 */ /* 3.3V @ 500mA */ }; vcc_1v2_ddr4: ina226@48 { /* u176 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-1v2-ddr4"; reg = <0x48>; shunt-resistor = <5000>; /* R1275 */ /* 1.2V @ 4A */ }; vcc1v1_lp4: ina226@49 { /* u177 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x49>; shunt-resistor = <5000>; /* R1286 */ /* 1.1V @ 4A */ }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vadj-fmc"; reg = <0x4a>; shunt-resistor = <2000>; /* R1350 */ /* 1.5V @ 10A */ }; mgtyavcc: ina226@4b { /* u186 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavcc"; reg = <0x4b>; shunt-resistor = <2000>; /* R1367 */ /* 0.88V @ 6A */ }; mgtyavtt: ina226@4c { /* u188 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyavtt"; reg = <0x4c>; shunt-resistor = <2000>; /* R1384 */ /* 1.2V @ 10A */ }; mgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-mgtyvccaux"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ /* 1.5V @ 500mA */ }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* FIXME wires ready but chip is missing */ }; i2c@5 { /* zSFP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_zsfp: clock-generator@5d { /* u192 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_zsfp_clk"; silabs,skip-recall; }; }; i2c@6 { /* USER_SI570_1 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_user1: clock-generator@5f { /* u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; /* FIXME check address */ temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "si570_user1"; silabs,skip-recall; }; }; i2c@7 { /* USER_SI570_2 */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* FIXME wires ready but chip is missing */ }; }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* 0x5c too */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* and connector J212D */ eeprom_ebm: eeprom@52 { /* x-ebm module */ compatible = "st,24c128", "atmel,24c128"; reg = <0x52>; }; }; fmc1: i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc1: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; fmc2: i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 FMC cards */ eeprom_fmc2: eeprom@50 { compatible = "st,24c128", "atmel,24c128"; reg = <0x50>; }; }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; silabs,skip-recall; }; }; i2c@4 { /* LPDDR4_SI570_CLK2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_lpddr4clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk2"; silabs,skip-recall; }; }; i2c@5 { /* LPDDR4_SI570_CLK1 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4clk1: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk1"; silabs,skip-recall; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; silabs,skip-recall; }; }; i2c@7 { /* 8A34001 - U219B and J310 connector */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2c-mux@75 { /* u214 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c-mux-idle-disconnect; i2c@0 { /* SFP0_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* SFP0 */ }; i2c@1 { /* SFP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* SFP1 */ }; i2c@2 { /* QSFP1_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* QSFP1 */ }; /* 3 - 7 unused */ }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-e-a2197-00-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevB System Controller * * (C) Copyright 2019-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-e-a2197-00-reva.dtsi" / { model = "Versal System Controller on a2197 Eval board RevB"; /* VCK190/VMK180 */ compatible = "xlnx,zynqmp-e-a2197-00-revB", "xlnx,zynqmp-a2197-revB", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; /delete-node/ ina226-vcco-500; /delete-node/ ina226-vcco-501; /delete-node/ ina226-vcco-502; }; &i2c0 { i2c-mux@74 { /* u33 */ i2c@2 { /* PCIE_CLK */ /delete-node/ clock-generator@6c; }; i2c@3 { /* PMBUS2_INA226 */ /delete-node/ ina226@42; /delete-node/ ina226@43; /delete-node/ ina226@44; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-g-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller on MGT * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 MGT Char board RevA"; compatible = "xlnx,zynqmp-g-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; mmc0 = &sdhci0; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; usb0 = &usb0; }; ina226-u74 { compatible = "iio-hwmon"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; &sdhci0 { /* emmc MIO 13-23 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &gem0 { /* eth MDIO 76/77 */ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; phy0: ethernet-phy@0 { /* marwell m88e1512 */ reg = <0>; reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>; }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "", "", "", /* 5 - 9 */ "", "", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "", "", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@50 { /* u96 - 24LC32A - 256B */ compatible = "atmel,24c32"; reg = <0x50>; }; }; i2c@1 { /* CM_I2C_SCL - Samtec */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* PMBUS - AFX_PMBUS */ #address-cells = <1>; #size-cells = <0>; reg = <2>; tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; tps544@10 { /* u73 */ compatible = "ti,tps544b25"; reg = <0x10>; }; tps544@11 { /* u76 */ compatible = "ti,tps544b25"; reg = <0x11>; }; tps544@12 { /* u77 */ compatible = "ti,tps544b25"; reg = <0x12>; }; tps544@13 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x13>; }; tps544@14 { /* u81 */ compatible = "ti,tps544b25"; reg = <0x14>; }; tps544@15 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x15>; }; tps544@16 { /* u63 */ compatible = "ti,tps544b25"; reg = <0x16>; }; tps544@17 { /* u66 */ compatible = "ti,tps544b25"; reg = <0x17>; }; tps544@18 { /* u67 */ compatible = "ti,tps544b25"; reg = <0x18>; }; tps544@19 { /* u69 */ compatible = "ti,tps544b25"; reg = <0x19>; }; tps544@1d { /* u88 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; tps544@1e { /* u89 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; tps544@1f { /* u87 */ compatible = "ti,tps544b25"; reg = <0x1f>; }; tps544@20 { /* u71 */ compatible = "ti,tps544b25"; reg = <0x20>; }; u74: ina226@40 { /* u74 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u74"; reg = <0x40>; shunt-resistor = <1000>; }; u75: ina226@41 { /* u75 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u75" reg = <0x41>; shunt-resistor = <1000>; }; u78: ina226@42 { /* u78 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u78"; reg = <0x42>; shunt-resistor = <5000>; }; u79: ina226@43 { /* u79 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u79"; reg = <0x43>; shunt-resistor = <1000>; }; u82: ina226@44 { /* u82 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u82"; reg = <0x44>; shunt-resistor = <1000>; }; u84: ina226@45 { /* u84 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-u84"; reg = <0x45>; shunt-resistor = <5000>; }; tps53681@60 { /* u53- 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; }; i2c@3 { /* fmc1 via JA2G */ #address-cells = <1>; #size-cells = <0>; reg = <3>; eeprom_fmc1: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@4 { /* fmc2 via JA3G */ #address-cells = <1>; #size-cells = <0>; reg = <4>; eeprom_fmc2: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@5 { /* fmc3 via JA4G */ #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom_fmc3: eeprom@50 { /* on FMC */ compatible = "atmel,24c04"; reg = <0x50>; }; }; i2c@6 { /* ddr dimm */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 7 unused */ }; }; &dwc3_0 { dr_mode = "peripheral"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { reg = <0>; }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; vcc0v6_lp4: ina226@49 { /* u101 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc0v6-lp4"; reg = <0x49>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_LP4_SI570_CLK"; }; }; i2c@3 { /* C1_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@5d { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_LP4_SI570_CLK"; }; }; i2c@4 { /* C2_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_LP4_SI570_CLK"; }; }; i2c@5 { /* C3_LP4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-02-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; abel = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* C0_DDR4_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { /* C2_DDR5_RDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { /* C3_DDR4_UDIMM */ #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_RLD3 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_RLD3_SI570_CLK"; }; }; i2c@4 { /* C2_DDR5 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_DDR5_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-m-a2197-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "Versal System Controller on a2197 Memory Char board RevA"; compatible = "xlnx,zynqmp-m-a2197-03-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; spi0 = &qspi; }; ina226-vcc-aux { compatible = "iio-hwmon"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; }; &qspi { num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; /* FIXME tap delay */ }; &sdhci1 { /* sd1 MIO45-51 cd in place */ status = "disable"; no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */ reg = <0>; /* xlnx,phy-type = ; */ }; /* phy-names = "..."; phys = <&lane0 PHY_TYPE_SGMII ... > Note: lane0 sgmii/lane1 usb3 */ }; &gpio { gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", "", "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u46 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */ i2c@0 { /* PMBUS must be enabled via SW21 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; reg_vcc1v2_lp4: tps544@15 { /* u97 */ compatible = "ti,tps544b25"; reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u95 */ compatible = "ti,tps544b25"; reg = <0x16>; }; reg_vdd1_1v8_lp4: tps544@17 { /* u99 */ compatible = "ti,tps544b25"; reg = <0x17>; }; /* UTIL_PMBUS connection */ reg_vcc1v8: tps544@13 { /* u92 */ compatible = "ti,tps544b25"; reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u93 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_vcc5v0: tps544@1e { /* u94 */ compatible = "ti,tps544b25"; reg = <0x1e>; }; reg_vcc1v2_ddr4: tps544@18 { /* u3022 */ compatible = "ti,tps544b25"; reg = <0x18>; }; }; i2c@1 { /* PMBUS_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; vcc_aux: ina226@42 { /* u86 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-aux"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u81 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-ram"; reg = <0x43>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@46 { /* u96 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v1-lp4"; reg = <0x46>; shunt-resistor = <5000>; }; vcc1v2_lp4: ina226@47 { /* u98 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc1v2-lp4"; reg = <0x47>; shunt-resistor = <5000>; }; vdd1_1v8_lp4: ina226@48 { /* u100 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vdd1-1v8-lp4"; reg = <0x48>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ compatible = "ti,tps544b25"; reg = <0x7>; }; reg_vcc_ram: tps544@8 { /* u82 */ compatible = "ti,tps544b25"; reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u83 */ compatible = "ti,tps544b25"; reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u84 */ compatible = "ti,tps544b25"; reg = <0xa>; }; reg_vccaux: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_vccaux_pmc: tps544@e { /* u87 */ compatible = "ti,tps544b25"; reg = <0xe>; }; reg_vcco_500: tps544@f { /* u88 */ compatible = "ti,tps544b25"; reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u89 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u90 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u91 */ compatible = "ti,tps544b25"; reg = <0x12>; }; }; i2c@3 { /* MEM PMBUS - FIXME bug in schematics */ #address-cells = <1>; #size-cells = <0>; /* reg = <3>; */ }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to U20G */ }; i2c@5 { /* DDR4_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ /* TODO teensy via U30 PCA9543A bus 1 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u47 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */ compatible = "atmel,24c08"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u26 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "REF_CLK"; /* FIXME */ silabs,skip-recall; }; /* Connection via Samtec U20D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@2 { /* C0_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_c0_ddr4: clock-generator@55 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C0_DD4_SI570_CLK"; }; }; i2c@3 { /* C1_SODIMM */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_c1_lp4: clock-generator@55 { /* u7 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C1_SODIMM_SI570_CLK"; }; }; i2c@4 { /* C2_QDRIV */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_c2_lp4: clock-generator@55 { /* u10 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C2_QDRIV_SI570_CLK"; }; }; i2c@5 { /* C3_DDR4 */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_c3_lp4: clock-generator@55 { /* u15 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x55>; temperature-stability = <50>; factory-fout = <30000000>; clock-frequency = <30000000>; clock-output-names = "C3_LP4_SI570_CLK"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u19 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "HSDP_SI570"; }; }; }; }; &dwc3_0 { dr_mode = "host"; /* dr_mode = "peripheral"; */ maximum-speed = "high-speed"; }; &usb1 { status = "disabled"; /* not at mem board */ }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-01-revA", "xlnx,zynqmp-x-prc-01", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681","ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-02 revA (SE2) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-02-revA", "xlnx,zynqmp-x-prc-02", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-03 revA (SE3) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-03-revA", "xlnx,zynqmp-x-prc-03", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; x_prc_si5338: clock-generator@70 { /* U9 */ compatible = "silabs,si5338"; reg = <0x70>; /* FIXME */ }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-04 revA (SE4) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-04-revA", "xlnx,zynqmp-x-prc-04", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5) * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05", "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; ref_clk: ref_clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4_dimm1_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4_dimm2_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp_si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 174 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; /* Connection via Samtec J212D */ /* Use for storing information about X-PRC card */ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */ compatible = "atmel,24c02"; reg = <0x52>; }; /* Use for setting up certain features on X-PRC card */ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */ compatible = "nxp,pca9534"; reg = <0x22>; gpio-controller; /* IRQ not connected */ #gpio-cells = <2>; gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4", "", "", "", ""; gtr-sel0 { gpio-hog; gpios = <0 0>; input; /* FIXME add meaning */ line-name = "sw4_1"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; input; /* FIXME add meaning */ line-name = "sw4_2"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; input; /* FIXME add meaning */ line-name = "sw4_3"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; input; /* FIXME add meaning */ line-name = "sw4_4"; }; }; si570_gem_tsu: clock-generator@5d { /* u164 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; /* FIXME */ clock-frequency = <300000000>; clock-output-names = "si570_gem_tsu_clk"; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater */ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ reg = <0xd8>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ }; }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-p-a2197-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal a2197 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" / { model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */ compatible = "xlnx,zynqmp-p-a2197-00-revA", "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; usb0 = &usb0; usb1 = &usb1; }; ref_clk: ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ref_clk>; }; ddr4_dimm1_si570: ddr4-dimm1-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm1>; }; ddr4_dimm2_si570: ddr4-dimm2-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_ddr_dimm2>; }; lpddr4_si570: lpddr4-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_lpddr4>; }; hsdp_si570: hsdp-si570 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&si570_hsdp>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &sdhci1 { /* sd1 MIO45-51 cd in place */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "", "", "", "", "", /* 0 - 4 */ "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */ "DC_SYS_CTRL3", "DC_SYS_CTRL4", "DC_SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "SYSCTLR_POWER_EN", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "SYSCTLR_LP_I2C_SM_ALERT", /* 85 -89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "SYSCTLR_VCC_RAM_EN", "SYSCTLR_VCC_PSLP_EN", "SYSCTLR_VCC_PSFP_EN", "SYSCTLR_VCCAUX_EN", "SYSCTLR_VCCAUX_PMC_EN", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ "SYSCTLR_VCC3V3_EN", "SYSCTLR_VCC1V2_DDR4_EN", "SYSCTLR_VCC1V1_LP4_EN", "SYSCTLR_VDD1_1V8_LP4_EN", "SYSCTLR_VADJ_FMC_EN", /* 115 - 119 */ "SYSCTLR_MGTYAVCC_EN", "SYSCTLR_MGTYAVTT_EN", "SYSCTLR_MGTYVCCAUX_EN", "SYSCTLR_UTIL_1V13_EN", "SYSCTLR_UTIL_1V8_EN", /* 120 - 124 */ "SYSCTLR_UTIL_2V5_EN", "FMCP1_FMC_PRSNT_M2C_B", "FMCP2_FMC_PRSNT_M2C_B", "FMCP1_FMCP_PRSNT_M2C_B", "FMCP2_FMCP_PRSNT_M2C_B", /* 125 - 129 */ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "SYSCTLR_USBC_SBU1", "SYSCTLR_USBC_SBU2", "TI_CABLE1", /* 130 - 134 */ "TI_CABLE2", "SYSCTLR_MIC2005_EN_B", "SYSCTLR_MIC2005_FAULT_B", "SYSCTLR_TUSB320_INT_B", "SYSCTLR_TUSB320_ID", /* 135 - 139 */ "PMBUS1_ALERT", "PMBUS2_ALERT", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ i2c@0 { /* PMBUS1 */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J98 */ reg_vcc_fmc: tps544@7 { /* u80 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x7>; regulator-name = "reg_vcc_fmc"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2600000>; /* enable-gpio = <&gpio0 23 0x4>; optional */ }; reg_vcc_ram: tps544@8 { /* u83 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x8>; }; reg_vcc_pslp: tps544@9 { /* u85 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x9>; }; reg_vcc_psfp: tps544@a { /* u86 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; /* vccint, vcc_io_soc */ }; }; i2c@1 { /* PMBUS1_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts comming to SC */ vcc_fmc: ina226@42 { /* u81 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u82 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u84 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u87 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* PMBUS2 */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* On connector J104 */ reg_vccaus: tps544@d { /* u88 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xd>; }; reg_vccaux_fmc: tps544@e { /* u90 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xe>; }; reg_vcco_500: tps544@f { /* u93 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0xf>; }; reg_vcco_501: tps544@10 { /* u95 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x10>; }; reg_vcco_502: tps544@11 { /* u97 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x11>; }; reg_vcco_503: tps544@12 { /* u99 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x12>; }; reg_vcc1v8: tps544@13 { /* u101 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x13>; }; reg_vcc3v3: tps544@14 { /* u102 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x14>; }; reg_vcc1v2_ddr4: tps544@15 { /* u104 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x15>; }; reg_vcc1v1_lp4: tps544@16 { /* u106 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x16>; }; reg_vcc1_1V8_lp4: tps544@17 { /* u108 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x17>; }; reg_vadj_fmc: tps544@19 { /* u109 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x19>; }; reg_mgtyavcc: tps544@1a { /* u111 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1a>; }; reg_mgtyavtt: tps544@1b { /* u114 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1b>; }; reg_mgtyvccaux: tps544@1c { /* u115 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1c>; }; reg_util_1v13: tps544@1d { /* u117 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1d>; }; reg_util_1v8: tps544@1e { /* u118 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1e>; }; reg_util_2v5: tps544@1f { /* u119 - FIXME name - don't know what it does */ compatible = "ti,tps544b25"; /* Documentation/hwmon/pmbus - wiring is missing */ reg = <0x1f>; }; }; i2c@3 { /* PMBUS2_INA226 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts comming to SC */ vccaux: ina226@40 { /* u89 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_fmc: ina226@41 { /* u91 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcco_500: ina226@42 { /* u92 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcco_501: ina226@43 { /* u94 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_502: ina226@44 { /* u96 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcco_503: ina226@45 { /* u98 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; vcc_1v8: ina226@46 { /* u100 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; vcc_3v3: ina226@47 { /* u103 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; vcc_1v2_ddr4: ina226@48 { /* u105 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <1000>; }; vcc1v1_lp4: ina226@49 { /* u107 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; vadj_fmc: ina226@4a { /* u110 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; mgtyavcc: ina226@4b { /* u112 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <1000>; }; mgtyavtt: ina226@4c { /* u113 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <1000>; }; mgtyvccaux: ina226@4d { /* u116 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; vcc_bat: ina226@4e { /* u12 */ compatible = "ti,ina226"; reg = <0x4e>; /* 10 ohm real value - setup 1ohm because of driver limitation */ shunt-resistor = <1000000>; }; }; i2c@4 { /* LP_I2C_SM */ #address-cells = <1>; #size-cells = <0>; reg = <4>; /* connected to J212G */ /* zynqmp sm alert or samtec J212H */ }; /* 5-7 unused */ }; }; /* TODO sysctrl via J239 */ /* TODO samtec J212G/H via J242 */ &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; /* Must be enabled via J242 */ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */ compatible = "atmel,24c02"; reg = <0x51>; }; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { /* DC_I2C */ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB FIXME addr */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; }; si570_ref_clk: clock-generator@60 { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* FMCP1_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* FMCP2_IIC */ #address-cells = <1>; #size-cells = <0>; reg = <2>; /* FIXME connection to Samtec J53C */ /* expected eeprom 0x50 SE cards */ }; i2c@3 { /* DDR4_DIMM1 */ #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_ddr_dimm1: clock-generator@60 { /* u2 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm1_clk"; }; /* 0x50 SPD? */ }; i2c@4 { /* DDR4_DIMM2 */ #address-cells = <1>; #size-cells = <0>; reg = <4>; si570_ddr_dimm2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_ddrdimm2_clk"; }; /* 0x50 SPD? */ }; i2c@5 { /* LPDDR4_SI570_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <5>; si570_lpddr4: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "si570_lpddr4_clk"; }; }; i2c@6 { /* HSDP_SI570 */ #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_hsdp: clock-generator@5d { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; /* FIXME addr */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; clock-output-names = "si570_hsdp_clk"; }; }; i2c@7 { /* PCIE_CLK */ #address-cells = <1>; #size-cells = <0>; reg = <7>; /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u39 8T49N240 - pcie clocking 3 */ }; }; }; &usb0 { phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &dwc3_1 { /delete-property/ phy-names ; /delete-property/ phys ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk ; snps,dis_u3_susphy_quirk ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/net/ti-dp83867.h" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revB", "xlnx,zynqmp-sc", "xlnx,zynqmp"; aliases { i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "sw16"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds40-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds44-led { label = "status"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; si5332_2: si5332_2 { /* u42 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 1>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "LED1", "LED2", "", /* 5 - 9 */ "", "ZU4_TRIGGER", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "UART0_RXD", "UART0_TXD", "", "", /* 25 - 29 */ "", "", "", "", "I2C0_SCL", /* 30 - 34 */ "I2C0_SDA", "UART1_TXD", "UART1_RXD", "GEM_TX_CLK", "GEM_TX_D0", /* 35 - 39 */ "GEM_TX_D1", "GEM_TX_D2", "GEM_TX_D3", "GEM_TX_CTL", "GEM_RX_CLK", /* 40 - 44 */ "GEM_RX_D0", "GEM_RX_D1", "GEM_RX_D2", "GEM_RX_D3", "GEM_RX_CTL", /* 45 - 49 */ "GEM_MDC", "GEM_MDIO", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "ETH_RESET_B", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 -89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ phy-mode = "rgmii-id"; phy-handle = <&phy0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem1_default>; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; ti,dp83867-rxctrl-strap-quirk; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <100>; reset-deassert-us = <280>; }; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; status = "okay"; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { /* i2c1 MIO 24-25 */ bootph-all; clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* No reason to do pinctrl setup at u-boot stage */ /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ bootph-all; }; }; /* USB 3.0 only */ &psgtr { /* nc, nc, usb3 */ clocks = <&si5332_2>; clock-names = "ref2"; }; &qspi { /* MIO 0-5 */ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &ttc0 { #pwm-cells = <3>; }; &uart1 { /* uart0 MIO36-37 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; }; &pinctrl0 { /* required by spec */ status = "okay"; pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; slew-rate = ; power-source = ; drive-strength = <12>; }; conf-rx { pins = "MIO37"; bias-high-impedance; }; conf-tx { pins = "MIO36"; bias-disable; }; mux { groups = "uart1_9_grp"; function = "uart1"; }; }; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { conf { groups = "i2c1_6_grp"; bias-pull-up; slew-rate = ; power-source = ; }; mux { groups = "i2c1_6_grp"; function = "i2c1"; }; }; pinctrl_i2c1_gpio: i2c1-gpio { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; power-source = ; }; mux { groups = "gpio0_24_grp", "gpio0_25_grp"; function = "gpio0"; }; }; pinctrl_gem1_default: gem1-default { conf { groups = "ethernet1_0_grp"; slew-rate = ; power-source = ; }; conf-rx { pins = "MIO44", "MIO46", "MIO48"; bias-high-impedance; low-power-disable; }; conf-bootstrap { pins = "MIO45", "MIO47", "MIO49"; bias-disable; low-power-disable; }; conf-tx { pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43"; bias-disable; low-power-enable; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; mux { function = "ethernet1"; groups = "ethernet1_0_grp"; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP Generic System Controller * * Copyright (C) 2021-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sc-revb.dtsi" / { model = "ZynqMP Generic System Controller"; compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; }; &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ /delete-node/ mdio; mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; adi,tx-internal-delay-ps = <2400>; adi,fifo-depth-bits = <8>; reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <5000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revA * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; gtclk1_1: sys-clk-0 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 0>; }; gtclk1_2: sys-clk-1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 1>; }; gtclk1_3: sys-clk-2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 2>; }; gtclk1_6: gtclk1-out6 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 3>; }; gtclk1_7: gtclk1-out7 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 4>; }; gtclk1_8: gtclk1-out8 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 5>; }; gtclk1_10: ps-ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 6>; }; gtclk1_11: gtclk1-out11 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&vc7 7>; }; }; &i2c0 { #address-cells = <1>; #size-cells = <0>; tca6416_u233: gpio@20 { /* u233 */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "", "", "SFP_MOD_ABS", "SFP_TX_DISABLE", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir35215_46: pmic@46 { /* IR35215 - u152 */ compatible = "infineon,ir35215"; reg = <0x46>; /* i2c addr - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; irps5401_48: pmic@48 { /* IRPS5401 - u279 */ compatible = "infineon,irps5401"; reg = <0x48>; /* i2c addr 0x18 */ }; ir38064_49: regulator@49 { /* IR38064 - u295 */ compatible = "infineon,ir38064"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1d */ }; ir38060_4e: regulator@4e { /* IR38060 - u282 */ compatible = "infineon,ir38060"; reg = <0x4e>; /* i2c addr 0x1e */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* alerts coming to u233 and SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <500>; /* r440 */ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <500>; /* r1702 */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r382 */ }; vcc_ram: ina226@43 { /* u355 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2417 */ }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; /* r1830 */ }; vcc_psfp: ina226@45 { /* u260 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2386 */ }; vcco_hdio: ina226@46 { /* u356 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; /* r2392 */ }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* alerts coming to u233 and SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; /* r2384 */ }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; /* r2000 */ }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; /* r1829 */ }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; /* r2397 */ }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; /* r2401 */ }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <500>; /* r1384 */ }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; /* r1994 */ }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; /* r2384 */ }; vcc1v1_lp4: ina226@49 { /* u306 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <500>; /* r2064 */ }; vadj_fmc: ina226@4a { /* u281 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; /* r2031 */ }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; /* r2004 */ }; lpdmgtyavtt: ina226@4c { /* u309 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; /* r1229 */ }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; /* r1679 */ }; }; i2c@4 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; rc21008a_gtclk1: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* connector j374 */ /* rc21008a at 0x9 u299 */ vc7: clock-generator@9 { compatible = "renesas,rc21008a"; reg = <0x9>; #clock-cells = <1>; clocks = <&vc7_xin>; clock-names = "xin"; }; }; fmcp1_iic: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* to j51c */ }; sfp: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* sfp+ connector J376 */ }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sc-vek280-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VEK280 revB * * (C) Copyright 2022-2024, Advanced Micro Devices, Inc * * Michal Simek */ #include "zynqmp-sc-vek280-reva.dtsi" &{/} { compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", "xlnx,zynqmp-vek280", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SM-K24 RevA/B/1"; compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-sm-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/phy/phy.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" / { model = "ZynqMP SM-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB", "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26", "xlnx,zynqmp"; aliases { gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; nvmem0 = &eeprom; nvmem1 = &eeprom_cc; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; usb0 = &usb0; usb1 = &usb1; }; chosen { bootargs = "earlycon"; stdout-path = "serial1:115200n8"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pmu_region: pmu@7ff00000 { reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds35-led { label = "heartbeat"; gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds36-led { label = "vbus_det"; gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; ams { compatible = "iio-hwmon"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>, <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>, <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>, <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>, <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>, <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; pwm-fan { compatible = "pwm-fan"; pwms = <&ttc0 2 40000 0>; }; }; &modepin_gpio { label = "modepin"; }; &ttc0 { #pwm-cells = <3>; }; &pinctrl0 { status = "okay"; pinctrl_sdhci0_default: sdhci0-default { conf { groups = "sdio0_0_grp"; slew-rate = ; power-source = ; bias-disable; }; mux { groups = "sdio0_0_grp"; function = "sdio0"; }; }; }; &qspi { /* MIO 0-5 - U143 */ spi_flash: flash@0 { /* MT25QU512A */ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "Image Selector"; reg = <0x0 0x80000>; /* 512KB */ read-only; lock; }; partition@80000 { label = "Image Selector Golden"; reg = <0x80000 0x80000>; /* 512KB */ read-only; lock; }; partition@100000 { label = "Persistent Register"; reg = <0x100000 0x20000>; /* 128KB */ }; partition@120000 { label = "Persistent Register Backup"; reg = <0x120000 0x20000>; /* 128KB */ }; partition@140000 { label = "Open_1"; reg = <0x140000 0xC0000>; /* 768KB */ }; partition@200000 { label = "Image A (FSBL, PMU, ATF, U-Boot)"; reg = <0x200000 0xD00000>; /* 13MB */ }; partition@f00000 { label = "ImgSel Image A Catch"; reg = <0xF00000 0x80000>; /* 512KB */ read-only; lock; }; partition@f80000 { label = "Image B (FSBL, PMU, ATF, U-Boot)"; reg = <0xF80000 0xD00000>; /* 13MB */ }; partition@1c80000 { label = "ImgSel Image B Catch"; reg = <0x1C80000 0x80000>; /* 512KB */ read-only; lock; }; partition@1d00000 { label = "Open_2"; reg = <0x1D00000 0x100000>; /* 1MB */ }; partition@1e00000 { label = "Recovery Image"; reg = <0x1E00000 0x200000>; /* 2MB */ read-only; lock; }; partition@2000000 { label = "Recovery Image Backup"; reg = <0x2000000 0x200000>; /* 2MB */ read-only; lock; }; partition@2200000 { label = "U-Boot storage variables"; reg = <0x2200000 0x20000>; /* 128KB */ }; partition@2220000 { label = "U-Boot storage variables backup"; reg = <0x2220000 0x20000>; /* 128KB */ }; partition@2240000 { label = "SHA256"; reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ read-only; lock; }; partition@2280000 { label = "Secure OS Storage"; reg = <0x2280000 0x20000>; /* 128KB */ }; partition@22A0000 { label = "User"; reg = <0x22A0000 0x1d60000>; /* 29.375 MB */ }; }; }; }; &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; assigned-clock-rates = <187498123>; }; &spi1 { /* MIO6, 9-11 */ label = "TPM"; num-cs = <1>; tpm@0 { /* slm9670 - U144 */ compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <18500000>; }; }; &i2c1 { bootph-all; clock-frequency = <400000>; scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x50>; /* WP pin EE_WP_EN connected to slg7x644092@68 */ }; eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */ bootph-all; compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */ reg = <0x51>; }; /* da9062@30 - u170 - also at address 0x31 */ /* da9131@33 - u167 */ da9131: pmic@33 { compatible = "dlg,da9131"; reg = <0x33>; regulators { da9131_buck1: buck1 { regulator-name = "da9131_buck1"; regulator-boot-on; regulator-always-on; }; da9131_buck2: buck2 { regulator-name = "da9131_buck2"; regulator-boot-on; regulator-always-on; }; }; }; /* da9130@32 - u166 */ da9130: pmic@32 { compatible = "dlg,da9130"; reg = <0x32>; regulators { da9130_buck1: buck1 { regulator-name = "da9130_buck1"; regulator-boot-on; regulator-always-on; }; }; }; /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */ /* * stdp4320 - u27 FW has below two issues to be fixed in next board revision. * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76. * Address conflict with slg7x644091@70 making both the devices NOT accessible. * With the FW fix, stdp4320 should respond to address 0x73 only. */ /* slg7x644092@68 - u169 */ /* Also connected via JA1C as C23/C24 */ }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */ "I2C1_SDA", "", "", "", "", /* 25 - 29 */ "", "", "", "", "", /* 30 - 34 */ "", "", "", "", "", /* 35 - 39 */ "", "", "", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "", "", "", /* 50 - 54 */ "", "", "", "", "", /* 55 - 59 */ "", "", "", "", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "", "", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k24-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. * (C) Copyright 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "zynqmp-sm-k24-reva.dtsi" / { model = "ZynqMP SMK-K24 RevA"; compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-smk-k26-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "zynqmp-sm-k26-reva.dtsi" / { model = "ZynqMP SMK-K26 Rev1/B/A"; compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB", "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26", "xlnx,zynqmp"; }; &sdhci0 { status = "disabled"; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-vp-x-a2785-00-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP vp-x-a2785-00 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on vp-x-a2785-00 board RevA"; compatible = "xlnx,zynqmp-vp-x-a2785-00-revA", "xlnx,zynqmp-vp-x-a2785-00", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; gpio-keys { compatible = "gpio-keys"; autorepeat; key-j383 { label = "j383"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds52 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb - u142 */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci1 { /* sd MIO 45-51 */ no-1-8-v; disable-wp; xlnx,mio-bank = <1>; }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { /* u131 - M88e1512 */ reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "", "", /* 10 - 14 */ "", "", "", "", "", /* 15 - 19 */ "", "", "", "", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "SD1_CD", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ "", "", "", "", "", /* 80 - 84 */ "", "", "", "", "", /* 85 - 89 */ "", "", "", "", "", /* 90 - 94 */ "", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "", "", /* 0 - 3 */ "", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "", "", "", "VCCINT_FAULT_B", /* 10 - 13 */ "VCCINT_VRHOT_B", "", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ compatible = "ti,tps53681", "ti,tps53679"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ compatible = "ti,tps544b25"; reg = <0xd>; }; reg_mgtyavcc: tps544@10 { /* u274 */ compatible = "ti,tps544b25"; reg = <0x10>; }; reg_mgtyavtt: tps544@11 { /* u275 */ compatible = "ti,tps544b25"; reg = <0x11>; }; reg_vccaux: tps544@12 { /* u276 */ compatible = "ti,tps544b25"; reg = <0x12>; }; reg_vcc_cpm: tps544@14 { /* u272 */ compatible = "ti,tps544b25"; reg = <0x14>; }; reg_util_3v3: tps544@1d { /* u278 */ compatible = "ti,tps544b25"; reg = <0x1d>; }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vcc_cpm: ina226@44 { /* u273 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <1000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pcie_smbus: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; pcie2_smbus: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ dc_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; si570_ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; i2c@1 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <3>; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; /* 6-7 unused */ }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/BOARD/zynqmp-vpk120-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx ZynqMP VPK120 RevA System Controller * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/pinctrl/pinctrl-zynqmp.h" #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/phy/phy.h" / { model = "ZynqMP System Controller on VPK120 board RevA"; compatible = "xlnx,zynqmp-vpk120-revA", "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &dcc; spi0 = &qspi; usb0 = &usb0; usb1 = &usb1; nvmem0 = &eeprom; }; si570_user1_fmc_clk: si570-user1-fmc-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&user_si570_1>; }; si570_ref_clk: si570-ref-clk { status = "okay"; compatible = "xlnx,fclk"; clocks = <&ref_clk>; }; si570_lpddr4_clk3: si570-lpddr4-clk3 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk3>; }; si570_lpddr4_clk2: si570-lpddr4-clk2 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk2>; }; si570_lpddr4_clk1: si570-lpddr4-clk1 { status = "okay"; compatible = "xlnx,fclk"; clocks = <&lpddr4_clk1>; }; gpio-keys { compatible = "gpio-keys"; autorepeat; button-16 { label = "sw16"; gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { /* ds40 */ label = "heartbeat"; gpios = <&gpio 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; si5332_0: si5332_0 { /* ps_ref_clk */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; si5332_1: si5332_1 { /* clk0_sgmii */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; /* FIXME */ }; si5332_2: si5332_2 { /* clk1_usb */ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &psgtr { /* sgmii, usb3 */ clocks = <&si5332_1>, <&si5332_2>; clock-names = "ref0", "ref1"; }; &qspi { /* MIO 0-5 */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ #address-cells = <1>; #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; partition@0 { /* for testing purpose */ label = "qspi"; reg = <0 0x4000000>; }; }; }; &sdhci0 { /* emmc MIO 13-23 - with some settings MTFC16GAPALBH 16GB */ non-removable; disable-wp; bus-width = <8>; xlnx,mio-bank = <0>; }; &uart0 { /* uart0 MIO38-39 */ bootph-all; }; &gem0 { phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ phy0: ethernet-phy@0 { reg = <0>; }; }; &gpio { gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */ "QSPI_CS_B", "", "", "SYSCTLR_GPIO", "SYSCTLR_LED", /* 5 - 9 */ "SYSCTLR_PB", "PMC_ZU4_TRIGGER", "", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */ "", "", "", "", "", /* 25 - 29 */ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */ "", "", "ETH_RESET_B", "", "", /* 40 - 44 */ "", "", "", "", "", /* 45 - 49 */ "", "", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "", /* 60 - 64 */ "", "", "", "", "", /* 65 - 69 */ "", "", "", "", "", /* 70 - 74 */ "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */ "", "", "", "", "", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "", "", "", "", "", /* 110 - 114 */ "", "", "", "", "", /* 115 - 119 */ "", "", "", "", "", /* 120 - 124 */ "", "", "", "", "", /* 125 - 129 */ "", "", "", "", "", /* 130 - 134 */ "", "", "", "", "", /* 135 - 139 */ "", "", "", "", "", /* 140 - 144 */ "", "", "", "", "", /* 145 - 149 */ "", "", "", "", "", /* 150 - 154 */ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ "", "", "", ""; /* 170 - 173 */ }; &i2c0 { /* MIO 34-35 - can't stay here */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; tca6416_u233: gpio@20 { /* u233 */ /* FIXME - address maybe wrong */ compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "QSFPDD1_MODSELL", "QSFPDD1_MODSELL", /* 0 - 3 */ "PMBUS2_INA226_ALERT", "", "", "MAX6643_FULL_SPEED", /* 4 - 7 */ "FMCP1_FMC_PRSNT_M2C_B", "", "FMCP1_FMCP_PRSNT_M2C_B", "", /* 10 - 13 */ "VCCINT_VRHOT_B", "8A34001_EXP_RST_B", "PMBUS_ALERT", "PMBUS1_INA226_ALERT"; /* 14 - 17 */ }; i2c-mux@74 { /* u33 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* On connector J325 */ ir38060_41: regulator@41 { /* IR38060 - u259 */ compatible = "infineon,ir38060", "infineon,ir38064"; reg = <0x41>; /* i2c addr 0x11 */ }; ir38164_43: regulator@43 { /* IR38164 - u13 */ compatible = "infineon,ir38164"; reg = <0x43>; /* i2c addr 0x13 */ }; ir35221_45: pmic@46 { /* IR35221 - u152 */ compatible = "infineon,ir35221"; reg = <0x46>; /* PMBUS - 0x16 */ }; irps5401_47: pmic5401@47 { /* IRPS5401 - u160 */ compatible = "infineon,irps5401"; reg = <0x47>; /* i2c addr 0x17 */ }; ir38164_49: regulator@49 { /* IR38164 - u189 */ compatible = "infineon,ir38164"; reg = <0x49>; /* i2c addr 0x19 */ }; irps5401_4c: pmic@4c { /* IRPS5401 - u167 */ compatible = "infineon,irps5401"; reg = <0x4c>; /* i2c addr 0x1c */ }; irps5401_4d: pmic@4d { /* IRPS5401 - u175 */ compatible = "infineon,irps5401"; reg = <0x4d>; /* i2c addr 0x1c */ }; ir38164_4e: regulator@4e { /* IR38164 - u184 */ compatible = "infineon,ir38164"; reg = <0x4e>; /* i2c addr 0x1e */ }; ir38164_4f: regulator@4f { /* IR38164 - u187 */ compatible = "infineon,ir38164"; reg = <0x4f>; /* i2c addr 0x1f */ }; }; pmbus1_ina226_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME check alerts coming to SC */ vccint: ina226@40 { /* u65 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc_ram: ina226@43 { /* u5 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcc_pslp: ina226@44 { /* u165 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; vcc_psfp: ina226@45 { /* u164 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; }; i2c@2 { /* NC */ /* FIXME maybe remove */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; pmbus2_ina226_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* FIXME check alerts coming to SC */ vccaux: ina226@40 { /* u166 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; vccaux_pmc: ina226@41 { /* u168 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; mgtavcc: ina226@42 { /* u265 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; vcc1v5: ina226@43 { /* u264 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; vcco_mio: ina226@45 { /* u172 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; mgtavtt: ina226@46 { /* u188 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; vcco_502: ina226@47 { /* u174 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; mgtvccaux: ina226@48 { /* u176 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; vcc1v1_lp4: ina226@49 { /* u186 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <2000>; }; vadj_fmc: ina226@4a { /* u184 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <2000>; }; lpdmgtyavcc: ina226@4b { /* u177 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; lpdmgtyavtt: ina226@4c { /* u260 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <2000>; }; lpdmgtyvccaux: ina226@4d { /* u234 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; }; i2c@4 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { /* NC */ #address-cells = <1>; #size-cells = <0>; reg = <5>; }; user_si570: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; user_si570_1: clock-generator@5f { /* USER C0 SI570 - u205 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5f>; temperature-stability = <50>; factory-fout = <100000000>; clock-frequency = <100000000>; clock-output-names = "fmc_si570"; }; }; /* 7 unused */ }; }; &i2c1 { /* i2c1 MIO 36-37 */ clock-frequency = <400000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; i2c-mux@74 { /* u35 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* Use for storing information about SC board */ eeprom: eeprom@54 { /* u34 - m24128 16kB */ compatible = "st,24c128", "atmel,24c128"; reg = <0x54>; /* & 0x5c */ }; ref_clk: clock-generator@5d { /* u32 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <33333333>; clock-frequency = <33333333>; clock-output-names = "ref_clk"; silabs,skip-recall; }; }; fmcp1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* FIXME connection to Samtec J51C */ /* expected eeprom 0x50 SE cards */ }; i2c@2 { /* NC - FIXME */ #address-cells = <1>; #size-cells = <0>; reg = <2>; }; lpddr4_si570_clk3_i2c: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; lpddr4_clk3: clock-generator@60 { /* u4 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk3"; }; }; lpddr4_si570_clk2_i2c: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; lpddr4_clk2: clock-generator@60 { /* u3 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk2"; }; }; lpddr4_si570_clk1_i2c: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; lpddr4_clk1: clock-generator@60 { /* u248 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x60>; temperature-stability = <50>; factory-fout = <200000000>; clock-frequency = <200000000>; clock-output-names = "lpddr4_clk1"; }; }; qsfpdd_i2c: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* J1/J2 connectors */ }; idt8a34001_i2c: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* Via J310 connector */ idt_8a34001: phc@5b { compatible = "idt,8a34001"; /* u219B */ reg = <0x5b>; /* FIXME not in schematics */ }; }; }; }; &usb0 { /* MIO52 - MIO63 */ phy-names = "usb3-phy"; phys = <&psgtr 1 PHY_TYPE_USB3 0 1>; }; &dwc3_0 { dr_mode = "peripheral"; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; maximum-speed = "super-speed"; }; &pinctrl0 { status = "okay"; pinctrl_i2c0_default: i2c0-default { mux { groups = "i2c0_8_grp"; function = "i2c0"; }; conf { groups = "i2c0_8_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c0_gpio: i2c0-gpio { mux { groups = "gpio0_34_grp", "gpio0_35_grp"; function = "gpio0"; }; conf { groups = "gpio0_34_grp", "gpio0_35_grp"; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_default: i2c1-default { mux { groups = "i2c1_9_grp"; function = "i2c1"; }; conf { groups = "i2c1_9_grp"; bias-pull-up; slew-rate = ; power-source = ; }; }; pinctrl_i2c1_gpio: i2c1-gpio { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; }; conf { groups = "gpio0_36_grp", "gpio0_37_grp"; slew-rate = ; power-source = ; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-versal-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_VERSAL_H #define _DT_BINDINGS_CLK_VERSAL_H #define PMC_PLL 1 #define APU_PLL 2 #define RPU_PLL 3 #define CPM_PLL 4 #define NOC_PLL 5 #define PLL_MAX 6 #define PMC_PRESRC 7 #define PMC_POSTCLK 8 #define PMC_PLL_OUT 9 #define PPLL 10 #define NOC_PRESRC 11 #define NOC_POSTCLK 12 #define NOC_PLL_OUT 13 #define NPLL 14 #define APU_PRESRC 15 #define APU_POSTCLK 16 #define APU_PLL_OUT 17 #define APLL 18 #define RPU_PRESRC 19 #define RPU_POSTCLK 20 #define RPU_PLL_OUT 21 #define RPLL 22 #define CPM_PRESRC 23 #define CPM_POSTCLK 24 #define CPM_PLL_OUT 25 #define CPLL 26 #define PPLL_TO_XPD 27 #define NPLL_TO_XPD 28 #define APLL_TO_XPD 29 #define RPLL_TO_XPD 30 #define EFUSE_REF 31 #define SYSMON_REF 32 #define IRO_SUSPEND_REF 33 #define USB_SUSPEND 34 #define SWITCH_TIMEOUT 35 #define RCLK_PMC 36 #define RCLK_LPD 37 #define WDT 38 #define TTC0 39 #define TTC1 40 #define TTC2 41 #define TTC3 42 #define GEM_TSU 43 #define GEM_TSU_LB 44 #define MUXED_IRO_DIV2 45 #define MUXED_IRO_DIV4 46 #define PSM_REF 47 #define GEM0_RX 48 #define GEM0_TX 49 #define GEM1_RX 50 #define GEM1_TX 51 #define CPM_CORE_REF 52 #define CPM_LSBUS_REF 53 #define CPM_DBG_REF 54 #define CPM_AUX0_REF 55 #define CPM_AUX1_REF 56 #define QSPI_REF 57 #define OSPI_REF 58 #define SDIO0_REF 59 #define SDIO1_REF 60 #define PMC_LSBUS_REF 61 #define I2C_REF 62 #define TEST_PATTERN_REF 63 #define DFT_OSC_REF 64 #define PMC_PL0_REF 65 #define PMC_PL1_REF 66 #define PMC_PL2_REF 67 #define PMC_PL3_REF 68 #define CFU_REF 69 #define SPARE_REF 70 #define NPI_REF 71 #define HSM0_REF 72 #define HSM1_REF 73 #define SD_DLL_REF 74 #define FPD_TOP_SWITCH 75 #define FPD_LSBUS 76 #define ACPU 77 #define DBG_TRACE 78 #define DBG_FPD 79 #define LPD_TOP_SWITCH 80 #define ADMA 81 #define LPD_LSBUS 82 #define CPU_R5 83 #define CPU_R5_CORE 84 #define CPU_R5_OCM 85 #define CPU_R5_OCM2 86 #define IOU_SWITCH 87 #define GEM0_REF 88 #define GEM1_REF 89 #define GEM_TSU_REF 90 #define USB0_BUS_REF 91 #define UART0_REF 92 #define UART1_REF 93 #define SPI0_REF 94 #define SPI1_REF 95 #define CAN0_REF 96 #define CAN1_REF 97 #define I2C0_REF 98 #define I2C1_REF 99 #define DBG_LPD 100 #define TIMESTAMP_REF 101 #define DBG_TSTMP 102 #define CPM_TOPSW_REF 103 #define USB3_DUAL_REF 104 #define OUTCLK_MAX 105 #define REF_CLK 106 #define PL_ALT_REF_CLK 107 #define MUXED_IRO 108 #define PL_EXT 109 #define PL_LB 110 #define MIO_50_OR_51 111 #define MIO_24_OR_25 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-versal-net-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_CLK_VERSAL_NET_H #define _DT_BINDINGS_CLK_VERSAL_NET_H #include #define GEM0_REF_RX 0xA9 #define GEM0_REF_TX 0xA8 #define GEM1_REF_RX 0xA2 #define GEM1_REF_TX 0xA1 #define CAN0_REF_2X 0x9E #define CAN1_REF_2X 0xAC #define FPD_WWDT 0x96 #define ACPU_0 0x98 #define ACPU_1 0x9B #define ACPU_2 0x9A #define ACPU_3 0x99 #define I3C0_REF 0x9D #define I3C1_REF 0x9F #define USB1_BUS_REF 0xAE #define LPD_WWDT 0xAD /* Remove Versal specific node IDs */ #undef APU_PLL #undef RPU_PLL #undef CPM_PLL #undef APU_PRESRC #undef APU_POSTCLK #undef APU_PLL_OUT #undef APLL #undef RPU_PRESRC #undef RPU_POSTCLK #undef RPU_PLL_OUT #undef RPLL #undef CPM_PRESRC #undef CPM_POSTCLK #undef CPM_PLL_OUT #undef CPLL #undef APLL_TO_XPD #undef RPLL_TO_XPD #undef RCLK_PMC #undef RCLK_LPD #undef WDT #undef MUXED_IRO_DIV2 #undef MUXED_IRO_DIV4 #undef PSM_REF #undef CPM_CORE_REF #undef CPM_LSBUS_REF #undef CPM_DBG_REF #undef CPM_AUX0_REF #undef CPM_AUX1_REF #undef CPU_R5 #undef CPU_R5_CORE #undef CPU_R5_OCM #undef CPU_R5_OCM2 #undef CAN0_REF #undef CAN1_REF #undef I2C0_REF #undef I2C1_REF #undef CPM_TOPSW_REF #undef USB3_DUAL_REF #undef MUXED_IRO #undef PL_EXT #undef PL_LB #undef MIO_50_OR_51 #undef MIO_24_OR_25 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/clock/xlnx-zynqmp-clk.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * */ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H #define IOPLL 0 #define RPLL 1 #define APLL 2 #define DPLL 3 #define VPLL 4 #define IOPLL_TO_FPD 5 #define RPLL_TO_FPD 6 #define APLL_TO_LPD 7 #define DPLL_TO_LPD 8 #define VPLL_TO_LPD 9 #define ACPU 10 #define ACPU_HALF 11 #define DBF_FPD 12 #define DBF_LPD 13 #define DBG_TRACE 14 #define DBG_TSTMP 15 #define DP_VIDEO_REF 16 #define DP_AUDIO_REF 17 #define DP_STC_REF 18 #define GDMA_REF 19 #define DPDMA_REF 20 #define DDR_REF 21 #define SATA_REF 22 #define PCIE_REF 23 #define GPU_REF 24 #define GPU_PP0_REF 25 #define GPU_PP1_REF 26 #define TOPSW_MAIN 27 #define TOPSW_LSBUS 28 #define GTGREF0_REF 29 #define LPD_SWITCH 30 #define LPD_LSBUS 31 #define USB0_BUS_REF 32 #define USB1_BUS_REF 33 #define USB3_DUAL_REF 34 #define USB0 35 #define USB1 36 #define CPU_R5 37 #define CPU_R5_CORE 38 #define CSU_SPB 39 #define CSU_PLL 40 #define PCAP 41 #define IOU_SWITCH 42 #define GEM_TSU_REF 43 #define GEM_TSU 44 #define GEM0_TX 45 #define GEM1_TX 46 #define GEM2_TX 47 #define GEM3_TX 48 #define GEM0_RX 49 #define GEM1_RX 50 #define GEM2_RX 51 #define GEM3_RX 52 #define QSPI_REF 53 #define SDIO0_REF 54 #define SDIO1_REF 55 #define UART0_REF 56 #define UART1_REF 57 #define SPI0_REF 58 #define SPI1_REF 59 #define NAND_REF 60 #define I2C0_REF 61 #define I2C1_REF 62 #define CAN0_REF 63 #define CAN1_REF 64 #define CAN0 65 #define CAN1 66 #define DLL_REF 67 #define ADMA_REF 68 #define TIMESTAMP_REF 69 #define AMS_REF 70 #define PL0_REF 71 #define PL1_REF 72 #define PL2_REF 73 #define PL3_REF 74 #define WDT 75 #define IOPLL_INT 76 #define IOPLL_PRE_SRC 77 #define IOPLL_HALF 78 #define IOPLL_INT_MUX 79 #define IOPLL_POST_SRC 80 #define RPLL_INT 81 #define RPLL_PRE_SRC 82 #define RPLL_HALF 83 #define RPLL_INT_MUX 84 #define RPLL_POST_SRC 85 #define APLL_INT 86 #define APLL_PRE_SRC 87 #define APLL_HALF 88 #define APLL_INT_MUX 89 #define APLL_POST_SRC 90 #define DPLL_INT 91 #define DPLL_PRE_SRC 92 #define DPLL_HALF 93 #define DPLL_INT_MUX 94 #define DPLL_POST_SRC 95 #define VPLL_INT 96 #define VPLL_PRE_SRC 97 #define VPLL_HALF 98 #define VPLL_INT_MUX 99 #define VPLL_POST_SRC 100 #define CAN0_MIO 101 #define CAN1_MIO 102 #define ACPU_FULL 103 #define GEM0_REF 104 #define GEM1_REF 105 #define GEM2_REF 106 #define GEM3_REF 107 #define GEM0_REF_UNG 108 #define GEM1_REF_UNG 109 #define GEM2_REF_UNG 110 #define GEM3_REF_UNG 111 #define LPD_WDT 112 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h ================================================ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright 2019 Laurent Pinchart */ #ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ #define ZYNQMP_DPDMA_VIDEO0 0 #define ZYNQMP_DPDMA_VIDEO1 1 #define ZYNQMP_DPDMA_VIDEO2 2 #define ZYNQMP_DPDMA_GRAPHICS 3 #define ZYNQMP_DPDMA_AUDIO0 4 #define ZYNQMP_DPDMA_AUDIO1 5 #endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/gpio/gpio.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most GPIO bindings. * * Most GPIO bindings include a flags cell as part of the GPIO specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_GPIO_GPIO_H #define _DT_BINDINGS_GPIO_GPIO_H /* Bit 0 express polarity */ #define GPIO_ACTIVE_HIGH 0 #define GPIO_ACTIVE_LOW 1 /* Bit 1 express single-endedness */ #define GPIO_PUSH_PULL 0 #define GPIO_SINGLE_ENDED 2 /* Bit 2 express Open drain or open source */ #define GPIO_LINE_OPEN_SOURCE 0 #define GPIO_LINE_OPEN_DRAIN 4 /* * Open Drain/Collector is the combination of single-ended open drain interface. * Open Source/Emitter is the combination of single-ended open source interface. */ #define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) #define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE) /* Bit 3 express GPIO suspend/resume and reset persistence */ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 /* Bit 4 express pull up */ #define GPIO_PULL_UP 16 /* Bit 5 express pull down */ #define GPIO_PULL_DOWN 32 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/input/input.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most input bindings. * * Most input bindings include key code, matrix key code format. * In most cases, key code and matrix key code format uses * the standard values/macro defined in this header. */ #ifndef _DT_BINDINGS_INPUT_INPUT_H #define _DT_BINDINGS_INPUT_INPUT_H /* * Device properties and quirks */ #define INPUT_PROP_POINTER 0x00 /* needs a pointer */ #define INPUT_PROP_DIRECT 0x01 /* direct input devices */ #define INPUT_PROP_BUTTONPAD 0x02 /* has button(s) under pad */ #define INPUT_PROP_SEMI_MT 0x03 /* touch rectangle only */ #define INPUT_PROP_TOPBUTTONPAD 0x04 /* softbuttons at top of pad */ #define INPUT_PROP_POINTING_STICK 0x05 /* is a pointing stick */ #define INPUT_PROP_ACCELEROMETER 0x06 /* has accelerometer */ #define INPUT_PROP_MAX 0x1f #define INPUT_PROP_CNT (INPUT_PROP_MAX + 1) /* * Event types */ #define EV_SYN 0x00 #define EV_KEY 0x01 #define EV_REL 0x02 #define EV_ABS 0x03 #define EV_MSC 0x04 #define EV_SW 0x05 #define EV_LED 0x11 #define EV_SND 0x12 #define EV_REP 0x14 #define EV_FF 0x15 #define EV_PWR 0x16 #define EV_FF_STATUS 0x17 #define EV_MAX 0x1f #define EV_CNT (EV_MAX+1) /* * Synchronization events. */ #define SYN_REPORT 0 #define SYN_CONFIG 1 #define SYN_MT_REPORT 2 #define SYN_DROPPED 3 #define SYN_MAX 0xf #define SYN_CNT (SYN_MAX+1) /* * Keys and buttons * * Most of the keys/buttons are modeled after USB HUT 1.12 * (see http://www.usb.org/developers/hidpage). * Abbreviations in the comments: * AC - Application Control * AL - Application Launch Button * SC - System Control */ #define KEY_RESERVED 0 #define KEY_ESC 1 #define KEY_1 2 #define KEY_2 3 #define KEY_3 4 #define KEY_4 5 #define KEY_5 6 #define KEY_6 7 #define KEY_7 8 #define KEY_8 9 #define KEY_9 10 #define KEY_0 11 #define KEY_MINUS 12 #define KEY_EQUAL 13 #define KEY_BACKSPACE 14 #define KEY_TAB 15 #define KEY_Q 16 #define KEY_W 17 #define KEY_E 18 #define KEY_R 19 #define KEY_T 20 #define KEY_Y 21 #define KEY_U 22 #define KEY_I 23 #define KEY_O 24 #define KEY_P 25 #define KEY_LEFTBRACE 26 #define KEY_RIGHTBRACE 27 #define KEY_ENTER 28 #define KEY_LEFTCTRL 29 #define KEY_A 30 #define KEY_S 31 #define KEY_D 32 #define KEY_F 33 #define KEY_G 34 #define KEY_H 35 #define KEY_J 36 #define KEY_K 37 #define KEY_L 38 #define KEY_SEMICOLON 39 #define KEY_APOSTROPHE 40 #define KEY_GRAVE 41 #define KEY_LEFTSHIFT 42 #define KEY_BACKSLASH 43 #define KEY_Z 44 #define KEY_X 45 #define KEY_C 46 #define KEY_V 47 #define KEY_B 48 #define KEY_N 49 #define KEY_M 50 #define KEY_COMMA 51 #define KEY_DOT 52 #define KEY_SLASH 53 #define KEY_RIGHTSHIFT 54 #define KEY_KPASTERISK 55 #define KEY_LEFTALT 56 #define KEY_SPACE 57 #define KEY_CAPSLOCK 58 #define KEY_F1 59 #define KEY_F2 60 #define KEY_F3 61 #define KEY_F4 62 #define KEY_F5 63 #define KEY_F6 64 #define KEY_F7 65 #define KEY_F8 66 #define KEY_F9 67 #define KEY_F10 68 #define KEY_NUMLOCK 69 #define KEY_SCROLLLOCK 70 #define KEY_KP7 71 #define KEY_KP8 72 #define KEY_KP9 73 #define KEY_KPMINUS 74 #define KEY_KP4 75 #define KEY_KP5 76 #define KEY_KP6 77 #define KEY_KPPLUS 78 #define KEY_KP1 79 #define KEY_KP2 80 #define KEY_KP3 81 #define KEY_KP0 82 #define KEY_KPDOT 83 #define KEY_ZENKAKUHANKAKU 85 #define KEY_102ND 86 #define KEY_F11 87 #define KEY_F12 88 #define KEY_RO 89 #define KEY_KATAKANA 90 #define KEY_HIRAGANA 91 #define KEY_HENKAN 92 #define KEY_KATAKANAHIRAGANA 93 #define KEY_MUHENKAN 94 #define KEY_KPJPCOMMA 95 #define KEY_KPENTER 96 #define KEY_RIGHTCTRL 97 #define KEY_KPSLASH 98 #define KEY_SYSRQ 99 #define KEY_RIGHTALT 100 #define KEY_LINEFEED 101 #define KEY_HOME 102 #define KEY_UP 103 #define KEY_PAGEUP 104 #define KEY_LEFT 105 #define KEY_RIGHT 106 #define KEY_END 107 #define KEY_DOWN 108 #define KEY_PAGEDOWN 109 #define KEY_INSERT 110 #define KEY_DELETE 111 #define KEY_MACRO 112 #define KEY_MUTE 113 #define KEY_VOLUMEDOWN 114 #define KEY_VOLUMEUP 115 #define KEY_POWER 116 /* SC System Power Down */ #define KEY_KPEQUAL 117 #define KEY_KPPLUSMINUS 118 #define KEY_PAUSE 119 #define KEY_SCALE 120 /* AL Compiz Scale (Expose) */ #define KEY_KPCOMMA 121 #define KEY_HANGEUL 122 #define KEY_HANGUEL KEY_HANGEUL #define KEY_HANJA 123 #define KEY_YEN 124 #define KEY_LEFTMETA 125 #define KEY_RIGHTMETA 126 #define KEY_COMPOSE 127 #define KEY_STOP 128 /* AC Stop */ #define KEY_AGAIN 129 #define KEY_PROPS 130 /* AC Properties */ #define KEY_UNDO 131 /* AC Undo */ #define KEY_FRONT 132 #define KEY_COPY 133 /* AC Copy */ #define KEY_OPEN 134 /* AC Open */ #define KEY_PASTE 135 /* AC Paste */ #define KEY_FIND 136 /* AC Search */ #define KEY_CUT 137 /* AC Cut */ #define KEY_HELP 138 /* AL Integrated Help Center */ #define KEY_MENU 139 /* Menu (show menu) */ #define KEY_CALC 140 /* AL Calculator */ #define KEY_SETUP 141 #define KEY_SLEEP 142 /* SC System Sleep */ #define KEY_WAKEUP 143 /* System Wake Up */ #define KEY_FILE 144 /* AL Local Machine Browser */ #define KEY_SENDFILE 145 #define KEY_DELETEFILE 146 #define KEY_XFER 147 #define KEY_PROG1 148 #define KEY_PROG2 149 #define KEY_WWW 150 /* AL Internet Browser */ #define KEY_MSDOS 151 #define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */ #define KEY_SCREENLOCK KEY_COFFEE #define KEY_ROTATE_DISPLAY 153 /* Display orientation for e.g. tablets */ #define KEY_DIRECTION KEY_ROTATE_DISPLAY #define KEY_CYCLEWINDOWS 154 #define KEY_MAIL 155 #define KEY_BOOKMARKS 156 /* AC Bookmarks */ #define KEY_COMPUTER 157 #define KEY_BACK 158 /* AC Back */ #define KEY_FORWARD 159 /* AC Forward */ #define KEY_CLOSECD 160 #define KEY_EJECTCD 161 #define KEY_EJECTCLOSECD 162 #define KEY_NEXTSONG 163 #define KEY_PLAYPAUSE 164 #define KEY_PREVIOUSSONG 165 #define KEY_STOPCD 166 #define KEY_RECORD 167 #define KEY_REWIND 168 #define KEY_PHONE 169 /* Media Select Telephone */ #define KEY_ISO 170 #define KEY_CONFIG 171 /* AL Consumer Control Configuration */ #define KEY_HOMEPAGE 172 /* AC Home */ #define KEY_REFRESH 173 /* AC Refresh */ #define KEY_EXIT 174 /* AC Exit */ #define KEY_MOVE 175 #define KEY_EDIT 176 #define KEY_SCROLLUP 177 #define KEY_SCROLLDOWN 178 #define KEY_KPLEFTPAREN 179 #define KEY_KPRIGHTPAREN 180 #define KEY_NEW 181 /* AC New */ #define KEY_REDO 182 /* AC Redo/Repeat */ #define KEY_F13 183 #define KEY_F14 184 #define KEY_F15 185 #define KEY_F16 186 #define KEY_F17 187 #define KEY_F18 188 #define KEY_F19 189 #define KEY_F20 190 #define KEY_F21 191 #define KEY_F22 192 #define KEY_F23 193 #define KEY_F24 194 #define KEY_PLAYCD 200 #define KEY_PAUSECD 201 #define KEY_PROG3 202 #define KEY_PROG4 203 #define KEY_DASHBOARD 204 /* AL Dashboard */ #define KEY_SUSPEND 205 #define KEY_CLOSE 206 /* AC Close */ #define KEY_PLAY 207 #define KEY_FASTFORWARD 208 #define KEY_BASSBOOST 209 #define KEY_PRINT 210 /* AC Print */ #define KEY_HP 211 #define KEY_CAMERA 212 #define KEY_SOUND 213 #define KEY_QUESTION 214 #define KEY_EMAIL 215 #define KEY_CHAT 216 #define KEY_SEARCH 217 #define KEY_CONNECT 218 #define KEY_FINANCE 219 /* AL Checkbook/Finance */ #define KEY_SPORT 220 #define KEY_SHOP 221 #define KEY_ALTERASE 222 #define KEY_CANCEL 223 /* AC Cancel */ #define KEY_BRIGHTNESSDOWN 224 #define KEY_BRIGHTNESSUP 225 #define KEY_MEDIA 226 #define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video outputs (Monitor/LCD/TV-out/etc) */ #define KEY_KBDILLUMTOGGLE 228 #define KEY_KBDILLUMDOWN 229 #define KEY_KBDILLUMUP 230 #define KEY_SEND 231 /* AC Send */ #define KEY_REPLY 232 /* AC Reply */ #define KEY_FORWARDMAIL 233 /* AC Forward Msg */ #define KEY_SAVE 234 /* AC Save */ #define KEY_DOCUMENTS 235 #define KEY_BATTERY 236 #define KEY_BLUETOOTH 237 #define KEY_WLAN 238 #define KEY_UWB 239 #define KEY_UNKNOWN 240 #define KEY_VIDEO_NEXT 241 /* drive next video source */ #define KEY_VIDEO_PREV 242 /* drive previous video source */ #define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */ #define KEY_BRIGHTNESS_AUTO 244 /* Set Auto Brightness: manual brightness control is off, rely on ambient */ #define KEY_BRIGHTNESS_ZERO KEY_BRIGHTNESS_AUTO #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WWAN 246 /* Wireless WAN (LTE, UMTS, GSM, etc.) */ #define KEY_WIMAX KEY_WWAN #define KEY_RFKILL 247 /* Key that controls all radios */ #define KEY_MICMUTE 248 /* Mute / unmute the microphone */ /* Code 255 is reserved for special needs of AT keyboard driver */ #define BTN_MISC 0x100 #define BTN_0 0x100 #define BTN_1 0x101 #define BTN_2 0x102 #define BTN_3 0x103 #define BTN_4 0x104 #define BTN_5 0x105 #define BTN_6 0x106 #define BTN_7 0x107 #define BTN_8 0x108 #define BTN_9 0x109 #define BTN_MOUSE 0x110 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_SIDE 0x113 #define BTN_EXTRA 0x114 #define BTN_FORWARD 0x115 #define BTN_BACK 0x116 #define BTN_TASK 0x117 #define BTN_JOYSTICK 0x120 #define BTN_TRIGGER 0x120 #define BTN_THUMB 0x121 #define BTN_THUMB2 0x122 #define BTN_TOP 0x123 #define BTN_TOP2 0x124 #define BTN_PINKIE 0x125 #define BTN_BASE 0x126 #define BTN_BASE2 0x127 #define BTN_BASE3 0x128 #define BTN_BASE4 0x129 #define BTN_BASE5 0x12a #define BTN_BASE6 0x12b #define BTN_DEAD 0x12f #define BTN_GAMEPAD 0x130 #define BTN_SOUTH 0x130 #define BTN_A BTN_SOUTH #define BTN_EAST 0x131 #define BTN_B BTN_EAST #define BTN_C 0x132 #define BTN_NORTH 0x133 #define BTN_X BTN_NORTH #define BTN_WEST 0x134 #define BTN_Y BTN_WEST #define BTN_Z 0x135 #define BTN_TL 0x136 #define BTN_TR 0x137 #define BTN_TL2 0x138 #define BTN_TR2 0x139 #define BTN_SELECT 0x13a #define BTN_START 0x13b #define BTN_MODE 0x13c #define BTN_THUMBL 0x13d #define BTN_THUMBR 0x13e #define BTN_DIGI 0x140 #define BTN_TOOL_PEN 0x140 #define BTN_TOOL_RUBBER 0x141 #define BTN_TOOL_BRUSH 0x142 #define BTN_TOOL_PENCIL 0x143 #define BTN_TOOL_AIRBRUSH 0x144 #define BTN_TOOL_FINGER 0x145 #define BTN_TOOL_MOUSE 0x146 #define BTN_TOOL_LENS 0x147 #define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */ #define BTN_TOUCH 0x14a #define BTN_STYLUS 0x14b #define BTN_STYLUS2 0x14c #define BTN_TOOL_DOUBLETAP 0x14d #define BTN_TOOL_TRIPLETAP 0x14e #define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */ #define BTN_WHEEL 0x150 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define KEY_OK 0x160 #define KEY_SELECT 0x161 #define KEY_GOTO 0x162 #define KEY_CLEAR 0x163 #define KEY_POWER2 0x164 #define KEY_OPTION 0x165 #define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */ #define KEY_TIME 0x167 #define KEY_VENDOR 0x168 #define KEY_ARCHIVE 0x169 #define KEY_PROGRAM 0x16a /* Media Select Program Guide */ #define KEY_CHANNEL 0x16b #define KEY_FAVORITES 0x16c #define KEY_EPG 0x16d #define KEY_PVR 0x16e /* Media Select Home */ #define KEY_MHP 0x16f #define KEY_LANGUAGE 0x170 #define KEY_TITLE 0x171 #define KEY_SUBTITLE 0x172 #define KEY_ANGLE 0x173 #define KEY_ZOOM 0x174 #define KEY_MODE 0x175 #define KEY_KEYBOARD 0x176 #define KEY_SCREEN 0x177 #define KEY_PC 0x178 /* Media Select Computer */ #define KEY_TV 0x179 /* Media Select TV */ #define KEY_TV2 0x17a /* Media Select Cable */ #define KEY_VCR 0x17b /* Media Select VCR */ #define KEY_VCR2 0x17c /* VCR Plus */ #define KEY_SAT 0x17d /* Media Select Satellite */ #define KEY_SAT2 0x17e #define KEY_CD 0x17f /* Media Select CD */ #define KEY_TAPE 0x180 /* Media Select Tape */ #define KEY_RADIO 0x181 #define KEY_TUNER 0x182 /* Media Select Tuner */ #define KEY_PLAYER 0x183 #define KEY_TEXT 0x184 #define KEY_DVD 0x185 /* Media Select DVD */ #define KEY_AUX 0x186 #define KEY_MP3 0x187 #define KEY_AUDIO 0x188 /* AL Audio Browser */ #define KEY_VIDEO 0x189 /* AL Movie Browser */ #define KEY_DIRECTORY 0x18a #define KEY_LIST 0x18b #define KEY_MEMO 0x18c /* Media Select Messages */ #define KEY_CALENDAR 0x18d #define KEY_RED 0x18e #define KEY_GREEN 0x18f #define KEY_YELLOW 0x190 #define KEY_BLUE 0x191 #define KEY_CHANNELUP 0x192 /* Channel Increment */ #define KEY_CHANNELDOWN 0x193 /* Channel Decrement */ #define KEY_FIRST 0x194 #define KEY_LAST 0x195 /* Recall Last */ #define KEY_AB 0x196 #define KEY_NEXT 0x197 #define KEY_RESTART 0x198 #define KEY_SLOW 0x199 #define KEY_SHUFFLE 0x19a #define KEY_BREAK 0x19b #define KEY_PREVIOUS 0x19c #define KEY_DIGITS 0x19d #define KEY_TEEN 0x19e #define KEY_TWEN 0x19f #define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */ #define KEY_GAMES 0x1a1 /* Media Select Games */ #define KEY_ZOOMIN 0x1a2 /* AC Zoom In */ #define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */ #define KEY_ZOOMRESET 0x1a4 /* AC Zoom */ #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */ #define KEY_EDITOR 0x1a6 /* AL Text Editor */ #define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */ #define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */ #define KEY_PRESENTATION 0x1a9 /* AL Presentation App */ #define KEY_DATABASE 0x1aa /* AL Database App */ #define KEY_NEWS 0x1ab /* AL Newsreader */ #define KEY_VOICEMAIL 0x1ac /* AL Voicemail */ #define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */ #define KEY_MESSENGER 0x1ae /* AL Instant Messaging */ #define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */ #define KEY_BRIGHTNESS_TOGGLE KEY_DISPLAYTOGGLE #define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */ #define KEY_LOGOFF 0x1b1 /* AL Logoff */ #define KEY_DOLLAR 0x1b2 #define KEY_EURO 0x1b3 #define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */ #define KEY_FRAMEFORWARD 0x1b5 #define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */ #define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */ #define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */ #define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */ #define KEY_IMAGES 0x1ba /* AL Image Browser */ #define KEY_DEL_EOL 0x1c0 #define KEY_DEL_EOS 0x1c1 #define KEY_INS_LINE 0x1c2 #define KEY_DEL_LINE 0x1c3 #define KEY_FN 0x1d0 #define KEY_FN_ESC 0x1d1 #define KEY_FN_F1 0x1d2 #define KEY_FN_F2 0x1d3 #define KEY_FN_F3 0x1d4 #define KEY_FN_F4 0x1d5 #define KEY_FN_F5 0x1d6 #define KEY_FN_F6 0x1d7 #define KEY_FN_F7 0x1d8 #define KEY_FN_F8 0x1d9 #define KEY_FN_F9 0x1da #define KEY_FN_F10 0x1db #define KEY_FN_F11 0x1dc #define KEY_FN_F12 0x1dd #define KEY_FN_1 0x1de #define KEY_FN_2 0x1df #define KEY_FN_D 0x1e0 #define KEY_FN_E 0x1e1 #define KEY_FN_F 0x1e2 #define KEY_FN_S 0x1e3 #define KEY_FN_B 0x1e4 #define KEY_BRL_DOT1 0x1f1 #define KEY_BRL_DOT2 0x1f2 #define KEY_BRL_DOT3 0x1f3 #define KEY_BRL_DOT4 0x1f4 #define KEY_BRL_DOT5 0x1f5 #define KEY_BRL_DOT6 0x1f6 #define KEY_BRL_DOT7 0x1f7 #define KEY_BRL_DOT8 0x1f8 #define KEY_BRL_DOT9 0x1f9 #define KEY_BRL_DOT10 0x1fa #define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */ #define KEY_NUMERIC_1 0x201 /* and other keypads */ #define KEY_NUMERIC_2 0x202 #define KEY_NUMERIC_3 0x203 #define KEY_NUMERIC_4 0x204 #define KEY_NUMERIC_5 0x205 #define KEY_NUMERIC_6 0x206 #define KEY_NUMERIC_7 0x207 #define KEY_NUMERIC_8 0x208 #define KEY_NUMERIC_9 0x209 #define KEY_NUMERIC_STAR 0x20a #define KEY_NUMERIC_POUND 0x20b #define KEY_NUMERIC_A 0x20c /* Phone key A - HUT Telephony 0xb9 */ #define KEY_NUMERIC_B 0x20d #define KEY_NUMERIC_C 0x20e #define KEY_NUMERIC_D 0x20f #define KEY_CAMERA_FOCUS 0x210 #define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */ #define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */ #define KEY_TOUCHPAD_ON 0x213 #define KEY_TOUCHPAD_OFF 0x214 #define KEY_CAMERA_ZOOMIN 0x215 #define KEY_CAMERA_ZOOMOUT 0x216 #define KEY_CAMERA_UP 0x217 #define KEY_CAMERA_DOWN 0x218 #define KEY_CAMERA_LEFT 0x219 #define KEY_CAMERA_RIGHT 0x21a #define KEY_ATTENDANT_ON 0x21b #define KEY_ATTENDANT_OFF 0x21c #define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */ #define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */ #define BTN_DPAD_UP 0x220 #define BTN_DPAD_DOWN 0x221 #define BTN_DPAD_LEFT 0x222 #define BTN_DPAD_RIGHT 0x223 #define KEY_ALS_TOGGLE 0x230 /* Ambient light sensor */ #define KEY_BUTTONCONFIG 0x240 /* AL Button Configuration */ #define KEY_TASKMANAGER 0x241 /* AL Task/Project Manager */ #define KEY_JOURNAL 0x242 /* AL Log/Journal/Timecard */ #define KEY_CONTROLPANEL 0x243 /* AL Control Panel */ #define KEY_APPSELECT 0x244 /* AL Select Task/Application */ #define KEY_SCREENSAVER 0x245 /* AL Screen Saver */ #define KEY_VOICECOMMAND 0x246 /* Listening Voice Command */ #define KEY_BRIGHTNESS_MIN 0x250 /* Set Brightness to Minimum */ #define KEY_BRIGHTNESS_MAX 0x251 /* Set Brightness to Maximum */ #define KEY_KBDINPUTASSIST_PREV 0x260 #define KEY_KBDINPUTASSIST_NEXT 0x261 #define KEY_KBDINPUTASSIST_PREVGROUP 0x262 #define KEY_KBDINPUTASSIST_NEXTGROUP 0x263 #define KEY_KBDINPUTASSIST_ACCEPT 0x264 #define KEY_KBDINPUTASSIST_CANCEL 0x265 #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 #define BTN_TRIGGER_HAPPY2 0x2c1 #define BTN_TRIGGER_HAPPY3 0x2c2 #define BTN_TRIGGER_HAPPY4 0x2c3 #define BTN_TRIGGER_HAPPY5 0x2c4 #define BTN_TRIGGER_HAPPY6 0x2c5 #define BTN_TRIGGER_HAPPY7 0x2c6 #define BTN_TRIGGER_HAPPY8 0x2c7 #define BTN_TRIGGER_HAPPY9 0x2c8 #define BTN_TRIGGER_HAPPY10 0x2c9 #define BTN_TRIGGER_HAPPY11 0x2ca #define BTN_TRIGGER_HAPPY12 0x2cb #define BTN_TRIGGER_HAPPY13 0x2cc #define BTN_TRIGGER_HAPPY14 0x2cd #define BTN_TRIGGER_HAPPY15 0x2ce #define BTN_TRIGGER_HAPPY16 0x2cf #define BTN_TRIGGER_HAPPY17 0x2d0 #define BTN_TRIGGER_HAPPY18 0x2d1 #define BTN_TRIGGER_HAPPY19 0x2d2 #define BTN_TRIGGER_HAPPY20 0x2d3 #define BTN_TRIGGER_HAPPY21 0x2d4 #define BTN_TRIGGER_HAPPY22 0x2d5 #define BTN_TRIGGER_HAPPY23 0x2d6 #define BTN_TRIGGER_HAPPY24 0x2d7 #define BTN_TRIGGER_HAPPY25 0x2d8 #define BTN_TRIGGER_HAPPY26 0x2d9 #define BTN_TRIGGER_HAPPY27 0x2da #define BTN_TRIGGER_HAPPY28 0x2db #define BTN_TRIGGER_HAPPY29 0x2dc #define BTN_TRIGGER_HAPPY30 0x2dd #define BTN_TRIGGER_HAPPY31 0x2de #define BTN_TRIGGER_HAPPY32 0x2df #define BTN_TRIGGER_HAPPY33 0x2e0 #define BTN_TRIGGER_HAPPY34 0x2e1 #define BTN_TRIGGER_HAPPY35 0x2e2 #define BTN_TRIGGER_HAPPY36 0x2e3 #define BTN_TRIGGER_HAPPY37 0x2e4 #define BTN_TRIGGER_HAPPY38 0x2e5 #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff #define KEY_CNT (KEY_MAX+1) /* * Relative axes */ #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_RX 0x03 #define REL_RY 0x04 #define REL_RZ 0x05 #define REL_HWHEEL 0x06 #define REL_DIAL 0x07 #define REL_WHEEL 0x08 #define REL_MISC 0x09 #define REL_MAX 0x0f #define REL_CNT (REL_MAX+1) /* * Absolute axes */ #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 #define ABS_RX 0x03 #define ABS_RY 0x04 #define ABS_RZ 0x05 #define ABS_THROTTLE 0x06 #define ABS_RUDDER 0x07 #define ABS_WHEEL 0x08 #define ABS_GAS 0x09 #define ABS_BRAKE 0x0a #define ABS_HAT0X 0x10 #define ABS_HAT0Y 0x11 #define ABS_HAT1X 0x12 #define ABS_HAT1Y 0x13 #define ABS_HAT2X 0x14 #define ABS_HAT2Y 0x15 #define ABS_HAT3X 0x16 #define ABS_HAT3Y 0x17 #define ABS_PRESSURE 0x18 #define ABS_DISTANCE 0x19 #define ABS_TILT_X 0x1a #define ABS_TILT_Y 0x1b #define ABS_TOOL_WIDTH 0x1c #define ABS_VOLUME 0x20 #define ABS_MISC 0x28 #define ABS_MT_SLOT 0x2f /* MT slot being modified */ #define ABS_MT_TOUCH_MAJOR 0x30 /* Major axis of touching ellipse */ #define ABS_MT_TOUCH_MINOR 0x31 /* Minor axis (omit if circular) */ #define ABS_MT_WIDTH_MAJOR 0x32 /* Major axis of approaching ellipse */ #define ABS_MT_WIDTH_MINOR 0x33 /* Minor axis (omit if circular) */ #define ABS_MT_ORIENTATION 0x34 /* Ellipse orientation */ #define ABS_MT_POSITION_X 0x35 /* Center X touch position */ #define ABS_MT_POSITION_Y 0x36 /* Center Y touch position */ #define ABS_MT_TOOL_TYPE 0x37 /* Type of touching device */ #define ABS_MT_BLOB_ID 0x38 /* Group a set of packets as a blob */ #define ABS_MT_TRACKING_ID 0x39 /* Unique ID of initiated contact */ #define ABS_MT_PRESSURE 0x3a /* Pressure on contact area */ #define ABS_MT_DISTANCE 0x3b /* Contact hover distance */ #define ABS_MT_TOOL_X 0x3c /* Center X tool position */ #define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */ #define ABS_MAX 0x3f #define ABS_CNT (ABS_MAX+1) /* * Switch events */ #define SW_LID 0x00 /* set = lid shut */ #define SW_TABLET_MODE 0x01 /* set = tablet mode */ #define SW_HEADPHONE_INSERT 0x02 /* set = inserted */ #define SW_RFKILL_ALL 0x03 /* rfkill master switch, type "any" set = radio enabled */ #define SW_RADIO SW_RFKILL_ALL /* deprecated */ #define SW_MICROPHONE_INSERT 0x04 /* set = inserted */ #define SW_DOCK 0x05 /* set = plugged into dock */ #define SW_LINEOUT_INSERT 0x06 /* set = inserted */ #define SW_JACK_PHYSICAL_INSERT 0x07 /* set = mechanical switch set */ #define SW_VIDEOOUT_INSERT 0x08 /* set = inserted */ #define SW_CAMERA_LENS_COVER 0x09 /* set = lens covered */ #define SW_KEYPAD_SLIDE 0x0a /* set = keypad slide out */ #define SW_FRONT_PROXIMITY 0x0b /* set = front proximity sensor active */ #define SW_ROTATE_LOCK 0x0c /* set = rotate locked/disabled */ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_MAX 0x0f #define SW_CNT (SW_MAX+1) /* * Misc events */ #define MSC_SERIAL 0x00 #define MSC_PULSELED 0x01 #define MSC_GESTURE 0x02 #define MSC_RAW 0x03 #define MSC_SCAN 0x04 #define MSC_TIMESTAMP 0x05 #define MSC_MAX 0x07 #define MSC_CNT (MSC_MAX+1) /* * LEDs */ #define LED_NUML 0x00 #define LED_CAPSL 0x01 #define LED_SCROLLL 0x02 #define LED_COMPOSE 0x03 #define LED_KANA 0x04 #define LED_SLEEP 0x05 #define LED_SUSPEND 0x06 #define LED_MUTE 0x07 #define LED_MISC 0x08 #define LED_MAIL 0x09 #define LED_CHARGING 0x0a #define LED_MAX 0x0f #define LED_CNT (LED_MAX+1) /* * Autorepeat values */ #define REP_DELAY 0x00 #define REP_PERIOD 0x01 #define REP_MAX 0x01 #define REP_CNT (REP_MAX+1) /* * Sounds */ #define SND_CLICK 0x00 #define SND_BELL 0x01 #define SND_TONE 0x02 #define SND_MAX 0x07 #define SND_CNT (SND_MAX+1) #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) #endif /* _DT_BINDINGS_INPUT_INPUT_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/interrupt-controller/irq.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides constants for most IRQ bindings. * * Most IRQ bindings include a flags cell as part of the IRQ specifier. * In most cases, the format of the flags cell uses the standard values * defined in this header. */ #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H #define IRQ_TYPE_NONE 0 #define IRQ_TYPE_EDGE_RISING 1 #define IRQ_TYPE_EDGE_FALLING 2 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) #define IRQ_TYPE_LEVEL_HIGH 4 #define IRQ_TYPE_LEVEL_LOW 8 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/net/mscc-phy-vsc8531.h ================================================ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Device Tree constants for Microsemi VSC8531 PHY * * Author: Nagaraju Lakkaraju * * Copyright (c) 2017 Microsemi Corporation */ #ifndef _DT_BINDINGS_MSCC_VSC8531_H #define _DT_BINDINGS_MSCC_VSC8531_H /* PHY LED Modes */ #define VSC8531_LINK_ACTIVITY 0 #define VSC8531_LINK_1000_ACTIVITY 1 #define VSC8531_LINK_100_ACTIVITY 2 #define VSC8531_LINK_10_ACTIVITY 3 #define VSC8531_LINK_100_1000_ACTIVITY 4 #define VSC8531_LINK_10_1000_ACTIVITY 5 #define VSC8531_LINK_10_100_ACTIVITY 6 #define VSC8584_LINK_100FX_1000X_ACTIVITY 7 #define VSC8531_DUPLEX_COLLISION 8 #define VSC8531_COLLISION 9 #define VSC8531_ACTIVITY 10 #define VSC8584_100FX_1000X_ACTIVITY 11 #define VSC8531_AUTONEG_FAULT 12 #define VSC8531_SERIAL_MODE 13 #define VSC8531_FORCE_LED_OFF 14 #define VSC8531_FORCE_LED_ON 15 #define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 #define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 #define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 #define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 #define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 #define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 #define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 #define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/net/ti-dp83867.h ================================================ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Device Tree constants for the Texas Instruments DP83867 PHY * * Author: Dan Murphy * * Copyright: (C) 2015 Texas Instruments, Inc. */ #ifndef _DT_BINDINGS_TI_DP83867_H #define _DT_BINDINGS_TI_DP83867_H /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 #define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 #define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 #define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 /* RGMIIDCTL internal delay for rx and tx */ #define DP83867_RGMIIDCTL_250_PS 0x0 #define DP83867_RGMIIDCTL_500_PS 0x1 #define DP83867_RGMIIDCTL_750_PS 0x2 #define DP83867_RGMIIDCTL_1_NS 0x3 #define DP83867_RGMIIDCTL_1_25_NS 0x4 #define DP83867_RGMIIDCTL_1_50_NS 0x5 #define DP83867_RGMIIDCTL_1_75_NS 0x6 #define DP83867_RGMIIDCTL_2_00_NS 0x7 #define DP83867_RGMIIDCTL_2_25_NS 0x8 #define DP83867_RGMIIDCTL_2_50_NS 0x9 #define DP83867_RGMIIDCTL_2_75_NS 0xa #define DP83867_RGMIIDCTL_3_00_NS 0xb #define DP83867_RGMIIDCTL_3_25_NS 0xc #define DP83867_RGMIIDCTL_3_50_NS 0xd #define DP83867_RGMIIDCTL_3_75_NS 0xe #define DP83867_RGMIIDCTL_4_00_NS 0xf /* IO_MUX_CFG - Clock output selection */ #define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 #define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 #define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 #define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 #define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 #define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 #define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 #define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 #define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 #define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA #define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB #define DP83867_CLK_O_SEL_REF_CLK 0xC /* Special flag to indicate clock should be off */ #define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/phy/phy.h ================================================ /* * * This header provides constants for the phy framework * * Copyright (C) 2014 STMicroelectronics * Author: Gabriel Fernandez * License terms: GNU General Public License (GPL), version 2 */ #ifndef _DT_BINDINGS_PHY #define _DT_BINDINGS_PHY #define PHY_NONE 0 #define PHY_TYPE_SATA 1 #define PHY_TYPE_PCIE 2 #define PHY_TYPE_USB2 3 #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 #define PHY_TYPE_XPCS 7 #define PHY_TYPE_SGMII 8 #define PHY_TYPE_QSGMII 9 #endif /* _DT_BINDINGS_PHY */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/pinctrl/pinctrl-zynqmp.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * MIO pin configuration defines for Xilinx ZynqMP * * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H #define _DT_BINDINGS_PINCTRL_ZYNQMP_H /* Bit value for different voltage levels */ #define IO_STANDARD_LVCMOS33 0 #define IO_STANDARD_LVCMOS18 1 /* Bit values for Slew Rates */ #define SLEW_RATE_FAST 0 #define SLEW_RATE_SLOW 1 /* Bit values for Pin drive strength */ #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 #define DRIVE_STRENGTH_8MA 8 #define DRIVE_STRENGTH_12MA 12 #endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-net-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. */ #ifndef _DT_BINDINGS_VERSAL_NET_POWER_H #define _DT_BINDINGS_VERSAL_NET_POWER_H #include #define PM_DEV_USB_1 (0x182240D7U) #define PM_DEV_FPD_SWDT_0 (0x182240DBU) #define PM_DEV_FPD_SWDT_1 (0x182240DCU) #define PM_DEV_FPD_SWDT_2 (0x182240DDU) #define PM_DEV_FPD_SWDT_3 (0x182240DEU) #define PM_DEV_TCM_A_0A (0x183180CBU) #define PM_DEV_TCM_A_0B (0x183180CCU) #define PM_DEV_TCM_A_0C (0x183180CDU) #define PM_DEV_RPU_A_0 (0x181100BFU) #define PM_DEV_LPD_SWDT_0 (0x182240D9U) #define PM_DEV_LPD_SWDT_1 (0x182240DAU) /* Remove Versal specific node IDs */ #undef PM_DEV_RPU0_0 #undef PM_DEV_RPU0_1 #undef PM_DEV_OCM_0 #undef PM_DEV_OCM_1 #undef PM_DEV_OCM_2 #undef PM_DEV_OCM_3 #undef PM_DEV_TCM_0_A #undef PM_DEV_TCM_1_A #undef PM_DEV_TCM_0_B #undef PM_DEV_TCM_1_B #undef PM_DEV_SWDT_FPD #undef PM_DEV_AI #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2019-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) #define PM_DEV_SPI_0 (0x1822401bU) #define PM_DEV_SPI_1 (0x1822401cU) #define PM_DEV_I2C_0 (0x1822401dU) #define PM_DEV_I2C_1 (0x1822401eU) #define PM_DEV_I2C_PMC (0x1822402dU) #define PM_DEV_CAN_FD_0 (0x1822401fU) #define PM_DEV_CAN_FD_1 (0x18224020U) #define PM_DEV_UART_0 (0x18224021U) #define PM_DEV_UART_1 (0x18224022U) #define PM_DEV_GPIO (0x18224023U) #define PM_DEV_TTC_0 (0x18224024U) #define PM_DEV_TTC_1 (0x18224025U) #define PM_DEV_TTC_2 (0x18224026U) #define PM_DEV_TTC_3 (0x18224027U) #define PM_DEV_SWDT_LPD (0x18224028U) #define PM_DEV_SWDT_FPD (0x18224029U) #define PM_DEV_OSPI (0x1822402aU) #define PM_DEV_QSPI (0x1822402bU) #define PM_DEV_GPIO_PMC (0x1822402cU) #define PM_DEV_SDIO_0 (0x1822402eU) #define PM_DEV_SDIO_1 (0x1822402fU) #define PM_DEV_RTC (0x18224034U) #define PM_DEV_ADMA_0 (0x18224035U) #define PM_DEV_ADMA_1 (0x18224036U) #define PM_DEV_ADMA_2 (0x18224037U) #define PM_DEV_ADMA_3 (0x18224038U) #define PM_DEV_ADMA_4 (0x18224039U) #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) #define PM_DEV_AI (0x18224072U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-versal-regnode.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2022-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_REGNODE_H #define _DT_BINDINGS_VERSAL_REGNODE_H #define PM_REGNODE_SYSMON_ROOT_0 (0x18224055U) #define PM_REGNODE_SYSMON_ROOT_1 (0x18225055U) #define PM_REGNODE_SYSMON_ROOT_2 (0x18226055U) #define PM_REGNODE_SYSMON_ROOT_3 (0x18227055U) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/power/xlnx-zynqmp-power.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 #define PD_TTC_1 25 #define PD_TTC_2 26 #define PD_TTC_3 27 #define PD_SATA 28 #define PD_ETH_0 29 #define PD_ETH_1 30 #define PD_ETH_2 31 #define PD_ETH_3 32 #define PD_UART_0 33 #define PD_UART_1 34 #define PD_SPI_0 35 #define PD_SPI_1 36 #define PD_I2C_0 37 #define PD_I2C_1 38 #define PD_SD_0 39 #define PD_SD_1 40 #define PD_DP 41 #define PD_GDMA 42 #define PD_ADMA 43 #define PD_NAND 44 #define PD_QSPI 45 #define PD_GPIO 46 #define PD_CAN_0 47 #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 #define PD_PL 69 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-versal-net-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_NET_RESETS_H #define _DT_BINDINGS_VERSAL_NET_RESETS_H #include "xlnx-versal-resets.h" #define VERSAL_RST_USB_1 (0xC1040C6U) /* Remove Versal specific reset IDs */ #undef VERSAL_RST_ACPU_0_POR #undef VERSAL_RST_ACPU_1_POR #undef VERSAL_RST_OCM2_POR #undef VERSAL_RST_APU #undef VERSAL_RST_ACPU_0 #undef VERSAL_RST_ACPU_1 #undef VERSAL_RST_ACPU_L2 #undef VERSAL_RST_RPU_ISLAND #undef VERSAL_RST_RPU_AMBA #undef VERSAL_RST_R5_0 #undef VERSAL_RST_R5_1 #undef VERSAL_RST_OCM2_RST #undef VERSAL_RST_I2C_PMC #undef VERSAL_RST_I2C_0 #undef VERSAL_RST_I2C_1 #undef VERSAL_RST_SWDT_FPD #undef VERSAL_RST_SWDT_LPD #undef VERSAL_RST_USB #undef VERSAL_RST_DPC #undef VERSAL_RST_DBG_TRACE #undef VERSAL_RST_DBG_TSTMP #undef VERSAL_RST_RPU0_DBG #undef VERSAL_RST_RPU1_DBG #undef VERSAL_RST_HSDP #undef VERSAL_RST_CPMDBG #undef VERSAL_RST_PCIE_CFG #undef VERSAL_RST_PCIE_CORE0 #undef VERSAL_RST_PCIE_CORE1 #undef VERSAL_RST_PCIE_DMA #undef VERSAL_RST_L2_0 #undef VERSAL_RST_L2_1 #undef VERSAL_RST_ADDR_REMAP #undef VERSAL_RST_CPI0 #undef VERSAL_RST_CPI1 #undef VERSAL_RST_XRAM #undef VERSAL_RST_AIE_ARRAY #undef VERSAL_RST_AIE_SHIM #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-versal-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2020-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_VERSAL_RESETS_H #define _DT_BINDINGS_VERSAL_RESETS_H #define VERSAL_RST_PMC_POR (0xc30c001U) #define VERSAL_RST_PMC (0xc410002U) #define VERSAL_RST_PS_POR (0xc30c003U) #define VERSAL_RST_PL_POR (0xc30c004U) #define VERSAL_RST_NOC_POR (0xc30c005U) #define VERSAL_RST_FPD_POR (0xc30c006U) #define VERSAL_RST_ACPU_0_POR (0xc30c007U) #define VERSAL_RST_ACPU_1_POR (0xc30c008U) #define VERSAL_RST_OCM2_POR (0xc30c009U) #define VERSAL_RST_PS_SRST (0xc41000aU) #define VERSAL_RST_PL_SRST (0xc41000bU) #define VERSAL_RST_NOC (0xc41000cU) #define VERSAL_RST_NPI (0xc41000dU) #define VERSAL_RST_SYS_RST_1 (0xc41000eU) #define VERSAL_RST_SYS_RST_2 (0xc41000fU) #define VERSAL_RST_SYS_RST_3 (0xc410010U) #define VERSAL_RST_FPD (0xc410011U) #define VERSAL_RST_PL0 (0xc410012U) #define VERSAL_RST_PL1 (0xc410013U) #define VERSAL_RST_PL2 (0xc410014U) #define VERSAL_RST_PL3 (0xc410015U) #define VERSAL_RST_APU (0xc410016U) #define VERSAL_RST_ACPU_0 (0xc410017U) #define VERSAL_RST_ACPU_1 (0xc410018U) #define VERSAL_RST_ACPU_L2 (0xc410019U) #define VERSAL_RST_ACPU_GIC (0xc41001aU) #define VERSAL_RST_RPU_ISLAND (0xc41001bU) #define VERSAL_RST_RPU_AMBA (0xc41001cU) #define VERSAL_RST_R5_0 (0xc41001dU) #define VERSAL_RST_R5_1 (0xc41001eU) #define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) #define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) #define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) #define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) #define VERSAL_RST_SYSMON_LPD (0xc410023U) #define VERSAL_RST_PDMA_RST1 (0xc410024U) #define VERSAL_RST_PDMA_RST0 (0xc410025U) #define VERSAL_RST_ADMA (0xc410026U) #define VERSAL_RST_TIMESTAMP (0xc410027U) #define VERSAL_RST_OCM (0xc410028U) #define VERSAL_RST_OCM2_RST (0xc410029U) #define VERSAL_RST_IPI (0xc41002aU) #define VERSAL_RST_SBI (0xc41002bU) #define VERSAL_RST_LPD (0xc41002cU) #define VERSAL_RST_QSPI (0xc10402dU) #define VERSAL_RST_OSPI (0xc10402eU) #define VERSAL_RST_SDIO_0 (0xc10402fU) #define VERSAL_RST_SDIO_1 (0xc104030U) #define VERSAL_RST_I2C_PMC (0xc104031U) #define VERSAL_RST_GPIO_PMC (0xc104032U) #define VERSAL_RST_GEM_0 (0xc104033U) #define VERSAL_RST_GEM_1 (0xc104034U) #define VERSAL_RST_SPARE (0xc104035U) #define VERSAL_RST_USB_0 (0xc104036U) #define VERSAL_RST_UART_0 (0xc104037U) #define VERSAL_RST_UART_1 (0xc104038U) #define VERSAL_RST_SPI_0 (0xc104039U) #define VERSAL_RST_SPI_1 (0xc10403aU) #define VERSAL_RST_CAN_FD_0 (0xc10403bU) #define VERSAL_RST_CAN_FD_1 (0xc10403cU) #define VERSAL_RST_I2C_0 (0xc10403dU) #define VERSAL_RST_I2C_1 (0xc10403eU) #define VERSAL_RST_GPIO_LPD (0xc10403fU) #define VERSAL_RST_TTC_0 (0xc104040U) #define VERSAL_RST_TTC_1 (0xc104041U) #define VERSAL_RST_TTC_2 (0xc104042U) #define VERSAL_RST_TTC_3 (0xc104043U) #define VERSAL_RST_SWDT_FPD (0xc104044U) #define VERSAL_RST_SWDT_LPD (0xc104045U) #define VERSAL_RST_USB (0xc104046U) #define VERSAL_RST_DPC (0xc208047U) #define VERSAL_RST_PMCDBG (0xc208048U) #define VERSAL_RST_DBG_TRACE (0xc208049U) #define VERSAL_RST_DBG_FPD (0xc20804aU) #define VERSAL_RST_DBG_TSTMP (0xc20804bU) #define VERSAL_RST_RPU0_DBG (0xc20804cU) #define VERSAL_RST_RPU1_DBG (0xc20804dU) #define VERSAL_RST_HSDP (0xc20804eU) #define VERSAL_RST_DBG_LPD (0xc20804fU) #define VERSAL_RST_CPM_POR (0xc30c050U) #define VERSAL_RST_CPM (0xc410051U) #define VERSAL_RST_CPMDBG (0xc208052U) #define VERSAL_RST_PCIE_CFG (0xc410053U) #define VERSAL_RST_PCIE_CORE0 (0xc410054U) #define VERSAL_RST_PCIE_CORE1 (0xc410055U) #define VERSAL_RST_PCIE_DMA (0xc410056U) #define VERSAL_RST_CMN (0xc410057U) #define VERSAL_RST_L2_0 (0xc410058U) #define VERSAL_RST_L2_1 (0xc410059U) #define VERSAL_RST_ADDR_REMAP (0xc41005aU) #define VERSAL_RST_CPI0 (0xc41005bU) #define VERSAL_RST_CPI1 (0xc41005cU) #define VERSAL_RST_XRAM (0xc30c05dU) #define VERSAL_RST_AIE_ARRAY (0xc10405eU) #define VERSAL_RST_AIE_SHIM (0xc10405fU) #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/include/dt-bindings/reset/xlnx-zynqmp-resets.h ================================================ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2018-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. */ #ifndef _DT_BINDINGS_ZYNQMP_RESETS_H #define _DT_BINDINGS_ZYNQMP_RESETS_H #define ZYNQMP_RESET_PCIE_CFG 0 #define ZYNQMP_RESET_PCIE_BRIDGE 1 #define ZYNQMP_RESET_PCIE_CTRL 2 #define ZYNQMP_RESET_DP 3 #define ZYNQMP_RESET_SWDT_CRF 4 #define ZYNQMP_RESET_AFI_FM5 5 #define ZYNQMP_RESET_AFI_FM4 6 #define ZYNQMP_RESET_AFI_FM3 7 #define ZYNQMP_RESET_AFI_FM2 8 #define ZYNQMP_RESET_AFI_FM1 9 #define ZYNQMP_RESET_AFI_FM0 10 #define ZYNQMP_RESET_GDMA 11 #define ZYNQMP_RESET_GPU_PP1 12 #define ZYNQMP_RESET_GPU_PP0 13 #define ZYNQMP_RESET_GPU 14 #define ZYNQMP_RESET_GT 15 #define ZYNQMP_RESET_SATA 16 #define ZYNQMP_RESET_ACPU3_PWRON 17 #define ZYNQMP_RESET_ACPU2_PWRON 18 #define ZYNQMP_RESET_ACPU1_PWRON 19 #define ZYNQMP_RESET_ACPU0_PWRON 20 #define ZYNQMP_RESET_APU_L2 21 #define ZYNQMP_RESET_ACPU3 22 #define ZYNQMP_RESET_ACPU2 23 #define ZYNQMP_RESET_ACPU1 24 #define ZYNQMP_RESET_ACPU0 25 #define ZYNQMP_RESET_DDR 26 #define ZYNQMP_RESET_APM_FPD 27 #define ZYNQMP_RESET_SOFT 28 #define ZYNQMP_RESET_GEM0 29 #define ZYNQMP_RESET_GEM1 30 #define ZYNQMP_RESET_GEM2 31 #define ZYNQMP_RESET_GEM3 32 #define ZYNQMP_RESET_QSPI 33 #define ZYNQMP_RESET_UART0 34 #define ZYNQMP_RESET_UART1 35 #define ZYNQMP_RESET_SPI0 36 #define ZYNQMP_RESET_SPI1 37 #define ZYNQMP_RESET_SDIO0 38 #define ZYNQMP_RESET_SDIO1 39 #define ZYNQMP_RESET_CAN0 40 #define ZYNQMP_RESET_CAN1 41 #define ZYNQMP_RESET_I2C0 42 #define ZYNQMP_RESET_I2C1 43 #define ZYNQMP_RESET_TTC0 44 #define ZYNQMP_RESET_TTC1 45 #define ZYNQMP_RESET_TTC2 46 #define ZYNQMP_RESET_TTC3 47 #define ZYNQMP_RESET_SWDT_CRL 48 #define ZYNQMP_RESET_NAND 49 #define ZYNQMP_RESET_ADMA 50 #define ZYNQMP_RESET_GPIO 51 #define ZYNQMP_RESET_IOU_CC 52 #define ZYNQMP_RESET_TIMESTAMP 53 #define ZYNQMP_RESET_RPU_R50 54 #define ZYNQMP_RESET_RPU_R51 55 #define ZYNQMP_RESET_RPU_AMBA 56 #define ZYNQMP_RESET_OCM 57 #define ZYNQMP_RESET_RPU_PGE 58 #define ZYNQMP_RESET_USB0_CORERESET 59 #define ZYNQMP_RESET_USB1_CORERESET 60 #define ZYNQMP_RESET_USB0_HIBERRESET 61 #define ZYNQMP_RESET_USB1_HIBERRESET 62 #define ZYNQMP_RESET_USB0_APB 63 #define ZYNQMP_RESET_USB1_APB 64 #define ZYNQMP_RESET_IPI 65 #define ZYNQMP_RESET_APM_LPD 66 #define ZYNQMP_RESET_RTC 67 #define ZYNQMP_RESET_SYSMON 68 #define ZYNQMP_RESET_AFI_FM6 69 #define ZYNQMP_RESET_LPD_SWDT 70 #define ZYNQMP_RESET_FPD 71 #define ZYNQMP_RESET_RPU_DBG1 72 #define ZYNQMP_RESET_RPU_DBG0 73 #define ZYNQMP_RESET_DBG_LPD 74 #define ZYNQMP_RESET_DBG_FPD 75 #define ZYNQMP_RESET_APLL 76 #define ZYNQMP_RESET_DPLL 77 #define ZYNQMP_RESET_VPLL 78 #define ZYNQMP_RESET_IOPLL 79 #define ZYNQMP_RESET_RPLL 80 #define ZYNQMP_RESET_GPO3_PL_0 81 #define ZYNQMP_RESET_GPO3_PL_1 82 #define ZYNQMP_RESET_GPO3_PL_2 83 #define ZYNQMP_RESET_GPO3_PL_3 84 #define ZYNQMP_RESET_GPO3_PL_4 85 #define ZYNQMP_RESET_GPO3_PL_5 86 #define ZYNQMP_RESET_GPO3_PL_6 87 #define ZYNQMP_RESET_GPO3_PL_7 88 #define ZYNQMP_RESET_GPO3_PL_8 89 #define ZYNQMP_RESET_GPO3_PL_9 90 #define ZYNQMP_RESET_GPO3_PL_10 91 #define ZYNQMP_RESET_GPO3_PL_11 92 #define ZYNQMP_RESET_GPO3_PL_12 93 #define ZYNQMP_RESET_GPO3_PL_13 94 #define ZYNQMP_RESET_GPO3_PL_14 95 #define ZYNQMP_RESET_GPO3_PL_15 96 #define ZYNQMP_RESET_GPO3_PL_16 97 #define ZYNQMP_RESET_GPO3_PL_17 98 #define ZYNQMP_RESET_GPO3_PL_18 99 #define ZYNQMP_RESET_GPO3_PL_19 100 #define ZYNQMP_RESET_GPO3_PL_20 101 #define ZYNQMP_RESET_GPO3_PL_21 102 #define ZYNQMP_RESET_GPO3_PL_22 103 #define ZYNQMP_RESET_GPO3_PL_23 104 #define ZYNQMP_RESET_GPO3_PL_24 105 #define ZYNQMP_RESET_GPO3_PL_25 106 #define ZYNQMP_RESET_GPO3_PL_26 107 #define ZYNQMP_RESET_GPO3_PL_27 108 #define ZYNQMP_RESET_GPO3_PL_28 109 #define ZYNQMP_RESET_GPO3_PL_29 110 #define ZYNQMP_RESET_GPO3_PL_30 111 #define ZYNQMP_RESET_GPO3_PL_31 112 #define ZYNQMP_RESET_RPU_LS 113 #define ZYNQMP_RESET_PS_ONLY 114 #define ZYNQMP_RESET_PL 115 #define ZYNQMP_RESET_PS_PL0 116 #define ZYNQMP_RESET_PS_PL1 117 #define ZYNQMP_RESET_PS_PL2 118 #define ZYNQMP_RESET_PS_PL3 119 #endif ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal/versal-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-clk.h" #include "include/dt-bindings/power/xlnx-versal-power.h" #include "include/dt-bindings/power/xlnx-versal-regnode.h" #include "include/dt-bindings/reset/xlnx-versal-resets.h" / { pl_alt_ref_clk: pl_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN0_REF>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1_clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_clk CAN1_REF>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; }; versal_reset: reset-controller { compatible = "xlnx,versal-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,versal-pinctrl"; }; versal_sec_cfg: versal-sec-cfg { compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; }; &cpu0 { clocks = <&versal_clk ACPU>; }; &can0 { clocks = <&can0_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&can1_clk>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM0_REF>, <&versal_clk GEM0_TX>, <&versal_clk GEM0_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_clk LPD_LSBUS>, <&versal_clk GEM1_REF>, <&versal_clk GEM1_TX>, <&versal_clk GEM1_RX>, <&versal_clk GEM_TSU>; power-domains = <&versal_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_clk PMC_LSBUS_REF>; power-domains = <&versal_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_clk I2C0_REF>; power-domains = <&versal_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_clk I2C1_REF>; power-domains = <&versal_firmware PM_DEV_I2C_1>; }; &i2c2 { clocks = <&versal_clk I2C_REF>; power-domains = <&versal_firmware PM_DEV_I2C_PMC>; }; &lpd_dma_chan0 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_0>; }; &lpd_dma_chan1 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_1>; }; &lpd_dma_chan2 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_2>; }; &lpd_dma_chan3 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_3>; }; &lpd_dma_chan4 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_4>; }; &lpd_dma_chan5 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_5>; }; &lpd_dma_chan6 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_6>; }; &lpd_dma_chan7 { clocks = <&versal_clk ADMA>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_clk QSPI_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_clk OSPI_REF>; power-domains = <&versal_firmware PM_DEV_OSPI>; reset-names = "qspi"; resets = <&versal_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_clk UART0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_clk UART1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_clk SDIO0_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_clk SDIO1_REF>, <&versal_clk LPD_LSBUS>, <&versal_clk SD_DLL_REF>; power-domains = <&versal_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_clk SPI0_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_clk SPI1_REF>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_clk TTC0>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_clk TTC1>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_clk TTC2>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_clk TTC3>, <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_clk USB0_BUS_REF>, <&versal_clk USB3_DUAL_REF>; power-domains = <&versal_firmware PM_DEV_USB_0>; resets = <&versal_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_clk USB0_BUS_REF>; }; &watchdog { clocks = <&versal_clk FPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_FPD>; }; &watchdog1 { clocks = <&versal_clk LPD_LSBUS>; power-domains = <&versal_firmware PM_DEV_SWDT_LPD>; }; &sysmon0 { xlnx,nodeid = ; }; &sysmon1 { xlnx,nodeid = ; }; &sysmon2 { xlnx,nodeid = ; }; &sysmon3 { xlnx,nodeid = ; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal/versal-spp-pm.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { alt_ref_clk: alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; pl_alt_ref_clk: pl_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_firmware: versal-firmware { compatible = "xlnx,versal-firmware-wip"; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-clk"; clocks = <&ref_clk>, <&alt_ref_clk>, <&pl_alt_ref_clk>; clock-names = "ref_clk", "alt_ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 30 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; }; }; zynqmp_ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 30 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff3f0440 { reg = <0 0xff3f0440 0 0x20>, <0 0xff3f0460 0 0x20>, <0 0xff3f0280 0 0x20>, <0 0xff3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_clk 77>; }; &can0 { clocks = <&versal_clk 96>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401f>; }; &can1 { clocks = <&versal_clk 97>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224020>; }; &gem0 { clocks = <&versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&versal_clk 43>; power-domains = <&versal_firmware 0x18224019>; }; &gem1 { clocks = <&versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&versal_clk 43>; power-domains = <&versal_firmware 0x1822401a>; }; &gpio0 { clocks = <&versal_clk 82>; power-domains = <&versal_firmware 0x18224023>; }; &gpio1 { clocks = <&versal_clk 61>; power-domains = <&versal_firmware 0x18224023>; }; &i2c0 { clocks = <&versal_clk 98>; power-domains = <&versal_firmware 0x1822401d>; }; &i2c1 { clocks = <&versal_clk 99>; power-domains = <&versal_firmware 0x1822401e>; }; &lpd_dma_chan0 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224035>; }; &lpd_dma_chan1 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224036>; }; &lpd_dma_chan2 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224037>; }; &lpd_dma_chan3 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224038>; }; &lpd_dma_chan4 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224039>; }; &lpd_dma_chan5 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403a>; }; &lpd_dma_chan6 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403b>; }; &lpd_dma_chan7 { clocks = <&versal_clk 81>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822403c>; }; &qspi { clocks = <&versal_clk 57>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402b>; }; &ospi { clocks = <&versal_clk 58>, <&versal_clk 82>; }; &rtc { power-domains = <&versal_firmware 0x18224034>; }; &serial0 { clocks = <&versal_clk 92>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224021>; }; &serial1 { clocks = <&versal_clk 93>, <&versal_clk 82>; power-domains = <&versal_firmware 0x18224022>; }; &sdhci0 { clocks = <&versal_clk 59>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402e>; }; &sdhci1 { clocks = <&versal_clk 60>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822402f>; }; &spi0 { clocks = <&versal_clk 94>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401b>; }; &spi1 { clocks = <&versal_clk 95>, <&versal_clk 82>; power-domains = <&versal_firmware 0x1822401c>; }; &usb0 { clocks = <&versal_clk 91>, <&versal_clk 104>; power-domains = <&versal_firmware 0x18224018>; }; &watchdog { clocks = <&versal_clk 82>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal/versal.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { compatible = "xlnx,versal"; #address-cells = <2>; #size-cells = <2>; model = "Xilinx Versal"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus: cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a72"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a72"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <1>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <1 7 0x304>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-parent = <&gic>; bootph-all; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; reg = <0 0xf9000000 0 0x80000>, /* GICD */ <0 0xf9080000 0 0x80000>; /* GICR */ interrupt-controller; interrupts = <1 9 4>; gic_its: msi-controller@f9020000 { compatible = "arm,gic-v3-its"; status = "disabled"; msi-controller; #msi-cells = <1>; reg = <0 0xf9020000 0 0x20000>; }; }; can0: can@ff060000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff060000 0 0x6000>; interrupts = <0 20 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; can1: can@ff070000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xff070000 0 0x6000>; interrupts = <0 21 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <0x40>; tx-mailbox-count = <0x20>; }; cci: cci@fd000000 { compatible = "arm,cci-500"; status = "disabled"; reg = <0 0xfd000000 0 0x10000>; ranges = <0 0 0xfd000000 0xa0000>; #address-cells = <1>; #size-cells = <1>; cci_pmu: pmu@10000 { compatible = "arm,cci-500-pmu,r0"; reg = <0x10000 0x90000>; interrupts = <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>, <0 106 4>; }; }; lpd_dma_chan0: dma-controller@ffa80000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa80000 0 0x1000>; interrupts = <0 60 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x210>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan1: dma-controller@ffa90000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffa90000 0 0x1000>; interrupts = <0 61 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x212>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan2: dma-controller@ffaa0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaa0000 0 0x1000>; interrupts = <0 62 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x214>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan3: dma-controller@ffab0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffab0000 0 0x1000>; interrupts = <0 63 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x216>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan4: dma-controller@ffac0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffac0000 0 0x1000>; interrupts = <0 64 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x218>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan5: dma-controller@ffad0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffad0000 0 0x1000>; interrupts = <0 65 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21a>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan6: dma-controller@ffae0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffae0000 0 0x1000>; interrupts = <0 66 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21c>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; lpd_dma_chan7: dma-controller@ffaf0000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xffaf0000 0 0x1000>; interrupts = <0 67 4>; clock-names = "clk_main", "clk_apb"; /* iommus = <&smmu 0x21e>; */ #dma-cells = <1>; xlnx,bus-width = <64>; /* dma-coherent; */ }; gem0: ethernet@ff0c0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0c0000 0 0x1000>; interrupts = <0 56 4>, <0 56 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x234>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0d0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xff0d0000 0 0x1000>; interrupts = <0 58 4>, <0 58 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; /* iommus = <&smmu 0x235>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@ff0b0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xff0b0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff020000 0 0x1000>; interrupts = <0 14 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xff030000 0 0x1000>; interrupts = <0 15 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; i2c2: i2c@f1000000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; reg = <0 0xf1000000 0 0x1000>; interrupts = <0 123 4>; clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; }; mc0: memory-controller@f6150000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc1: memory-controller@f62c0000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf62c0000 0x0 0x2000>, <0x0 0xf6210000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc2: memory-controller@f6430000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf6430000 0x0 0x2000>, <0x0 0xf6380000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; mc3: memory-controller@f65a0000 { compatible = "xlnx,versal-ddrmc"; status = "disabled"; reg = <0x0 0xf65a0000 0x0 0x2000>, <0x0 0xf64f0000 0x0 0x20000>; reg-names = "base", "noc"; interrupts = <0 147 4>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupts = <0 10 4>; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupt-names = "alarm", "sec"; interrupts = <0 142 4>, <0 143 4>; calibration = <0x7FFF>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 126 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; /* iommus = <&smmu 0x242>; */ /* dma-coherent; */ }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 128 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; /* iommus = <&smmu 0x243>; */ /* dma-coherent; */ }; serial0: serial@ff000000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff000000 0 0x1000>; interrupts = <0 18 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; bootph-all; }; serial1: serial@ff010000 { compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xff010000 0 0x1000>; interrupts = <0 19 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; bootph-all; }; smmu: iommu@fd800000 { compatible = "arm,mmu-500"; status = "disabled"; reg = <0 0xfd800000 0 0x40000>; stream-match-mask = <0x7c00>; #iommu-cells = <1>; #global-interrupts = <1>; interrupts = <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>, <0 107 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cadence,qspi", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>; interrupts = <0 124 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xC0000000>; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 125 4>; clock-names = "ref_clk", "pclk"; /* iommus = <&smmu 0x244>; */ /* dma-coherent; */ #address-cells = <1>; #size-cells = <0>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff040000 0 0x1000>; interrupts = <0 16 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; reg = <0 0xff050000 0 0x1000>; interrupts = <0 17 4>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 144 4>; xlnx,numchannels = /bits/8 <0>; }; sysmon1: sysmon@109270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x09270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon2: sysmon@111270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x11270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; sysmon3: sysmon@119270000 { compatible = "xlnx,versal-sysmon"; #address-cells = <2>; #size-cells = <2>; status = "disabled"; reg = <0x1 0x19270000 0x0 0x4000>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@ff0e0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff0f0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 40 4>, <0 41 4>, <0 42 4>; reg = <0x0 0xff0f0000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff100000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; reg = <0x0 0xff100000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; usb0: usb@ff9d0000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xff9d0000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xfe200000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 0x16 4>, <0 0x16 4>, <0 0x1a 4>, <0x0 0x4a 0x4>; /* iommus = <&smmu 0x230>; */ snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; /* dma-coherent; */ }; }; cpm_pciea: pci@fca10000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm-host-1.00"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_0 0>, <0 0 0 2 &pcie_intc_0 1>, <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x00000000 0xe0000000 0x0 0xe0000000 0x00000000 0x10000000>, <0x43000000 0x00000080 0x00000000 0x00000080 0x00000000 0x00000000 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, <0x6 0x00000000 0x0 0x1000000>; reg-names = "cpm_slcr", "cfg"; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller ; }; }; cpm5_pcie: pcie@fcdd0000 { device_type = "pci"; #address-cells = <3>; #interrupt-cells = <1>; #size-cells = <2>; compatible = "xlnx,versal-cpm5-host"; status = "disabled"; interrupt-map = <0 0 0 1 &pcie_intc_1 0>, <0 0 0 2 &pcie_intc_1 1>, <0 0 0 3 &pcie_intc_1 2>, <0 0 0 4 &pcie_intc_1 3>; interrupt-map-mask = <0 0 0 7>; interrupt-names = "misc"; interrupts = <0 72 4>; interrupt-parent = <&gic>; bus-range = <0x00 0xff>; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &gic_its 0x0 0x10000>; reg = <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, <0x00 0xfce20000 0x00 0x1000000>; reg-names = "cpm_slcr", "cfg", "cpm_csr"; pcie_intc_1: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; }; }; watchdog: watchdog@fd4d0000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xfd4d0000 0 0x10000>; timeout-sec = <30>; }; watchdog1: watchdog@ff120000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xff120000 0 0x10000>; timeout-sec = <30>; }; xilsem_edac: edac@f2014050 { compatible = "xlnx,versal-xilsem-edac"; status = "disabled"; reg = <0x0 0xf2014050 0x0 0xc4>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal with PM * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { ref_clk: ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; can0_clk: can0-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN0_REF_2X>; clock-div = <2>; clock-mult = <1>; }; can1_clk: can1-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&versal_net_clk CAN1_REF_2X>; clock-div = <2>; clock-mult = <1>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; #power-domain-cells = <1>; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; versal_net_power: zynqmp-power { /* untested */ compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_sec_cfg: versal-sec-cfg { /* untested */ compatible = "xlnx,versal-sec-cfg"; #address-cells = <1>; #size-cells = <1>; bbram_zeroize: bbram-zeroize@4 { reg = <0x04 0x4>; }; bbram_key: bbram-key@10 { reg = <0x10 0x20>; }; bbram_usr: bbram-usr@30 { reg = <0x30 0x4>; }; bbram_lock: bbram-lock@48 { reg = <0x48 0x4>; }; user_key0: user-key@110 { reg = <0x110 0x20>; }; user_key1: user-key@130 { reg = <0x130 0x20>; }; user_key2: user-key@150 { reg = <0x150 0x20>; }; user_key3: user-key@170 { reg = <0x170 0x20>; }; user_key4: user-key@190 { reg = <0x190 0x20>; }; user_key5: user-key@1b0 { reg = <0x1b0 0x20>; }; user_key6: user-key@1d0 { reg = <0x1d0 0x20>; }; user_key7: user-key@1f0 { reg = <0x1f0 0x20>; }; }; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; }; &cpu0 { clocks = <&versal_net_clk ACPU_0>; }; &cpu100 { clocks = <&versal_net_clk ACPU_0>; }; &cpu200 { clocks = <&versal_net_clk ACPU_0>; }; &cpu300 { clocks = <&versal_net_clk ACPU_0>; }; &cpu10000 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10100 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10200 { clocks = <&versal_net_clk ACPU_1>; }; &cpu10300 { clocks = <&versal_net_clk ACPU_1>; }; &cpu20000 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20100 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20200 { clocks = <&versal_net_clk ACPU_2>; }; &cpu20300 { clocks = <&versal_net_clk ACPU_2>; }; &cpu30000 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30100 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30200 { clocks = <&versal_net_clk ACPU_3>; }; &cpu30300 { clocks = <&versal_net_clk ACPU_3>; }; &can0 { clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &adma0 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; &adma1 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; &adma2 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; &adma3 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; &adma4 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; &adma5 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; &adma6 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; &adma7 { clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; }; &ospi { clocks = <&versal_net_clk OSPI_REF>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &rtc { power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; }; &sdhci0 { clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; &sdhci1 { clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, <&versal_net_clk SD_DLL_REF>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; &ttc1 { clocks = <&versal_net_clk TTC1>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_1>; }; &ttc2 { clocks = <&versal_net_clk TTC2>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_2>; }; &ttc3 { clocks = <&versal_net_clk TTC3>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; &lpd_wwdt0 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; &lpd_wwdt1 { clocks = <&versal_net_clk LPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET fixed clock * * (C) Copyright 2022-2024, Xilinx, Inc. * * Michal Simek */ #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { clk60: clk60 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <60000000>; }; clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk150: clk150 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <150000000>; }; clk160: clk160 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <160000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk450: clk450 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <450000000>; }; clk1200: clk1200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1200000000>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; }; }; &adma0 { clocks = <&clk450>, <&clk450>; }; &adma1 { clocks = <&clk450>, <&clk450>; }; &adma2 { clocks = <&clk450>, <&clk450>; }; &adma3 { clocks = <&clk450>, <&clk450>; }; &adma4 { clocks = <&clk450>, <&clk450>; }; &adma5 { clocks = <&clk450>, <&clk450>; }; &adma6 { clocks = <&clk450>, <&clk450>; }; &adma7 { clocks = <&clk450>, <&clk450>; }; &can0 { clocks = <&clk160>, <&clk160>; }; &can1 { clocks = <&clk160>, <&clk160>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; }; &gpio0 { clocks = <&clk100>; }; &gpio1 { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &i3c0 { clocks = <&clk100>; }; &i3c1 { clocks = <&clk100>; }; &ospi { clocks = <&clk200>; resets = <&versal_net_reset VERSAL_RST_OSPI>; }; &qspi { clocks = <&clk300>, <&clk300>; }; &rtc { /* Nothing */ }; &sdhci0 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &sdhci1 { clocks = <&clk200>, <&clk200>, <&clk1200>; }; &serial0 { clocks = <&clk100>, <&clk100>; clock = <1000000>; }; &serial1 { clocks = <&clk100>, <&clk100>; clock = <100000000>; }; &spi0 { clocks = <&clk200>, <&clk200>; }; &spi1 { clocks = <&clk200>, <&clk200>; }; &ttc0 { clocks = <&clk150>; }; &usb0 { clocks = <&clk60>, <&clk60>; }; &dwc3_0 { /* Nothing */ }; &usb1 { clocks = <&clk60>, <&clk60>; }; &dwc3_1 { /* Nothing */ }; &wwdt0 { clocks = <&clk150>; }; &wwdt1 { clocks = <&clk150>; }; &wwdt2 { clocks = <&clk150>; }; &wwdt3 { clocks = <&clk150>; }; &lpd_wwdt0 { clocks = <&clk150>; }; &lpd_wwdt1 { clocks = <&clk150>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net-ipp-rev1.9.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * (C) Copyright 2021-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/clock/xlnx-versal-net-clk.h" #include "include/dt-bindings/power/xlnx-versal-net-power.h" #include "include/dt-bindings/reset/xlnx-versal-net-resets.h" / { compatible = "xlnx,versal-net-ipp-1.9", "xlnx,versal-net-spp-5.0", "xlnx,versal-net-spp", "xlnx,versal-net"; model = "Xilinx Versal NET SPP 5.0/IPP 1.9"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; }; }; memory: memory@0 { reg = <0 0 0 0x80000000>; device_type = "memory"; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; chosen { bootargs = "earlycon=pl011,mmio32,0xf1920000 console=ttyAMA0,115200 spi-cadence-quadspi.read_timeout_ms=30 dw-i3c-master.scl_timing_quirk_spp=1"; stdout-path = "serial0:115200"; }; ref_clk: ref_clk { compatible = "fixed-clock"; bootph-all; #clock-cells = <0>; clock-frequency = <33333333>; }; firmware { versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; interrupt-parent = <&gic>; bootph-all; method = "smc"; #power-domain-cells = <0x01>; versal_net_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; clocks = <&ref_clk>, <&ref_clk>; clock-names = "ref_clk", "pl_alt_ref_clk"; }; zynqmp_power: zynqmp-power { compatible = "xlnx,zynqmp-power"; interrupts = <0 57 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; versal_net_reset: reset-controller { compatible = "xlnx,versal-net-reset"; #reset-cells = <1>; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; zynqmp-ipi { compatible = "xlnx,zynqmp-ipi-mailbox"; interrupts = <0 57 4>; xlnx,ipi-id = <2>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@eb3f0440 { reg = <0 0xeb3f0440 0 0x20>, <0 0xeb3f0460 0 0x20>, <0 0xeb3f0280 0 0x20>, <0 0xeb3f02a0 0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <1>; }; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN0_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; clocks = <&versal_net_clk CAN1_REF_2X>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_0>; mdio0: mdio { #address-cells = <1>; #size-cells = <0>; phy1: ethernet-phy@1 { #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; max-speed = <100>; ti,rx-internal-delay = <11>; ti,tx-internal-delay = <10>; ti,fifo-depth = <1>; ti,dp83867-rxctrl-strap-quirk; }; }; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,versal-gem", "cdns,gem"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; phy-handle = <&phy2>; phy-mode = "rmii"; clocks = <&versal_net_clk LPD_LSBUS>, <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; power-domains = <&versal_net_firmware PM_DEV_GEM_1>; mdio1: mdio { #address-cells = <1>; #size-cells = <0>; phy2: ethernet-phy@2 { compatible = "ethernet-phy-id0007.0762"; /* Vitesse VSC8540 */ reg = <2>; max-speed = <100>; }; }; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 13 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 122 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; clocks = <&versal_net_clk PMC_LSBUS_REF>; power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C0_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk I3C1_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; i3c: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 21 4>; clocks = <&versal_net_clk I2C_REF>; power-domains = <&versal_net_firmware PM_DEV_I2C_PMC>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; cdns,trigger-address = <0xc0000000>; clocks = <&versal_net_clk OSPI_REF>; #address-cells = <1>; #size-cells = <0>; power-domains = <&versal_net_firmware PM_DEV_OSPI>; reset-gpios = <&gpio1 0xc GPIO_ACTIVE_HIGH>; mt35xu02g: flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>; #address-cells = <1>; #size-cells = <1>; cdns,read-delay = <0>; cdns,tshsl-ns = <0>; cdns,tsd2d-ns = <0>; cdns,tchsh-ns = <1>; cdns,tslch-ns = <1>; spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <20000000>; broken-flash-reset; no-wp; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "ospi-flash0"; reg = <0 0x200000>; }; partition@1 { label = "ospi-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; reg = <0 0xf1030000 0 0x1000>; interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; num-cs = <2>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_QSPI>; #address-cells = <1>; #size-cells = <0>; flash@0 { compatible = "micron,m25p80", "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ #address-cells = <1>; #size-cells = <1>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; spi-max-frequency = <10000000>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "qspi0-flash0"; reg = <0 0x200000>; }; partition@1 { label = "qspi0-flash1"; reg = <0x200000 0x7E00000>; }; }; }; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb"; no-1-8-v; clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_0>; clock = <1000000>; current-speed = <115200>; skip-init; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_UART_1>; clock = <1000000>; current-speed = <115200>; skip-init; }; smmu: smmu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_0>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi0-flash0"; reg = <0 0x80000>; }; }; }; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; interrupt-parent = <&gic>; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_SPI_1>; num-cs = <1>; flash@0 { compatible = "m25p80"; spi-max-frequency = <5000000>; reg = <0>; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { label = "spi1-flash0"; reg = <0 0x80000>; }; }; }; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; interrupt-parent = <&gic>; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; clocks = <&versal_net_clk TTC0>, <&versal_net_clk LPD_LSBUS>; power-domains = <&versal_net_firmware PM_DEV_TTC_0>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; /* clocks = <&clk60>, <&clk60>; */ clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_0>; resets = <&versal_net_reset VERSAL_RST_USB_0>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; power-domains = <&versal_net_firmware PM_DEV_USB_1>; resets = <&versal_net_reset VERSAL_RST_USB_1>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "dwc_usb3","otg","usb-wakeup"; interrupts = <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; clocks = <&versal_net_clk FPD_WWDT>; power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/versal-net/versal-net.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0 /* * dts file for Xilinx Versal NET * * Copyright (C) 2022, Xilinx, Inc. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. * * Michal Simek */ / { compatible = "xlnx,versal-net"; model = "Xilinx Versal NET"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu100>; }; core2 { cpu = <&cpu200>; }; core3 { cpu = <&cpu300>; }; }; cluster1 { core0 { cpu = <&cpu10000>; }; core1 { cpu = <&cpu10100>; }; core2 { cpu = <&cpu10200>; }; core3 { cpu = <&cpu10300>; }; }; cluster2 { core0 { cpu = <&cpu20000>; }; core1 { cpu = <&cpu20100>; }; core2 { cpu = <&cpu20200>; }; core3 { cpu = <&cpu20300>; }; }; cluster3 { core0 { cpu = <&cpu30000>; }; core1 { cpu = <&cpu30100>; }; core2 { cpu = <&cpu30200>; }; core3 { cpu = <&cpu30300>; }; }; }; cpu0: cpu@0 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu100: cpu@100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu200: cpu@200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu300: cpu@300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10000: cpu@10000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10100: cpu@10100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10200: cpu@10200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu10300: cpu@10300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x10300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20000: cpu@20000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20100: cpu@20100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20200: cpu@20200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu20300: cpu@20300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x20300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30000: cpu@30000 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30000>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30100: cpu@30100 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30100>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30200: cpu@30200 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30200>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu30300: cpu@30300 { compatible = "arm,cortex-a78"; device_type = "cpu"; enable-method = "psci"; reg = <0x30300>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-1066000000 { opp-hz = /bits/ 64 <1066000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1866000000 { opp-hz = /bits/ 64 <1866000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-1999000000 { opp-hz = /bits/ 64 <1999000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2050000000 { opp-hz = /bits/ 64 <2050000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2100000000 { opp-hz = /bits/ 64 <2100000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2200000000 { opp-hz = /bits/ 64 <2200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; aliases { serial0 = &serial0; serial1 = &serial1; serial2 = &dcc; mmc0 = &sdhci0; mmc1 = &sdhci1; i2c0 = &i2c0; i2c1 = &i2c1; rtc = &rtc; usb0 = &usb0; usb1 = &usb1; spi0 = &ospi; spi1 = &qspi; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; firmware { psci { compatible = "arm,psci-1.0"; method = "smc"; }; }; fpga: fpga { compatible = "fpga-region"; fpga-mgr = <&versal_fpga>; #address-cells = <2>; #size-cells = <2>; }; timer: timer { compatible = "arm,armv8-timer"; interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; /* FIXME 3rd cell */ }; versal_fpga: versal-fpga { compatible = "xlnx,versal-fpga"; }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; adma0: dma-controller@ebd00000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd00000 0 0x1000>; interrupts = <0 72 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma1: dma-controller@ebd10000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd10000 0 0x1000>; interrupts = <0 73 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma2: dma-controller@ebd20000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd20000 0 0x1000>; interrupts = <0 74 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma3: dma-controller@ebd30000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd30000 0 0x1000>; interrupts = <0 75 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma4: dma-controller@ebd40000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd40000 0 0x1000>; interrupts = <0 76 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma5: dma-controller@ebd50000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd50000 0 0x1000>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma6: dma-controller@ebd60000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd60000 0 0x1000>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; adma7: dma-controller@ebd70000 { compatible = "xlnx,zynqmp-dma-1.0"; status = "disabled"; reg = <0 0xebd70000 0 0x1000>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; }; can0: can@f1980000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1980000 0 0x6000>; interrupts = <0 27 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; can1: can@f1990000 { compatible = "xlnx,canfd-2.0"; status = "disabled"; reg = <0 0xf1990000 0 0x6000>; interrupts = <0 28 4>; clock-names = "can_clk", "s_axi_aclk"; rx-fifo-depth = <64>; tx-mailbox-count = <32>; }; gem0: ethernet@f19e0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19e0000 0 0x1000>; interrupts = <0 39 4>, <0 39 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gem1: ethernet@f19f0000 { compatible = "xlnx,versal-gem", "cdns,gem"; status = "disabled"; reg = <0 0xf19f0000 0 0x1000>; interrupts = <0 41 4>, <0 41 4>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; }; gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; reg = <0 0xe2000000 0 0x10000>, <0 0xe2060000 0 0x200000>; interrupt-controller; interrupts = <1 9 4>; #address-cells = <2>; #size-cells = <2>; ranges; its: msi-controller@e2040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; reg = <0 0xe2040000 0 0x20000>; }; }; gpio0: gpio@f19d0000 { compatible = "xlnx,versal-gpio-1.0"; status = "disabled"; reg = <0 0xf19d0000 0 0x1000>; interrupts = <0 20 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; gpio1: gpio@f1020000 { compatible = "xlnx,pmc-gpio-1.0"; status = "disabled"; reg = <0 0xf1020000 0 0x1000>; interrupts = <0 180 4>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; }; i2c0: i2c@f1940000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1940000 0 0x1000>; interrupts = <0 21 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@f1950000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; reg = <0 0xf1950000 0 0x1000>; interrupts = <0 22 4>; clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; i3c0: i3c-master@f1948000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1948000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 21 4>; }; i3c1: i3c-master@f1958000 { compatible = "snps,dw-i3c-master-1.00a"; status = "disabled"; reg = <0 0xf1958000 0 0x1000>; #address-cells = <3>; #size-cells = <0>; interrupts = <0 22 4>; }; ospi: spi@f1010000 { compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; status = "disabled"; reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>; interrupts = <0 182 4>; cdns,fifo-depth = <256>; cdns,fifo-width = <4>; cdns,is-dma = <1>; /* u-boot specific */ /* cdns,is-stig-pgm = <1>; - unused - checking with Sai */ cdns,trigger-address = <0xc0000000>; }; qspi: spi@f1030000 { compatible = "xlnx,versal-qspi-1.0"; status = "disabled"; reg = <0 0xf1030000 0 0x1000>; /* missing one more reg range - checking with Sai */ interrupts = <0 183 4>; clock-names = "ref_clk", "pclk"; }; rtc: rtc@f12a0000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0 0xf12a0000 0 0x100>; interrupts = <0 200 4>, <0 201 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sdhci0: mmc@f1040000 { compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; reg = <0 0xf1040000 0 0x10000>; interrupts = <0 184 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; sdhci1: mmc@f1050000 { compatible = "xlnx,versal-net-emmc"; status = "disabled"; reg = <0 0xf1050000 0 0x10000>; interrupts = <0 186 4>; clock-names = "clk_xin", "clk_ahb", "gate"; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; serial0: serial@f1920000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1920000 0 0x1000>; interrupts = <0 25 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; serial1: serial@f1930000 { bootph-all; compatible = "arm,pl011", "arm,primecell"; status = "disabled"; reg = <0 0xf1930000 0 0x1000>; interrupts = <0 26 4>; reg-io-width = <4>; clock-names = "uartclk", "apb_pclk"; current-speed = <115200>; }; smmu: iommu@ec000000 { compatible = "arm,smmu-v3"; status = "disabled"; reg = <0 0xec000000 0 0x40000>; #iommu-cells = <1>; interrupt-names = "combined"; interrupts = <0 169 4>; dma-coherent; }; spi0: spi@f1960000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; spi1: spi@f1970000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; clock-names = "ref_clk", "pclk"; }; sysmon0: sysmon@f1270000 { compatible = "xlnx,versal-sysmon"; status = "disabled"; reg = <0x0 0xf1270000 0x0 0x4000>; interrupts = <0 202 4>; xlnx,numchannels = /bits/8 <0>; }; ttc0: timer@f1dc0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 43 4>, <0 44 4>, <0 45 4>; timer-width = <32>; reg = <0x0 0xf1dc0000 0x0 0x1000>; }; ttc1: timer@f1dd0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 46 4>, <0 47 4>, <0 48 4>; timer-width = <32>; reg = <0x0 0xf1dd0000 0x0 0x1000>; }; ttc2: timer@f1de0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 49 4>, <0 50 4>, <0 51 4>; timer-width = <32>; reg = <0x0 0xf1de0000 0x0 0x1000>; }; ttc3: timer@f1df0000 { compatible = "cdns,ttc"; status = "disabled"; interrupts = <0 52 4>, <0 53 4>, <0 54 4>; timer-width = <32>; reg = <0x0 0xf1df0000 0x0 0x1000>; }; usb0: usb@f1e00000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0 0xf1e00000 0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; #address-cells = <2>; #size-cells = <2>; dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xf1b00000 0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "peripheral"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /*phy-names = "usb3-phy";- checking with Pyiush */ }; }; usb1: usb@f1e10000 { compatible = "xlnx,versal-dwc3"; status = "disabled"; reg = <0x0 0xf1e10000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; ranges; interrupt-names = "usb-wakeup"; interrupts = <0 99 4>; #address-cells = <2>; #size-cells = <2>; dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xf1c00000 0x0 0x10000>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; snps,quirk-frame-length-adjustment = <0x20>; dr_mode = "host"; maximum-speed = "high-speed"; snps,usb3_lpm_capable; clock-names = "ref"; /* phy-names = "usb3-phy"; - checking with Pyiush */ }; }; wwdt0: watchdog@ecc10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecc10000 0 0x10000>; timeout-sec = <30>; }; wwdt1: watchdog@ecd10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecd10000 0 0x10000>; timeout-sec = <30>; }; wwdt2: watchdog@ece10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xece10000 0 0x10000>; timeout-sec = <30>; }; wwdt3: watchdog@ecf10000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xecf10000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt0: watchdog@ea420000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea420000 0 0x10000>; timeout-sec = <30>; }; lpd_wwdt1: watchdog@ea430000 { compatible = "xlnx,versal-wwdt"; status = "disabled"; reg = <0 0xea430000 0 0x10000>; timeout-sec = <30>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/zynq/skeleton.dtsi ================================================ /* * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. */ / { #address-cells = <1>; #size-cells = <1>; chosen { }; aliases { }; memory { device_type = "memory"; reg = <0 0>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/zynq/zynq-7000.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2011-2022 Xilinx, Inc. * Copyright (C) 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ / { #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-7000"; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x3000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; operating-points = < /* kHz uV */ 666667 1000000 333334 1000000 >; }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; }; }; fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; #size-cells = <1>; ranges; }; pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; interrupt-parent = <&intc>; reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; }; regulator_vccpint: fixedregulator { compatible = "regulator-fixed"; regulator-name = "VCCPINT"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; }; replicator { compatible = "arm,coresight-static-replicator"; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&etb_in_port>; }; }; }; in-ports { /* replicator input port */ port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port>; }; }; }; }; amba: axi { bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&intc>; ranges; adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; interrupt-parent = <&intc>; clocks = <&clkc 12>; }; can0: can@e0008000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 19>, <&clkc 36>; clock-names = "can_clk", "pclk"; reg = <0xe0008000 0x1000>; interrupts = <0 28 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@e0009000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clocks = <&clkc 20>, <&clkc 37>; clock-names = "can_clk", "pclk"; reg = <0xe0009000 0x1000>; interrupts = <0 51 4>; interrupt-parent = <&intc>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; gpio0: gpio@e000a000 { compatible = "xlnx,zynq-gpio-1.0"; #gpio-cells = <2>; clocks = <&clkc 42>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupts = <0 20 4>; reg = <0xe000a000 0x1000>; }; i2c0: i2c@e0004000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 38>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 25 4>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@e0005000 { compatible = "cdns,i2c-r1p10"; status = "disabled"; clocks = <&clkc 39>; clock-frequency = <400000>; interrupt-parent = <&intc>; interrupts = <0 48 4>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; }; intc: interrupt-controller@f8f01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0xF8F01000 0x1000>, <0xF8F00100 0x100>; }; L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; interrupts = <0 2 4>; arm,data-latency = <3 2 2>; arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; }; mc: memory-controller@f8006000 { compatible = "xlnx,zynq-ddrc-a05"; reg = <0xf8006000 0x1000>; }; ocm: sram@fffc0000 { compatible = "mmio-sram"; reg = <0xfffc0000 0x10000>; }; uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 23>, <&clkc 40>; clock-names = "uart_clk", "pclk"; reg = <0xE0000000 0x1000>; interrupts = <0 27 4>; }; uart1: serial@e0001000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; clocks = <&clkc 24>, <&clkc 41>; clock-names = "uart_clk", "pclk"; reg = <0xE0001000 0x1000>; interrupts = <0 50 4>; }; spi0: spi@e0006000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0006000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 26 4>; clocks = <&clkc 25>, <&clkc 34>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@e0007000 { compatible = "xlnx,zynq-spi-r1p6"; reg = <0xe0007000 0x1000>; status = "disabled"; interrupt-parent = <&intc>; interrupts = <0 49 4>; clocks = <&clkc 26>, <&clkc 35>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; qspi: spi@e000d000 { compatible = "xlnx,zynq-qspi-1.0"; reg = <0xe000d000 0x1000>; interrupt-parent = <&intc>; interrupts = <0 19 4>; clocks = <&clkc 10>, <&clkc 43>; clock-names = "ref_clk", "pclk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gem0: ethernet@e000b000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; smcc: memory-controller@e000e000 { compatible = "arm,pl353-smc-r2p1", "arm,primecell"; reg = <0xe000e000 0x0001000>; status = "disabled"; clock-names = "memclk", "apb_pclk"; clocks = <&clkc 11>, <&clkc 44>; ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; interrupt-parent = <&intc>; interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; #address-cells = <0x1>; #size-cells = <0x0>; }; nor0: flash@1,0 { status = "disabled"; compatible = "cfi-flash"; reg = <1 0 0x2000000>; #address-cells = <1>; #size-cells = <1>; }; }; sdhci0: mmc@e0100000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 21>, <&clkc 32>; interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; }; sdhci1: mmc@e0101000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; clock-names = "clk_xin", "clk_ahb"; clocks = <&clkc 22>, <&clkc 33>; interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; }; slcr: slcr@f8000000 { bootph-all; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { bootph-all; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb"; reg = <0x100 0x100>; }; rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x48>; #reset-cells = <1>; syscon = <&slcr>; }; pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>; syscon = <&slcr>; }; }; dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; /* * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", * "dma4", "dma5", "dma6", "dma7"; */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>; #dma-cells = <1>; clocks = <&clkc 27>; clock-names = "apb_pclk"; }; devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; interrupt-parent = <&intc>; interrupts = <0 8 4>; clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; }; efuse: efuse@f800d000 { compatible = "xlnx,zynq-efuse"; reg = <0xf800d000 0x20>; }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xf8f00200 0x20>; interrupts = <1 11 0x301>; interrupt-parent = <&intc>; clocks = <&clkc 4>; }; ttc0: timer@f8001000 { interrupt-parent = <&intc>; interrupts = <0 10 4>, <0 11 4>, <0 12 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8001000 0x1000>; }; ttc1: timer@f8002000 { interrupt-parent = <&intc>; interrupts = <0 37 4>, <0 38 4>, <0 39 4>; compatible = "cdns,ttc"; clocks = <&clkc 6>; reg = <0xF8002000 0x1000>; }; scutimer: timer@f8f00600 { bootph-all; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; }; usb0: usb@e0002000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 28>; interrupt-parent = <&intc>; interrupts = <0 21 4>; reg = <0xe0002000 0x1000>; phy_type = "ulpi"; }; usb1: usb@e0003000 { compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; status = "disabled"; clocks = <&clkc 29>; interrupt-parent = <&intc>; interrupts = <0 44 4>; reg = <0xe0003000 0x1000>; phy_type = "ulpi"; }; watchdog0: watchdog@f8005000 { clocks = <&clkc 45>; compatible = "cdns,wdt-r1p2"; interrupt-parent = <&intc>; interrupts = <0 9 1>; reg = <0xf8005000 0x1000>; timeout-sec = <10>; }; etb@f8801000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0xf8801000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { etb_in_port: endpoint { remote-endpoint = <&replicator_out_port1>; }; }; }; }; tpiu@f8803000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0xf8803000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; in-ports { port { tpiu_in_port: endpoint { remote-endpoint = <&replicator_out_port0>; }; }; }; }; funnel@f8804000 { compatible = "arm,coresight-static-funnel", "arm,primecell"; reg = <0xf8804000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; /* funnel output ports */ out-ports { port { funnel_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; /* funnel input ports */ port@0 { reg = <0>; funnel0_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel0_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel0_in_port2: endpoint { }; }; /* The other input ports are not connect to anything */ }; }; ptm@f889c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889c000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu0>; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel0_in_port0>; }; }; }; }; ptm@f889d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0xf889d000 0x1000>; clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; cpu = <&cpu1>; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel0_in_port1>; }; }; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/zynqmp/zynqmp-clk-ccf.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/clock/xlnx-zynqmp-clk.h" / { pss_ref_clk: pss_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; }; video_clk: video_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; pss_alt_ref_clk: pss_alt_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; gt_crx_ref_clk: gt_crx_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; }; aux_ref_clk: aux_ref_clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; }; }; &zynqmp_firmware { zynqmp_clk: clock-controller { bootph-all; #clock-cells = <1>; compatible = "xlnx,zynqmp-clk"; clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; }; }; &can0 { clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &can1 { clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &cpu0 { clocks = <&zynqmp_clk ACPU>; }; &fpd_dma_chan1 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan2 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan3 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan4 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan5 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan6 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan7 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &fpd_dma_chan8 { clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gpu { clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; }; &lpd_dma_chan1 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan2 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan3 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan4 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan5 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan6 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan7 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &lpd_dma_chan8 { clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; }; &nand0 { clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>; }; &gem0 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { clocks = <&zynqmp_clk LPD_LSBUS>; }; &i2c0 { clocks = <&zynqmp_clk I2C0_REF>; }; &i2c1 { clocks = <&zynqmp_clk I2C1_REF>; }; &perf_monitor_ocm { clocks = <&zynqmp_clk LPD_LSBUS>; }; &perf_monitor_ddr { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_cci { clocks = <&zynqmp_clk TOPSW_LSBUS>; }; &perf_monitor_lpd { clocks = <&zynqmp_clk LPD_LSBUS>; }; &pcie { clocks = <&zynqmp_clk PCIE_REF>; }; &qspi { clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; }; &sata { clocks = <&zynqmp_clk SATA_REF>; }; &sdhci0 { clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO0_REF>; }; &sdhci1 { clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; assigned-clocks = <&zynqmp_clk SDIO1_REF>; }; &spi0 { clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &spi1 { clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &ttc0 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc1 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc2 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &ttc3 { clocks = <&zynqmp_clk LPD_LSBUS>; }; &uart0 { clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>; }; &uart1 { clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; &usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_0 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; &dwc3_1 { clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { clocks = <&zynqmp_clk WDT>; }; &lpd_watchdog { clocks = <&zynqmp_clk LPD_WDT>; }; &xilinx_ams { clocks = <&zynqmp_clk AMS_REF>; }; &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; assigned-clocks = <&zynqmp_clk DP_STC_REF>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; &zynqmp_dp_snd_codec0 { clocks = <&zynqmp_clk DP_AUDIO_REF>; }; ================================================ FILE: device_tree/data/kernel_dtsi/2024.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ #include "include/dt-bindings/dma/xlnx-zynqmp-dpdma.h" #include "include/dt-bindings/gpio/gpio.h" #include "include/dt-bindings/power/xlnx-zynqmp-power.h" #include "include/dt-bindings/reset/xlnx-zynqmp-resets.h" / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; options { u-boot { compatible = "u-boot,config"; bootscr-address = /bits/ 64 <0x20000000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; next-level-cache = <&L2>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; zynqmp_ipi: zynqmp-ipi { bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; interrupts = <0 35 4>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; ranges; ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>, <0x0 0xff990e80 0x0 0x20>, <0x0 0xff990ea0 0x0 0x20>; reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region"; #mbox-cells = <1>; xlnx,ipi-id = <4>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; bootph-all; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; firmware { zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; bootph-all; method = "smc"; #power-domain-cells = <0x1>; zynqmp_power: zynqmp-power { bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; interrupts = <0 35 4>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; /* efuse access */ efuse_dna: efuse-dna@c { reg = <0xc 0xc>; }; efuse_usr0: efuse-usr0@20 { reg = <0x20 0x4>; }; efuse_usr1: efuse-usr1@24 { reg = <0x24 0x4>; }; efuse_usr2: efuse-usr2@28 { reg = <0x28 0x4>; }; efuse_usr3: efuse-usr3@2c { reg = <0x2c 0x4>; }; efuse_usr4: efuse-usr4@30 { reg = <0x30 0x4>; }; efuse_usr5: efuse-usr5@34 { reg = <0x34 0x4>; }; efuse_usr6: efuse-usr6@38 { reg = <0x38 0x4>; }; efuse_usr7: efuse-usr7@3c { reg = <0x3c 0x4>; }; efuse_miscusr: efuse-miscusr@40 { reg = <0x40 0x4>; }; efuse_chash: efuse-chash@50 { reg = <0x50 0x4>; }; efuse_pufmisc: efuse-pufmisc@54 { reg = <0x54 0x4>; }; efuse_sec: efuse-sec@58 { reg = <0x58 0x4>; }; efuse_spkid: efuse-spkid@5c { reg = <0x5c 0x4>; }; efuse_aeskey: efuse-aeskey@60 { reg = <0x60 0x20>; }; efuse_ppk0hash: efuse-ppk0hash@a0 { reg = <0xa0 0x30>; }; efuse_ppk1hash: efuse-ppk1hash@d0 { reg = <0xd0 0x30>; }; efuse_pufuser: efuse-pufuser@100 { reg = <0x100 0x7F>; }; }; }; zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; zynqmp_reset: reset-controller { compatible = "xlnx,zynqmp-reset"; #reset-cells = <1>; }; pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; modepin_gpio: gpio { compatible = "xlnx,zynqmp-gpio-modepin"; gpio-controller; #gpio-cells = <2>; }; }; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; ranges; }; amba: axi { compatible = "simple-bus"; bootph-all; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN0>; power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; resets = <&zynqmp_reset ZYNQMP_RESET_CAN1>; power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; status = "disabled"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x0 0x10000>, <0x0 0xf9020000 0x0 0x20000>, <0x0 0xf9040000 0x0 0x20000>, <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; gpu: gpu@fd4b0000 { status = "disabled"; compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x868>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x869>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86a>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86b>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86c>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86d>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86e>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; /* iommus = <&smmu 0x86f>; */ power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; nand0: nand-controller@ff100000 { compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; status = "disabled"; reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; reset-names = "gem0_rst"; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; reset-names = "gem1_rst"; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; reset-names = "gem2_rst"; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "gem3_rst"; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { compatible = "xlnx,zynqmp-ocmc-1.0"; reg = <0x0 0xff960000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 10 4>; }; perf_monitor_ocm: perf-monitor@ffa00000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa00000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_ddr: perf-monitor@fd0b0000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd0b0000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <6>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <10>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_cci: perf-monitor@fd490000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xfd490000 0x0 0x10000>; interrupts = <0 123 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <0>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; perf_monitor_lpd: perf-monitor@ffa10000 { compatible = "xlnx,axi-perf-monitor"; reg = <0x0 0xffa10000 0x0 0x10000>; interrupts = <0 25 4>; interrupt-parent = <&gic>; xlnx,enable-profile = <0>; xlnx,enable-trace = <0>; xlnx,num-monitor-slots = <1>; xlnx,enable-event-count = <1>; xlnx,enable-event-log = <1>; xlnx,have-sampled-metric-cnt = <1>; xlnx,num-of-counters = <8>; xlnx,metric-count-width = <32>; xlnx,metrics-sample-count-width = <32>; xlnx,global-count-width = <32>; xlnx,metric-count-scale = <1>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x00 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; qspi: spi@ff0f0000 { bootph-all; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; psgtr: phy@fd400000 { compatible = "xlnx,zynqmp-psgtr-v1.1"; status = "disabled"; reg = <0x0 0xfd400000 0x0 0x40000>, <0x0 0xfd3d0000 0x0 0x1000>; reg-names = "serdes", "siou"; #phy-cells = <4>; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>;*/ }; sdhci0: mmc@ff160000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; power-domains = <&zynqmp_firmware PD_SD_0>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; }; sdhci1: mmc@ff170000 { bootph-all; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; power-domains = <&zynqmp_firmware PD_SD_1>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; #iommu-cells = <1>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { bootph-all; compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb@ff9d0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 65 4>, <0 65 4>, <0 69 4>, <0 75 4>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; }; usb1: usb@ff9e0000 { #address-cells = <2>; #size-cells = <2>; status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; ranges; dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg", "wakeup"; interrupts = <0 70 4>, <0 70 4>, <0 74 4>, <0 76 4>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; snps,resume-hs-terminations; /* dma-coherent; */ }; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; }; lpd_watchdog: watchdog@ff150000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 52 1>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; xilinx_ams: ams@ffa50000 { compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>; ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; }; ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>; }; }; zynqmp_dpdma: dma-controller@fd4c0000 { compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; iommus = <&smmu 0xce4>; #dma-cells = <1>; }; zynqmp_dpaud_setting: dp-aud@fd4ac000 { compatible = "xlnx,zynqmp-dpaud-setting", "syscon"; reg = <0x0 0xfd4ac000 0x0 0x1000>; }; zynqmp_dpsub: display@fd4a0000 { bootph-all; compatible = "xlnx,zynqmp-dpsub-1.7"; status = "disabled"; reg = <0x0 0xfd4a0000 0x0 0x1000>, <0x0 0xfd4aa000 0x0 0x1000>, <0x0 0xfd4ab000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf"; xlnx,dpaud-reg = <&zynqmp_dpaud_setting>; interrupts = <0 119 4>; interrupt-parent = <&gic>; iommus = <&smmu 0xce3>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; power-domains = <&zynqmp_firmware PD_DP>; resets = <&zynqmp_reset ZYNQMP_RESET_DP>; dma-names = "vid0", "vid1", "vid2", "gfx0"; dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; /* dummy node to to indicate there's no child i2c device */ i2c-bus { }; zynqmp_dp_snd_codec0: zynqmp-dp-snd-codec0 { compatible = "xlnx,dp-snd-codec"; clock-names = "aud_clk"; }; zynqmp_dp_snd_pcm0: zynqmp-dp-snd-pcm0 { compatible = "xlnx,dp-snd-pcm0"; dmas = <&zynqmp_dpdma 4>; dma-names = "tx"; }; zynqmp_dp_snd_pcm1: zynqmp-dp-snd-pcm1 { compatible = "xlnx,dp-snd-pcm1"; dmas = <&zynqmp_dpdma 5>; dma-names = "tx"; }; zynqmp_dp_snd_card0: zynqmp-dp-snd-card { compatible = "xlnx,dp-snd-card"; xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, <&zynqmp_dp_snd_pcm1>; xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; }; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcep108.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ep108 development board * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { model = "ZynqMP EP108"; aliases { mmc0 = &sdhci0; mmc1 = &sdhci1; serial0 = &uart0; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; max-speed = <100>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; eeprom@54 { compatible = "atmel,24c64"; reg = <0x54>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom@55 { compatible = "atmel,24c64"; reg = <0x55>; }; }; &sata { status = "okay"; ceva,broken-gen2; /* SATA Phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>; ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>; }; &sdhci0 { status = "okay"; bus-width = <8>; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: spi0_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi0_flash0@0 { label = "spi0_flash0"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: spi1_flash0@0 { compatible = "m25p80"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <50000000>; reg = <0>; spi1_flash0@0 { label = "spi1_flash0"; reg = <0x0 0x100000>; }; }; }; &usb0 { status = "okay"; dr_mode = "peripheral"; maximum-speed = "high-speed"; }; &usb1 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 1>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 0>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 0>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 0>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 0>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 0>; default-state = "on"; }; bt_power { label = "bt_power"; gpios = <&gpio 8 0>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 1>; /* WIFI_EN */ }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 1>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 1>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.17/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.18/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.19/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma_clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm_clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v4.20/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu_opp_table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba_apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: sdhci@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: sdhci@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include #include #include / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.0/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53", "arm,armv8"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr-sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr-sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr-sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr-sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.1/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.2/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include #include #include / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.3/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/avnet-ultra96-rev1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Avnet Ultra96 rev1 * * (C) Copyright 2018-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "Avnet Ultra96 Rev1"; compatible = "avnet,ultra96-rev1", "avnet,ultra96", "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; /* down */ wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus_det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ }; }; &gpio { gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * LSEXP_I2C0 */ label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* * LSEXP_I2C1 */ label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* * HSEXP_I2C2 */ label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* * HSEXP_I2C3 */ label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { no-1-8-v; disable-wp; broken-cd; /* CD has to be enabled by default */ }; &sdhci1 { bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1232-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1232 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZC1232 RevA"; compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1254-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1254 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1254 RevA"; compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1275-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZC1275 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Siva Durga Prasad Paladugu */ / { model = "ZynqMP ZC1275 RevA"; compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp"; aliases { serial0 = &uart0; serial1 = &dcc; }; }; &dcc { status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc1.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm015-dc1 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ reg = <0x55>; }; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* eMMC */ &sdhci0 { status = "okay"; bus-width = <8>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc2.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm016-dc2 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { can0 = &can0; can1 = &can1; ethernet0 = &gem2; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; spi0 = &spi0; spi1 = &spi1; }; }; &gem2 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@5 { reg = <5>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; &spi0 { status = "okay"; num-cs = <1>; spi0_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x100000>; }; }; }; &spi1 { status = "okay"; num-cs = <1>; spi1_flash0: flash0@0 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; partition@0 { label = "data"; reg = <0x0 0x84000>; }; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc3.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm017-dc3 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { /* VSC8211 */ reg = <0>; }; }; /* just eeprom here */ &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* IRQ not connected */ }; rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; }; }; /* eeprom24c02 and SE98A temp chip pca9306 */ &i2c1 { status = "okay"; clock-frequency = <400000>; }; &sata { status = "okay"; /* SATA phy OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; &usb0 { status = "okay"; dr_mode = "host"; }; /* ULPI SMSC USB3320 */ &usb1 { status = "okay"; dr_mode = "host"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc4.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP zc1751-xm018-dc4"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem0; ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; }; }; &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */ reg = <0>; }; ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */ reg = <7>; }; ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */ reg = <3>; }; ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */ reg = <8>; }; }; &gem1 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy7>; }; &gem2 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy3>; }; &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy8>; }; &i2c0 { clock-frequency = <400000>; status = "okay"; }; &i2c1 { clock-frequency = <400000>; status = "okay"; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zc1751-dc5.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP zc1751-xm019-dc5 * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Siva Durga Prasad * Michal Simek */ / { model = "ZynqMP zc1751-xm019-dc5 RevA"; compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; aliases { ethernet0 = &gem1; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; serial0 = &uart0; serial1 = &uart1; }; }; &gem1 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@0 { reg = <0>; }; }; &sdhci0 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu100-revc.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * Nathalie Chan King Choy */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/interrupt-controller/irq.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU100 RevC"; compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; serial1 = &uart0; serial2 = &dcc; spi0 = &spi0; spi1 = &spi1; mmc0 = &sdhci0; mmc1 = &sdhci1; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw4 { label = "sw4"; gpios = <&gpio 23 GPIO_ACTIVE_LOW>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; ds2 { label = "ds2"; gpios = <&gpio 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; ds3 { label = "ds3"; gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tx"; /* WLAN tx */ default-state = "off"; }; ds4 { label = "ds4"; gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0rx"; /* WLAN rx */ default-state = "off"; }; ds5 { label = "ds5"; gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; linux,default-trigger = "bluetooth-power"; }; vbus-det { /* U5 USB5744 VBUS detection via MIO25 */ label = "vbus_det"; gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; wmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; regulator-name = "wmmcsdio_fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */ post-power-on-delay-ms = <10>; }; }; &dcc { status = "okay"; }; &gpio { status = "okay"; gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL", "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS", "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1", "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1", "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT", "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE", "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL", "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C", "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E", "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3", "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &i2c1 { status = "okay"; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2csw_0: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; label = "LS-I2C0"; }; i2csw_1: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; label = "LS-I2C1"; }; i2csw_2: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; label = "HS-I2C2"; }; i2csw_3: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; label = "HS-I2C3"; }; i2csw_4: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <0x4>; pmic: pmic@5e { /* Custom TI PMIC u33 */ compatible = "ti,tps65086"; reg = <0x5e>; interrupt-parent = <&gpio>; interrupts = <77 GPIO_ACTIVE_LOW>; #gpio-cells = <2>; gpio-controller; }; }; i2csw_5: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* PS_PMBUS */ ina226@40 { /* u35 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <10000>; /* MIO31 is alert which should be routed to PMUFW */ }; }; i2csw_6: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* * Not Connected */ }; i2csw_7: i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* * usb5744 (DNP) - U5 * 100kHz - this is default freq for us */ }; }; }; /* SD0 only supports 3.3V, no level shifter */ &sdhci0 { status = "okay"; no-1-8-v; broken-cd; /* CD has to be enabled by default */ disable-wp; }; &sdhci1 { status = "okay"; bus-width = <0x4>; non-removable; disable-wp; cap-power-off-card; mmc-pwrseq = <&sdio_pwrseq>; vqmmc-supply = <&wmmcsdio_fixed>; #address-cells = <1>; #size-cells = <0>; wlcore: wifi@2 { compatible = "ti,wl1831"; reg = <2>; interrupt-parent = <&gpio>; interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */ }; }; &spi0 { /* Low Speed connector */ status = "okay"; label = "LS-SPI0"; }; &spi1 { /* High Speed connector */ status = "okay"; label = "HS-SPI1"; }; &uart0 { status = "okay"; bluetooth { compatible = "ti,wl1831-st"; enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; }; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu102-rev1.0.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 Rev1.0 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 Rev1.0"; compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &eeprom { #address-cells = <1>; #size-cells = <1>; board_sn: board-sn@0 { reg = <0x0 0x14>; }; eth_mac: eth-mac@20 { reg = <0x20 0x6>; }; board_name: board-name@d0 { reg = <0xd0 0x6>; }; board_revision: board-revision@e0 { reg = <0xe0 0x3>; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu102-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevA"; compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@21 { reg = <21>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu102-revb.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU102 RevB * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { model = "ZynqMP ZCU102 RevB"; compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 0>; linux,code = <108>; gpio-key,wakeup; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat_led { label = "heartbeat"; gpios = <&gpio 23 0>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { phy-handle = <&phyc>; phyc: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - PS_GTR_LAN_SEL0 * 1 - PS_GTR_LAN_SEL1 * 2 - PS_GTR_LAN_SEL2 * 3 - PS_GTR_LAN_SEL3 * 4 - PCI_CLK_DIR_SEL * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7, 10 - 17 - not connected */ gtr_sel0 { gpio-hog; gpios = <0 0>; output-low; /* PCIE = 0, DP = 1 */ line-name = "sel0"; }; gtr_sel1 { gpio-hog; gpios = <1 0>; output-high; /* PCIE = 0, DP = 1 */ line-name = "sel1"; }; gtr_sel2 { gpio-hog; gpios = <2 0>; output-high; /* PCIE = 0, USB0 = 1 */ line-name = "sel2"; }; gtr_sel3 { gpio-hog; gpios = <3 0>; output-high; /* PCIE = 0, SATA = 1 */ line-name = "sel3"; }; }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max15303@20 { /* u8 */ compatible = "maxim,max15303"; status = "disabled"; /* unreachable */ reg = <0x20>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; /* * Chip has interrupt present connected to PL * interrupt-parent = <&>; * interrupts = <>; */ }; }; /* 5 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu104-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU104 RevA"; compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; #address-cells = <1>; #size-cells = <1>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */ reg = <0x6c>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u175 */ reg = <0x43>; }; irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */ reg = <0x4d>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; tca6416_u97: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - IRPS5401_ALERT_B * 1 - HDMI_8T49N241_INT_ALM * 2 - MAX6643_OT_B * 3 - MAX6643_FANFAIL_B * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 7 - FMC_LPC_PRSNT_M2C_B * 4, 10 - 17 - not connected */ }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; }; /* 3, 6 not connected */ }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; disable-wp; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu106-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU106 RevA"; compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &uart1; serial2 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - SFP_SI5328_INT_ALM * 1 - HDMI_SI5328_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMC_HPC0_PRSNT_M2C_B * 11 - FMC_HPC1_PRSNT_M2C_B * 2-4, 7, 12-17 - not connected */ }; tca6416_u61: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; gpio-controller; #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - VCCPSPLL_EN * 1 - MGTRAVCC_EN * 2 - MGTRAVTT_EN * 3 - VCCPSDDRPLL_EN * 4 - MIO26_PMU_INPUT_LS * 5 - PL_PMBUS_ALERT * 6 - PS_PMBUS_ALERT * 7 - MAXIM_PMBUS_ALERT * 10 - PL_DDR4_VTERM_EN * 11 - PL_DDR4_VPP_2V5_EN * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON * 13 - PS_DIMM_SUSPEND_EN * 14 - PS_DDR4_VTERM_EN * 15 - PS_DDR4_VPP_2V5_EN * 16 - 17 - not connected */ }; i2c-mux@75 { /* u60 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ ina226@40 { /* u76 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <5000>; }; ina226@41 { /* u77 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u78 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u87 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u85 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u86 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u93 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u88 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@4a { /* u15 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u92 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* PL_PMBUS */ ina226@40 { /* u79 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u81 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u80 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u84 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@44 { /* u16 */ compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <5000>; }; ina226@45 { /* u65 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u74 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <5000>; }; ina226@47 { /* u75 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* MAXIM_PMBUS - 00 */ max15301@a { /* u46 */ compatible = "maxim,max15301"; reg = <0xa>; }; max15303@b { /* u4 */ compatible = "maxim,max15303"; reg = <0xb>; }; max15303@10 { /* u13 */ compatible = "maxim,max15303"; reg = <0x10>; }; max15301@13 { /* u47 */ compatible = "maxim,max15301"; reg = <0x13>; }; max15303@14 { /* u7 */ compatible = "maxim,max15303"; reg = <0x14>; }; max15303@15 { /* u6 */ compatible = "maxim,max15303"; reg = <0x15>; }; max15303@16 { /* u10 */ compatible = "maxim,max15303"; reg = <0x16>; }; max15303@17 { /* u9 */ compatible = "maxim,max15303"; reg = <0x17>; }; max15301@18 { /* u63 */ compatible = "maxim,max15301"; reg = <0x18>; }; max15303@1a { /* u49 */ compatible = "maxim,max15303"; reg = <0x1a>; }; max15303@1b { /* u8 */ compatible = "maxim,max15303"; reg = <0x1b>; }; max15303@1d { /* u18 */ compatible = "maxim,max15303"; reg = <0x1d>; }; max20751@72 { /* u95 */ compatible = "maxim,max20751"; reg = <0x72>; }; max20751@73 { /* u96 */ compatible = "maxim,max20751"; reg = <0x73>; }; }; /* Bus 3 is not connected */ }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u23 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u69 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u42 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* FAN controller */ temp@4c {/* lm96163 - u128 */ compatible = "national,lm96163"; reg = <0x4c>; }; }; /* 6 - 7 unconnected */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u135 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* HPC0_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* HPC1_IIC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SEP 3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SEP 2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SEP 1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SEP 0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/board/zcu111-reva.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ #include "include/dt-bindings/input/input.h" #include "include/dt-bindings/gpio/gpio.h" / { model = "ZynqMP ZCU111 RevA"; compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; serial0 = &uart0; serial1 = &dcc; }; gpio-keys { compatible = "gpio-keys"; autorepeat; sw19 { label = "sw19"; gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; linux,code = ; wakeup-source; autorepeat; }; }; leds { compatible = "gpio-leds"; heartbeat-led { label = "heartbeat"; gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; }; &dcc { status = "okay"; }; &gem3 { status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; phy0: phy@c { reg = <0xc>; ti,rx-internal-delay = <0x8>; ti,tx-internal-delay = <0xa>; ti,fifo-depth = <0x1>; ti,dp83867-rxctrl-strap-quirk; }; }; &i2c0 { status = "okay"; clock-frequency = <400000>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; gpio-controller; /* interrupt not connected */ #gpio-cells = <2>; /* * IRQ not connected * Lines: * 0 - MAX6643_OT_B * 1 - MAX6643_FANFAIL_B * 2 - MIO26_PMU_INPUT_LS * 4 - SFP_SI5382_INT_ALM * 5 - IIC_MUX_RESET_B * 6 - GEM3_EXP_RESET_B * 10 - FMCP_HSPC_PRSNT_M2C_B * 11 - CLK_SPI_MUX_SEL0 * 12 - CLK_SPI_MUX_SEL1 * 16 - IRPS5401_ALERT_B * 17 - INA226_PMBUS_ALERT * 3, 7, 13-15 - not connected */ }; i2c-mux@75 { /* u23 */ compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* PS_PMBUS */ /* PMBUS_ALERT done via pca9544 */ ina226@40 { /* u67 */ compatible = "ti,ina226"; reg = <0x40>; shunt-resistor = <2000>; }; ina226@41 { /* u59 */ compatible = "ti,ina226"; reg = <0x41>; shunt-resistor = <5000>; }; ina226@42 { /* u61 */ compatible = "ti,ina226"; reg = <0x42>; shunt-resistor = <5000>; }; ina226@43 { /* u60 */ compatible = "ti,ina226"; reg = <0x43>; shunt-resistor = <5000>; }; ina226@45 { /* u64 */ compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <5000>; }; ina226@46 { /* u69 */ compatible = "ti,ina226"; reg = <0x46>; shunt-resistor = <2000>; }; ina226@47 { /* u66 */ compatible = "ti,ina226"; reg = <0x47>; shunt-resistor = <5000>; }; ina226@48 { /* u65 */ compatible = "ti,ina226"; reg = <0x48>; shunt-resistor = <5000>; }; ina226@49 { /* u63 */ compatible = "ti,ina226"; reg = <0x49>; shunt-resistor = <5000>; }; ina226@4a { /* u3 */ compatible = "ti,ina226"; reg = <0x4a>; shunt-resistor = <5000>; }; ina226@4b { /* u71 */ compatible = "ti,ina226"; reg = <0x4b>; shunt-resistor = <5000>; }; ina226@4c { /* u77 */ compatible = "ti,ina226"; reg = <0x4c>; shunt-resistor = <5000>; }; ina226@4d { /* u73 */ compatible = "ti,ina226"; reg = <0x4d>; shunt-resistor = <5000>; }; ina226@4e { /* u79 */ compatible = "ti,ina226"; reg = <0x4e>; shunt-resistor = <5000>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */ reg = <0x43>; }; irps5401_44: irps54012@44 { /* IRPS5401 - u55 */ reg = <0x44>; }; irps5401_45: irps54012@45 { /* IRPS5401 - u57 */ reg = <0x45>; }; /* u68 IR38064 +0 */ /* u70 IR38060 +1 */ /* u74 IR38060 +2 */ /* u75 IR38060 +6 */ /* J19 header too */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* SYSMON */ }; }; }; &i2c1 { status = "okay"; clock-frequency = <400000>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x74>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* * IIC_EEPROM 1kB memory which uses 256B blocks * where every block has different address. * 0 - 256B address 0x54 * 256B - 512B address 0x55 * 512B - 768B address 0x56 * 768B - 1024B address 0x57 */ eeprom: eeprom@54 { /* u88 */ compatible = "atmel,24c08"; reg = <0x54>; }; }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; si5341: clock-generator@36 { /* SI5341 - u46 */ reg = <0x36>; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; si570_1: clock-generator@5d { /* USER SI570 - u47 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <300000000>; clock-frequency = <300000000>; }; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */ #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <148500000>; }; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; si5328: clock-generator@69 { /* SI5328 - u48 */ reg = <0x69>; }; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; sc18is603@2f { /* sc18is602 - u93 */ compatible = "nxp,sc18is603"; reg = <0x2f>; /* 4 gpios for CS not handled by driver */ /* * USB2ANY cable or * LMK04208 - u90 or * LMX2594 - u102 or * LMX2594 - u103 or * LMX2594 - u104 */ }; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* FMC connector */ }; /* 7 NC */ }; i2c-mux@75 { compatible = "nxp,pca9548"; /* u27 */ #address-cells = <1>; #size-cells = <0>; reg = <0x75>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; /* FMCP_HSPC_IIC */ }; i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; /* NC */ }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; /* SYSMON */ }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; /* DDR4 SODIMM */ }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; /* SFP3 */ }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; /* SFP2 */ }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; /* SFP1 */ }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; /* SFP0 */ }; }; }; &sata { status = "okay"; /* SATA OOB timing settings */ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; }; /* SD1 with level shifter */ &sdhci1 { status = "okay"; no-1-8-v; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp-clk.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * Clock specification for Xilinx ZynqMP * * (C) Copyright 2015-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek */ / { clk100: clk100 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; clk125: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; }; clk200: clk200 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; }; clk250: clk250 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; }; clk300: clk300 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000000>; }; clk600: clk600 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <600000000>; }; dp_aclk: clock0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-accuracy = <100>; }; dp_aud_clk: clock1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; clock-accuracy = <100>; }; dpdma_clk: dpdma-clk { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <533000000>; }; drm_clock: drm-clock { compatible = "fixed-clock"; #clock-cells = <0x0>; clock-frequency = <262750000>; clock-accuracy = <0x64>; }; }; &can0 { clocks = <&clk100 &clk100>; }; &can1 { clocks = <&clk100 &clk100>; }; &fpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &fpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan1 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan2 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan3 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan4 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan5 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan6 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan7 { clocks = <&clk600>, <&clk100>; }; &lpd_dma_chan8 { clocks = <&clk600>, <&clk100>; }; &gem0 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem1 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem2 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gem3 { clocks = <&clk125>, <&clk125>, <&clk125>; }; &gpio { clocks = <&clk100>; }; &i2c0 { clocks = <&clk100>; }; &i2c1 { clocks = <&clk100>; }; &sata { clocks = <&clk250>; }; &sdhci0 { clocks = <&clk200 &clk200>; }; &sdhci1 { clocks = <&clk200 &clk200>; }; &spi0 { clocks = <&clk200 &clk200>; }; &spi1 { clocks = <&clk200 &clk200>; }; &uart0 { clocks = <&clk100 &clk100>; }; &uart1 { clocks = <&clk100 &clk100>; }; &usb0 { clocks = <&clk250>, <&clk250>; }; &usb1 { clocks = <&clk250>, <&clk250>; }; &watchdog0 { clocks = <&clk250>; }; ================================================ FILE: device_tree/data/kernel_dtsi/v5.4/zynqmp/zynqmp.dtsi ================================================ // SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * * (C) Copyright 2014-2022 Xilinx, Inc. * (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. * * Michal Simek * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. */ / { compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu2: cpu@2 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; cpu3: cpu@3 { compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; }; idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; arm,psci-suspend-param = <0x40000000>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <600>; min-residency-us = <10000>; }; }; }; cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { opp-hz = /bits/ 64 <1199999988>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp01 { opp-hz = /bits/ 64 <599999994>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp02 { opp-hz = /bits/ 64 <399999996>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; opp03 { opp-hz = /bits/ 64 <299999997>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = <0 143 4>, <0 144 4>, <0 145 4>, <0 146 4>; }; psci { compatible = "arm,psci-0.2"; method = "smc"; }; timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <1 13 0xf08>, <1 14 0xf08>, <1 11 0xf08>, <1 10 0xf08>; }; amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, <0x0 0xf9040000 0x20000>, <0x0 0xf9060000 0x20000>; interrupt-controller; interrupt-parent = <&gic>; interrupts = <1 9 0xf04>; }; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; can0: can@ff060000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; interrupts = <0 23 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; can1: can@ff070000 { compatible = "xlnx,zynq-can-1.0"; status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; }; cci: cci@fd6e0000 { compatible = "arm,cci-400"; reg = <0x0 0xfd6e0000 0x0 0x9000>; ranges = <0x0 0x0 0xfd6e0000 0x10000>; #address-cells = <1>; #size-cells = <1>; pmu@9000 { compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; interrupts = <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>, <0 123 4>; }; }; /* GDMA */ fpd_dma_chan1: dma@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan2: dma@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan3: dma@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan4: dma@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan5: dma@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan6: dma@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan7: dma@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; fpd_dma_chan8: dma@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <128>; }; /* LPDDMA default allows only secured access. inorder to enable * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; }; mc: memory-controller@fd070000 { compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; interrupts = <0 112 4>; }; gem0: ethernet@ff0b0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem1: ethernet@ff0c0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem2: ethernet@ff0d0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gem3: ethernet@ff0e0000 { compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; }; i2c0: i2c@ff020000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; i2c1: i2c@ff030000 { compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; }; pcie: pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "disabled"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; msi-controller; device_type = "pci"; interrupt-parent = <&gic>; interrupts = <0 118 4>, <0 117 4>, <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, <0x80 0x00000000 0x0 0x1000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ bus-range = <0x00 0xff>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; #interrupt-cells = <1>; }; }; rtc: rtc@ffa60000 { compatible = "xlnx,zynqmp-rtc"; status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; interrupts = <0 26 4>, <0 27 4>; interrupt-names = "alarm", "sec"; calibration = <0x8000>; }; sata: ahci@fd0c0000 { compatible = "ceva,ahci-1v84"; status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; }; sdhci0: mmc@ff160000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; sdhci1: mmc@ff170000 { compatible = "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; }; smmu: smmu@fd800000 { compatible = "arm,mmu-500"; reg = <0x0 0xfd800000 0x0 0x20000>; status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; interrupts = <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 19 4>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@ff050000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 20 4>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; }; ttc0: timer@ff110000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; }; ttc1: timer@ff120000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; }; ttc2: timer@ff130000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; }; ttc3: timer@ff140000 { compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; }; uart0: serial@ff000000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; uart1: serial@ff010000 { compatible = "cdns,uart-r1p12", "xlnx,xuartps"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; }; usb0: usb@fe200000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 65 4>; reg = <0x0 0xfe200000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; usb1: usb@fe300000 { compatible = "snps,dwc3"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 70 4>; reg = <0x0 0xfe300000 0x0 0x40000>; clock-names = "clk_xin", "clk_ahb"; }; watchdog0: watchdog@fd4d0000 { compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <10>; }; }; }; ================================================ FILE: dfx_axi_shutdown_manager/data/dfx_axi_shutdown_manager.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dfx_axi_shutdown_manager OPTION supported_peripherals = (dfx_axi_shutdown_manager); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dfx_axi_shutdown_manager; END driver ================================================ FILE: dfx_axi_shutdown_manager/data/dfx_axi_shutdown_manager.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,dfx-axi-shutdown-manager"] set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: dmaps/data/dmaps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dmaps OPTION supported_peripherals = (ps7_dma psu_adma psu_gdma psu_csudma psv_adma psv_gdma psv_csudma psx_pmcdma); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dmaps; END driver ================================================ FILE: dmaps/data/dmaps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { set ip [get_cells -hier $drv_handle] #disabling non-secure dma if { [string match -nocase $ip "ps7_dma_ns"] } { set_property NAME none $drv_handle } } ================================================ FILE: dp/data/dp.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dp OPTION supported_peripherals = (psu_dp psv_dp); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dp; END driver ================================================ FILE: dp/data/dp.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } generate_dp_param $drv_handle } proc generate_dp_param {drv_handle} { set periph_list [get_cells -hier] foreach periph $periph_list { set zynq_ultra_ps [get_property IP_NAME $periph] if {[string match -nocase $zynq_ultra_ps "zynq_ultra_ps_e"] } { set dp_sel [get_property CONFIG.PSU__DP__LANE_SEL [get_cells -hier $periph]] set mode [lindex $dp_sel 0] set lan_sel [lindex $dp_sel 1] set dp_freq [get_property CONFIG.PSU__DP__REF_CLK_FREQ [get_cells -hier $periph]] set dp_freq "${dp_freq}000000" set ref_clk_list [get_property CONFIG.PSU__DP__REF_CLK_SEL [get_cells -hier $periph]] regsub -all {[^0-9]} [lindex $ref_clk_list 1] "" val if {[string match -nocase $mode "Single"]} { if {[string match -nocase $lan_sel "Lower"]} { set lan_name "dp-phy0" set lan_phy_type "psgtr 1 6 0 $val" set_drv_prop $drv_handle phy-names "$lan_name" stringlist set_drv_prop $drv_handle phys "$lan_phy_type" reference } else { set lan_name "dp-phy0" set lan_phy_type "psgtr 3 6 0 $val" set_drv_prop $drv_handle phy-names "$lan_name" stringlist set_drv_prop $drv_handle phys "$lan_phy_type" reference } set_drv_prop $drv_handle xlnx,max-lanes 1 int } elseif {[string match -nocase $mode "Dual"]} { if {[string match -nocase $lan_sel "Lower"]} { set lan0_phy_type "psgtr 1 6 0 $val" set lan1_phy_type "psgtr 0 6 1 $val" set_drv_prop $drv_handle phy-names "dp-phy0\",\"dp-phy1" stringlist set phy_ids "$lan0_phy_type>, <&$lan1_phy_type" set_drv_prop $drv_handle phys "$phy_ids" reference } else { set lan0_phy_type "psgtr 3 6 0 $val" set lan1_phy_type "psgtr 2 6 1 $val" set_drv_prop $drv_handle phy-names "dp-phy0\",\"dp-phy1" stringlist set phy_ids "$lan0_phy_type>, <&$lan1_phy_type" set_drv_prop $drv_handle phys "$phy_ids" reference } set_drv_prop $drv_handle xlnx,max-lanes 2 int } } } set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $mainline_ker "none"]} { set dp_list "zynqmp_dp_snd_pcm0 zynqmp_dp_snd_pcm1 zynqmp_dp_snd_card0 zynqmp_dp_snd_codec0" set dts_file [get_property CONFIG.pcw_dts [get_os]] foreach dp_name ${dp_list} { set dp_node [add_or_get_dt_node -n "&${dp_name}" -d $dts_file] hsi::utils::add_new_dts_param "${dp_node}" "status" "okay" string } } } ================================================ FILE: dp_rx/data/dp_rx.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dp_rx OPTION supported_peripherals = (v_dp_rxss1); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dp_rx; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: dp_rx/data/dp_rx.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } lappend compatible "xlnx,v-dp-rxss-3.0" "xlnx,v-dp-rxss-3.1" set_drv_prop $drv_handle compatible "$compatible" stringlist set audio_channels [get_property CONFIG.AUDIO_CHANNELS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,audio-channels" $audio_channels int set audio_enable [get_property CONFIG.AUDIO_ENABLE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enable" $audio_enable int set bits_per_color [get_property CONFIG.BITS_PER_COLOR [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,bpc" $bits_per_color int set hdcp22_enable [get_property CONFIG.HDCP22_ENABLE [get_cells -hier $drv_handle]] if {$hdcp22_enable == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp22-enable" "" boolean } set hdcp_enable [get_property CONFIG.HDCP_ENABLE [get_cells -hier $drv_handle]] if {$hdcp_enable == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp-enable" "" boolean } set include_fec_ports [get_property CONFIG.INCLUDE_FEC_PORTS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,include-fec-ports" $include_fec_ports int set edid_ip [get_cells -hier -filter IP_NAME==vid_edid] if {[llength $edid_ip]} { set baseaddr_dp_rx [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]] set highaddr_dp_rx [get_property CONFIG.C_HIGHADDR [get_cells -hier $drv_handle]] set baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $edid_ip]] set highaddr [get_property CONFIG.C_HIGHADDR [get_cells -hier $edid_ip]] set reg_val_0 [generate_reg_property $baseaddr_dp_rx $highaddr_dp_rx] set updat [lappend updat $reg_val_0] set reg_val_1 [generate_reg_property $baseaddr $highaddr] set updat [lappend updat $reg_val_1] set reg_val [lindex $updat 0] append reg_val ">, <[lindex $updat 1]" set_drv_prop $drv_handle reg "$reg_val" hexintlist } lappend reg_names "dp_base" "edid_base" hsi::utils::add_new_dts_param "${node}" "reg-names" $reg_names stringlist lappend phy_names "dp-phy0" "dp-phy1" "dp-phy2" "dp-phy3" hsi::utils::add_new_dts_param "${node}" "phy-names" $phy_names stringlist set lane_count [get_property CONFIG.LANE_COUNT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,lane-count" $lane_count int hsi::utils::add_new_dts_param "${node}" "xlnx,dp-retimer" "xfmc" reference set i 0 set updat "" while {$i < $lane_count} { set rxpinname "s_axis_lnk_rx_lane$i" set channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $rxpinname] if {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} { set phy_s "${channelip}rxphy_lane${i} 0 1 1 1" set clocks [lappend clocks $phy_s] set updat [lappend updat $phy_s] } incr i } set len [llength $updat] switch $len { "1" { set refs [lindex $updat 0] hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "2" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "3" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "4" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } } set mode [get_property CONFIG.MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,mode" $mode int set num_streams [get_property CONFIG.NUM_STREAMS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,num-streams" $num_streams int set phy_data_width [get_property CONFIG.PHY_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,phy-data-width" $phy_data_width int set pixel_mode [get_property CONFIG.PIXEL_MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,pixel-mode" $pixel_mode int set sim_mode [get_property CONFIG.SIM_MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,sim-mode" $sim_mode string set video_interface [get_property CONFIG.VIDEO_INTERFACE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,video-interface" $video_interface int set vid_phy_ctlr [get_cells -hier -filter IP_NAME==vid_phy_controller] if {[llength $vid_phy_ctlr]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vidphy" $vid_phy_ctlr reference } set ports_node [add_or_get_dt_node -n "ports" -l dprx_ports$drv_handle -p ${node}] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port0_node [add_or_get_dt_node -n "port" -u 0 -l dprx_port$drv_handle -p $ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int set dprxip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_video_stream1"] foreach ip $dprxip { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set dp_rx_node [add_or_get_dt_node -n "endpoint" -l dprx_out$drv_handle -p $port0_node] gen_endpoint $drv_handle "dprx_out$drv_handle" hsi::utils::add_new_dts_param "$dp_rx_node" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle $ip$drv_handle if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $ip $drv_handle } } else { set connectip [get_connect_ip $ip $intfpins] if {[llength $connectip]} { set sdi_rx_node [add_or_get_dt_node -n "endpoint" -l dprx_out$drv_handle -p $port0_node] gen_endpoint $drv_handle "dprx_out$drv_handle" hsi::utils::add_new_dts_param "$dp_rx_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle $connectip$drv_handle if {[string match -nocase [get_property IP_NAME $connectip] "axi_vdma"] || [string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $connectip $drv_handle } } } } } proc gen_frmbuf_wr_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_dprx$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" dprx_out$drv_handle reference } ================================================ FILE: dp_tx/data/dp_tx.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dp_tx OPTION supported_peripherals = (v_dp_txss1); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dp_tx; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: dp_tx/data/dp_tx.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } lappend compatible "xlnx,v-dp-txss-3.1" set_drv_prop $drv_handle compatible "$compatible" stringlist set num_audio_channels [get_property CONFIG.Number_of_Audio_Channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,num-audio-channels" $num_audio_channels int set audio_enable [get_property CONFIG.AUDIO_ENABLE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enable" $audio_enable int set bits_per_color [get_property CONFIG.BITS_PER_COLOR [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,bpc" $bits_per_color int set hdcp22_enable [get_property CONFIG.HDCP22_ENABLE [get_cells -hier $drv_handle]] if {$hdcp22_enable == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp22-enable" "" boolean } set hdcp_enable [get_property CONFIG.HDCP_ENABLE [get_cells -hier $drv_handle]] if {$hdcp_enable == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp-enable" "" boolean } set include_fec_ports [get_property CONFIG.INCLUDE_FEC_PORTS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,include-fec-ports" $include_fec_ports int lappend reg_names "dp_base" hsi::utils::add_new_dts_param "${node}" "reg-names" $reg_names stringlist lappend phy_names "dp-phy0" "dp-phy1" "dp-phy2" "dp-phy3" hsi::utils::add_new_dts_param "${node}" "phy-names" $phy_names stringlist set lane_count [get_property CONFIG.LANE_COUNT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-lanes" $lane_count int hsi::utils::add_new_dts_param "${node}" "xlnx,dp-retimer" "xfmc" reference set hdcp_keymngmt [get_cells -hier -filter IP_NAME==hdcp_keymngmt_blk] if {[llength $hdcp_keymngmt]} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp1x-keymgmt" [lindex $hdcp_keymngmt 1] reference } set clknames "s_axi_aclk tx_vid_clk" overwrite_clknames $clknames $drv_handle set i 0 set updat "" while {$i < $lane_count} { set txpinname "m_axis_lnk_tx_lane$i" set channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname] if {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} { set phy_s "${channelip}txphy_lane${i} 0 1 1 1" set clocks [lappend clocks $phy_s] set updat [lappend updat $phy_s] } incr i } set len [llength $updat] switch $len { "1" { set refs [lindex $updat 0] hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "2" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "3" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } "4" { set refs [lindex $updat 0] append refs ">, <&[lindex $updat 1]>, <&[lindex $updat 2]>, <&[lindex $updat 3]" hsi::utils::add_new_dts_param "${node}" "phys" "$refs" reference } } set link_rate [get_property CONFIG.LINK_RATE [get_cells -hier $drv_handle]] set link_rate [expr {${link_rate} * 100000}] set link_rate [expr int ($link_rate)] hsi::utils::add_new_dts_param "${node}" "xlnx,max-link-rate" $link_rate int set mode [get_property CONFIG.MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,mode" $mode int set num_streams [get_property CONFIG.NUM_STREAMS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,num-streams" $num_streams int set phy_data_width [get_property CONFIG.PHY_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,phy-data-width" $phy_data_width int set pixel_mode [get_property CONFIG.PIXEL_MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,pixel-mode" $pixel_mode int set sim_mode [get_property CONFIG.SIM_MODE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,sim-mode" $sim_mode string set video_interface [get_property CONFIG.VIDEO_INTERFACE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,video-interface" $video_interface int set vtcip [get_cells -hier -filter {IP_NAME == "v_tc"}] if {[llength $vtcip]} { set baseaddr [get_property CONFIG.C_BASEADDR [get_cells -hier $vtcip]] if {[llength $baseaddr]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vtc-offset" "$baseaddr" int } } set ports_node [add_or_get_dt_node -n "ports" -l dptx_ports$drv_handle -p ${node}] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port0_node [add_or_get_dt_node -n "port" -u 0 -l dptx_port$drv_handle -p $ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int set dptxip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video_stream1"] foreach ip $dptxip { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set dp_tx_node [add_or_get_dt_node -n "endpoint" -l dptx_out$drv_handle -p $port0_node] gen_endpoint $drv_handle "dptx_out$drv_handle" if {[string match -nocase [get_property IP_NAME $ip] "v_mix"]} { hsi::utils::add_new_dts_param "$dp_tx_node" "remote-endpoint" "mixer_crtc$ip" reference gen_remoteendpoint $drv_handle "mixer_crtc$ip" } else { hsi::utils::add_new_dts_param "$dp_tx_node" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle $ip$drv_handle } if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_rd"]} { gen_pl_disp_node $ip $drv_handle } } else { set connectip [get_connect_ip $ip $intfpins] if {[llength $connectip]} { set dp_tx_node [add_or_get_dt_node -n "endpoint" -l dptx_out$drv_handle -p $port0_node] gen_endpoint $drv_handle "dptx_out$drv_handle" if {[string match -nocase [get_property IP_NAME $ip] "v_mix"]} { hsi::utils::add_new_dts_param "$dp_tx_node" "remote-endpoint" "mixer_crtc$connectip" reference gen_remoteendpoint $drv_handle "mixer_crtc$connectip" } else { hsi::utils::add_new_dts_param "$dp_tx_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle $connectip$drv_handle } if {[string match -nocase [get_property IP_NAME $connectip] "axi_vdma"] || [string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_rd"]} { gen_pl_disp_node $connectip $drv_handle } } } gen_xfmc_node } } proc gen_pl_disp_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set pl_disp [add_or_get_dt_node -n "drm-pl-disp-drv" -l "v_pl_disp" -p $bus_node] hsi::utils::add_new_dts_param $pl_disp "compatible" "xlnx,pl-disp" string hsi::utils::add_new_dts_param $pl_disp "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $pl_disp "dma-names" "dma0" string hsi::utils::add_new_dts_param $pl_disp "xlnx,vformat" "YUYV" string set pl_port [add_or_get_dt_node -n "port" -l "pl_disp_port" -u 0 -p $pl_disp] hsi::utils::add_new_dts_param "$pl_port" "reg" 0 int set pl_disp_crtc [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $pl_port] hsi::utils::add_new_dts_param "$pl_disp_crtc" "remote-endpoint" dptx_out$drv_handle reference } #generate fmc card node as this is required when display port exits proc gen_xfmc_node {} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set pl_disp [add_or_get_dt_node -n "xv_fmc" -l "xfmc" -p $bus_node] hsi::utils::add_new_dts_param $pl_disp "compatible" "xilinx-vfmc" string } ================================================ FILE: dpu_eu/data/dpu_eu.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver dpu_eu OPTION supported_peripherals = (dpu_eu); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = dpu_eu; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: dpu_eu/data/dpu_eu.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "deephi,dpu"] set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: emaclite/data/emaclite.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver emaclite OPTION supported_peripherals = (axi_ethernetlite); OPTION driver_state = ACTIVE; OPTION NAME = emaclite; OPTION supported_os_types = (DTS); PARAMETER name = system.dts, default = "local-mac-address", type = stringlist; PARAMETER name = dev_type, default = ethernet, type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-ethernetlite-1.00.a"; DTGPARAM name = device_type, type = string, default = network; DTGPARAM name = dtg.alias, type = string, default = ethernet; DTGPARAM name = local-mac-address, default = "00 0a 35 00 00 00", type = bytelist; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: emaclite/data/emaclite.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-ethernetlite-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist update_eth_mac_addr $drv_handle set node [gen_peripheral_nodes $drv_handle] gen_mdio_node $drv_handle $node } ================================================ FILE: emacps/data/emacps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver emacps OPTION supported_peripherals = (ps7_ethernet psu_ethernet psv_ethernet psx_ethernet); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = emacps; PARAMETER name = dev_type, default = ethernet, type = string; PARAMETER name = system.dts, default = "local-mac-address", type = stringlist; DTGPARAM name = local-mac-address, default = "00 0a 35 00 00 00", type = bytelist DTGPARAM name = dtg.alias, type = string, default = ethernet; DTGPARAM name = phy-mode, default = gmii DTGPARAM name = "xlnx,ptp-enet-clock" END driver ================================================ FILE: emacps/data/emacps.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # ############################################################################## variable phy_count 0 ############################################################################## proc is_gmii2rgmii_conv_present {slave} { set phy_addr -1 set ipconv 0 set ips [get_cells -hier -filter {IP_NAME == "gmii_to_rgmii"}] set ip_name [get_property NAME $slave] set slave_pins [get_pins -of_objects [get_cells -hier $slave]] foreach ip $ips { set ipconv2eth_pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $ip "gmii_txd"]]] if {[regexp -nocase {(enet[0-3])} "$ipconv2eth_pins" match]} { set number [regexp -all -inline -- {[0-3]+} $ipconv2eth_pins] if {[string match -nocase $slave "psu_ethernet_$number"] || [string match -nocase $slave "ps7_ethernet_$number"]} { set ipconv $ip set phy_addr [get_property "CONFIG.C_PHYADDR" $ipconv] break } } foreach gmii_pin ${ipconv2eth_pins} { # check if it is connected to the slave IP if { [lsearch ${slave_pins} $gmii_pin] >= 0 } { set ipconv $ip set phy_addr [get_property "CONFIG.C_PHYADDR" $ipconv] break } } if { $phy_addr >= 0 } { break } } return "$phy_addr $ipconv" } proc gen_phy_node args { set mdio_node [lindex $args 0] set phy_name [lindex $args 1] set phya [lindex $args 2] set default_dts [get_property CONFIG.pcw_dts [get_os]] set rgmii_node [add_or_get_dt_node -l $phy_name -n $phy_name -u $phya -d $default_dts -p $mdio_node] hsi::utils::add_new_dts_param "${rgmii_node}" "reg" $phya int hsi::utils::add_new_dts_param "${rgmii_node}" "compatible" "xlnx,gmii-to-rgmii-1.0" string hsi::utils::add_new_dts_param "${rgmii_node}" "phy-handle" phy1 reference } proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } update_eth_mac_addr $drv_handle set slave [get_cells -hier $drv_handle] set phymode [hsi::utils::get_ip_param_value $slave "C_ETH_MODE"] if { $phymode == 0 } { set_property CONFIG.phy-mode "gmii" $drv_handle } elseif { $phymode == 2 } { set_property CONFIG.phy-mode "sgmii" $drv_handle } else { set_property CONFIG.phy-mode "rgmii-id" $drv_handle } set hwproc [get_cells -hier [get_sw_processor]] if { [llength [get_sw_processor] ] && [llength $hwproc] } { set ps7_cortexa9_1x_clk [hsi::utils::get_ip_param_value $hwproc "C_CPU_1X_CLK_FREQ_HZ"] set_property CONFIG.xlnx,ptp-enet-clock "$ps7_cortexa9_1x_clk" $drv_handle } ps7_reset_handle $drv_handle CONFIG.C_ENET_RESET CONFIG.enet-reset # only generate the mdio node if it has mdio set has_mdio [get_property CONFIG.C_HAS_MDIO $slave] if { $has_mdio == "0" } { return 0 } # node must be created before child node set node [gen_peripheral_nodes $drv_handle] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psu_cortexa53"] } { set zynq_periph [get_cells -hier -filter {IP_NAME == zynq_ultra_ps_e}] set avail_param [list_property [get_cells -hier $zynq_periph]] if {[lsearch -nocase $avail_param "CONFIG.PSU__GEM__TSU__ENABLE"] >= 0} { set val [get_property CONFIG.PSU__GEM__TSU__ENABLE [get_cells -hier $zynq_periph]] if {$val == 1} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set root_node [add_or_get_dt_node -n / -d ${default_dts}] set tsu_node [add_or_get_dt_node -n "tsu_ext_clk" -l "tsu_ext_clk" -d $default_dts -p $root_node] hsi::utils::add_new_dts_param "${tsu_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${tsu_node}" "#clock-cells" 0 int set tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${tsu_node}" "clock-frequency" ${tsu-clk-freq} int set_drv_prop_if_empty $drv_handle "clock-names" "pclk hclk tx_clk rx_clk tsu_clk" stringlist if {[string match -nocase $node "&gem3"]} { set_drv_prop_if_empty $drv_handle "clocks" "zynqmp_clk 31>, <&zynqmp_clk 107>, <&zynqmp_clk 48>, <&zynqmp_clk 52>, <&tsu_ext_clk" reference } elseif {[string match -nocase $node "&gem2"]} { set_drv_prop_if_empty $drv_handle "clocks" "zynqmp_clk 31>, <&zynqmp_clk 106>, <&zynqmp_clk 47>, <&zynqmp_clk 51>, <&tsu_ext_clk" reference } elseif {[string match -nocase $node "&gem1"]} { set_drv_prop_if_empty $drv_handle "clocks" "zynqmp_clk 31>, <&zynqmp_clk 105>, <&zynqmp_clk 46>, <&zynqmp_clk 50>, <&tsu_ext_clk" reference } elseif {[string match -nocase $node "&gem0"]} { set_drv_prop_if_empty $drv_handle "clocks" "zynqmp_clk 31>, <&zynqmp_clk 104>, <&zynqmp_clk 45>, <&zynqmp_clk 49>, <&tsu_ext_clk" reference } } } } if {[string match -nocase $proc_type "psv_cortexa72"] } { set versal_periph [get_cells -hier -filter {IP_NAME == versal_cips || IP_NAME == ps_wizard}] if {[llength $versal_periph]} { set avail_param [list_property [get_cells -hier $versal_periph]] if {[lsearch -nocase $avail_param "CONFIG.PS_GEM_TSU_ENABLE"] >= 0} { set val [get_property CONFIG.PS_GEM_TSU_ENABLE [get_cells -hier $versal_periph]] if {$val == 1} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set root_node [add_or_get_dt_node -n / -d ${default_dts}] set tsu_node [add_or_get_dt_node -n "tsu_ext_clk" -l "tsu_ext_clk" -d $default_dts -p $root_node] hsi::utils::add_new_dts_param "${tsu_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${tsu_node}" "#clock-cells" 0 int set tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${tsu_node}" "clock-frequency" ${tsu-clk-freq} int set_drv_prop_if_empty $drv_handle "clock-names" "pclk hclk tx_clk rx_clk tsu_clk" stringlist if {[string match -nocase $node "&gem0"]} { set_drv_prop_if_empty $drv_handle "clocks" "versal_clk 82>, <&versal_clk 88>, <&versal_clk 49>, <&versal_clk 48>, <&tsu_ext_clk" reference } elseif {[string match -nocase $node "&gem1"]} { set_drv_prop_if_empty $drv_handle "clocks" "versal_clk 82>, <&versal_clk 89>, <&versal_clk 51>, <&versal_clk 50>, <&tsu_ext_clk" reference } } } } } if {[string match -nocase $proc_type "psx_cortexa78"] } { set versalnet_periph [get_cells -hier -filter {IP_NAME == psx_wizard}] set psx_pmcx_params [get_property CONFIG.PSX_PMCX_CONFIG [get_cells -hier $versalnet_periph]] set psx_gem_tsu_enable "" if {[llength $psx_pmcx_params]} { set psx_gem_tsu "" if {[dict exists $psx_pmcx_params "PSX_GEM_TSU"]} { set psx_gem_tsu [dict get $psx_pmcx_params "PSX_GEM_TSU"] if {[dict exists $psx_gem_tsu "ENABLE"]} { set psx_gem_tsu_enable [dict get $psx_gem_tsu "ENABLE"] } } } if {$psx_gem_tsu_enable == 1} { set default_dts [get_property CONFIG.pcw_dts [get_os]] set root_node [add_or_get_dt_node -n / -d ${default_dts}] set tsu_node [add_or_get_dt_node -n "tsu_ext_clk" -l "tsu_ext_clk" -d $default_dts -p $root_node] hsi::utils::add_new_dts_param "${tsu_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${tsu_node}" "#clock-cells" 0 int set tsu-clk-freq [get_property CONFIG.C_ENET_TSU_CLK_FREQ_HZ [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${tsu_node}" "clock-frequency" ${tsu-clk-freq} int set_drv_prop_if_empty $drv_handle "clock-names" "pclk hclk tx_clk rx_clk tsu_clk" stringlist if {[string match -nocase $node "&gem0"]} { set_drv_prop_if_empty $drv_handle "clocks" "versal_net_clk 82>, <&versal_net_clk 88>, <&versal_net_clk 49>, <&versal_net_clk 48>, <&tsu_ext_clk" reference } elseif {[string match -nocase $node "&gem1"]} { set_drv_prop_if_empty $drv_handle "clocks" "versal_net_clk 82>, <&versal_net_clk 89>, <&versal_net_clk 51>, <&versal_net_clk 50>, <&tsu_ext_clk" reference } } } # check if gmii2rgmii converter is used. set conv_data [is_gmii2rgmii_conv_present $slave] set phya [lindex $conv_data 0] if { $phya != "-1" } { set phy_name "[lindex $conv_data 1]" set_drv_prop $drv_handle phy-handle "phy1" reference set mdio_node [gen_mdio1_node $drv_handle $node] gen_phy_node $mdio_node $phy_name $phya } set ip_name " " if {[string match -nocase $proc_type "ps7_cortexa9"] } { if {[string match -nocase $node "&gem1"]} { set zynq_periph [get_cells -hier -filter {IP_NAME == processing_system7}] set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $zynq_periph] "ENET1_MDIO_O"]] set sink_periph "" if {[llength $port0_pins]} { set sink_periph [::hsi::get_cells -of_objects $port0_pins] } if {[llength $sink_periph]} { set ip_name [get_property IP_NAME $sink_periph] } if {[llength $ip_name] && [string match -nocase $ip_name "gig_ethernet_pcs_pma"]} { set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $sink_periph] "phyaddr"]] if {[llength $pin]} { set periph [::hsi::get_cells -of_objects $pin] } if {[llength $periph]} { set val [get_property CONFIG.CONST_VAL $periph] set inhex [format %x $val] set_drv_prop $drv_handle phy-handle "phy$inhex" reference set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node] hsi::utils::add_new_dts_param "${pcspma_phy_node}" "reg" $val int set phy_type [get_property CONFIG.Standard $sink_periph] set is_sgmii [get_property CONFIG.c_is_sgmii $sink_periph] if {$phy_type == "1000BASEX"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x5 int } elseif { $is_sgmii == "true"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x4 int } else { dtg_warning "unsupported phytype:$phy_type" } } } } } if {[string match -nocase $proc_type "psu_cortexa53"] } { set sink_periph "" if {[string match -nocase $node "&gem0"]} { set connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph "MDIO_ENET0"] if {[llength $connected_ip]} { set ip_name [get_property IP_NAME $connected_ip] } if {[llength $ip_name] && [string match -nocase $ip_name "gig_ethernet_pcs_pma"]} { set intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] "MDIO_ENET0"] set connected_pin "" set intf_nets "" if {[llength $intf_pins]} { set intf_nets [::hsi::get_intf_nets -of_objects $intf_pins] } if {[llength $intf_nets]} { set connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}] } set phyaddr_suffix "" if {[llength $connected_pin]} { set phyaddr_suffix [string trim $connected_pin "mdio_pcs_pma"] } set phyaddr "phyaddr" if {[llength $phyaddr_suffix]} { append phyaddr "_$phyaddr_suffix" } set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]] if {[llength $pin]} { set sink_periph [::hsi::get_cells -of_objects $pin] } if {[llength $sink_periph]} { set val [get_property CONFIG.CONST_VAL $sink_periph] set inhex [format %x $val] set_drv_prop $drv_handle phy-handle "phy$inhex" reference set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node] hsi::utils::add_new_dts_param "${pcspma_phy_node}" "reg" $val int set phy_type [get_property CONFIG.Standard $connected_ip] set is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip] if {$phy_type == "1000BASEX"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x5 int } elseif { $is_sgmii == "true"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x4 int } else { dtg_warning "unsupported phytype:$phy_type" } } } } if {[string match -nocase $node "&gem1"]} { set connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph "MDIO_ENET1"] if {[llength $connected_ip]} { set ip_name [get_property IP_NAME $connected_ip] } if {[llength $ip_name] && [string match -nocase $ip_name "gig_ethernet_pcs_pma"]} { set intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] "MDIO_ENET1"] set connected_pin "" set intf_nets "" if {[llength $intf_pins]} { set intf_nets [::hsi::get_intf_nets -of_objects $intf_pins] } if {[llength $intf_nets]} { set connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}] } set phyaddr_suffix "" if {[llength $connected_pin]} { set phyaddr_suffix [string trim $connected_pin "mdio_pcs_pma"] } set phyaddr "phyaddr" if {[llength $phyaddr_suffix]} { append phyaddr "_$phyaddr_suffix" } set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]] if {[llength $pin]} { set sink_periph [::hsi::get_cells -of_objects $pin] } if {[llength $sink_periph]} { set val [get_property CONFIG.CONST_VAL $sink_periph] set inhex [format %x $val] set_drv_prop $drv_handle phy-handle "phy$inhex" reference set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node] hsi::utils::add_new_dts_param "${pcspma_phy_node}" "reg" $val int set phy_type [get_property CONFIG.Standard $connected_ip] set is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip] if {$phy_type == "1000BASEX"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x5 int } elseif { $is_sgmii == "true"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x4 int } else { dtg_warning "unsupported phytype:$phy_type" } } } } if {[string match -nocase $node "&gem2"]} { set connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph "MDIO_ENET2"] if {[llength $connected_ip]} { set ip_name [get_property IP_NAME $connected_ip] } if {[llength $ip_name] && [string match -nocase $ip_name "gig_ethernet_pcs_pma"]} { set intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] "MDIO_ENET2"] set connected_pin "" set intf_nets "" if {[llength $intf_pins]} { set intf_nets [::hsi::get_intf_nets -of_objects $intf_pins] } if {[llength $intf_nets]} { set connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}] } set phyaddr_suffix "" if {[llength $connected_pin]} { set phyaddr_suffix [string trim $connected_pin "mdio_pcs_pma"] } set phyaddr "phyaddr" if {[llength $phyaddr_suffix]} { append phyaddr "_$phyaddr_suffix" } set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]] if {[llength $pin]} { set sink_periph [::hsi::get_cells -of_objects $pin] } if {[llength $sink_periph]} { set val [get_property CONFIG.CONST_VAL $sink_periph] set inhex [format %x $val] set_drv_prop $drv_handle phy-handle "phy$inhex" reference set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node] hsi::utils::add_new_dts_param "${pcspma_phy_node}" "reg" $val int set phy_type [get_property CONFIG.Standard $connected_ip] set is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip] if {$phy_type == "1000BASEX"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x5 int } elseif { $is_sgmii == "true"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x4 int } else { dtg_warning "unsupported phytype:$phy_type" } } } } if {[string match -nocase $node "&gem3"]} { set connected_ip [hsi::utils::get_connected_stream_ip $zynq_periph "MDIO_ENET3"] if {[llength $connected_ip]} { set ip_name [get_property IP_NAME $connected_ip] } if {[llength $ip_name] && [string match -nocase $ip_name "gig_ethernet_pcs_pma"]} { set intf_pins [::hsi::get_intf_pins -of_objects [get_cells $zynq_periph] "MDIO_ENET3"] set connected_pin "" set intf_nets "" if {[llength $intf_pins]} { set intf_nets [::hsi::get_intf_nets -of_objects $intf_pins] } if {[llength $intf_nets]} { set connected_pin [::hsi::get_intf_pins -of_objects $intf_nets -filter {TYPE==SLAVE || TYPE==TARGET}] } set phyaddr_suffix "" if {[llength $connected_pin]} { set phyaddr_suffix [string trim $connected_pin "mdio_pcs_pma"] } set phyaddr "phyaddr" if {[llength $phyaddr_suffix]} { append phyaddr "_$phyaddr_suffix" } set pin [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $connected_ip] $phyaddr]] if {[llength $pin]} { set sink_periph [::hsi::get_cells -of_objects $pin] } if {[llength $sink_periph]} { set val [get_property CONFIG.CONST_VAL $sink_periph] set inhex [format %x $val] set_drv_prop $drv_handle phy-handle "phy$inhex" reference set pcspma_phy_node [add_or_get_dt_node -l phy$inhex -n phy -u $inhex -p $node] hsi::utils::add_new_dts_param "${pcspma_phy_node}" "reg" $val int set phy_type [get_property CONFIG.Standard $connected_ip] set is_sgmii [get_property CONFIG.c_is_sgmii $connected_ip] if {$phy_type == "1000BASEX"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x5 int } elseif { $is_sgmii == "true"} { hsi::utils::add_new_dts_param "${pcspma_phy_node}" "xlnx,phy-type" 0x4 int } else { dtg_warning "unsupported phytype:$phy_type" } } } } } set is_pcspma [get_cells -hier -filter {IP_NAME == gig_ethernet_pcs_pma}] if {![string_is_empty ${is_pcspma}] && $phymode == 2} { # if eth mode is sgmii and no external pcs/pma found hsi::utils::add_new_property $drv_handle "is-internal-pcspma" boolean "" } } proc gen_mdio1_node {drv_handle parent_node} { set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return } set default_dts [get_property CONFIG.pcw_dts [get_os]] set mdio_node [add_or_get_dt_node -l ${drv_handle}_mdio -n mdio -d $default_dts -p $parent_node] hsi::utils::add_new_dts_param "${mdio_node}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${mdio_node}" "#size-cells" 0 int "" return $mdio_node } ================================================ FILE: ernic/data/ernic.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ernic OPTION supported_peripherals = (ernic); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ernic; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: ernic/data/ernic.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set proc_type [get_sw_proc_prop IP_NAME] set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set ernic_ip [get_cells -hier $drv_handle] set ip_name [get_property IP_NAME $ernic_ip] set ethip [get_connected_ip $drv_handle "rx_pkt_hndler_s_axis"] if {[llength $ethip]} { set_drv_property $drv_handle eth-handle "$ethip" reference } } proc get_connected_ip {drv_handle dma_pin} { global connected_ip set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin] set valid_eth_list "l_ethernet" if {[string_is_empty ${intf}]} { return 0 } set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf] if {[string_is_empty ${connected_ip}]} { dtg_warning "$drv_handle connected ip is NULL for the pin $intf" return 0 } set iptype [get_property IP_NAME [get_cells -hier $connected_ip]] if {[string match -nocase $iptype "axis_data_fifo"] } { set dma_pin "M_AXIS" get_connected_ip $connected_ip $dma_pin } elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } { return $connected_ip } else { set dma_pin "S_AXIS" get_connected_ip $connected_ip $dma_pin } } ================================================ FILE: framebuf_rd/data/framebuf_rd.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver framebuf_rd OPTION supported_peripherals = (v_frmbuf_rd); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = framebuf_rd; END driver ================================================ FILE: framebuf_rd/data/framebuf_rd.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-frmbuf-rd-v2.2"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set_drv_conf_prop $drv_handle C_S_AXI_CTRL_ADDR_WIDTH xlnx,s-axi-ctrl-addr-width set_drv_conf_prop $drv_handle C_S_AXI_CTRL_DATA_WIDTH xlnx,s-axi-ctrl-data-width set vid_formats "" set has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]] if {$has_bgr8 == 1} { append vid_formats " " "rgb888" } set has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]] if {$has_rgbx8 == 1} { append vid_formats " " "xbgr8888" } set has_bgra8 [get_property CONFIG.HAS_BGRA8 [get_cells -hier $drv_handle]] if {$has_bgra8 == 1} { append vid_formats " " "argb8888" } set has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]] if {$has_bgrx8 == 1} { append vid_formats " " "xrgb8888" } set has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]] if {$has_rgb8 == 1} { append vid_formats " " "bgr888" } set has_rgba8 [get_property CONFIG.HAS_RGBA8 [get_cells -hier $drv_handle]] if {$has_rgba8 == 1} { append vid_formats " " "abgr8888" } set has_bgrx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]] if {$has_bgrx10 == 1} { append vid_formats " " "xbgr2101010" } set has_uyvy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]] if {$has_uyvy8 == 1} { append vid_formats " " "uyvy" } set has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]] if {$has_y8 == 1} { append vid_formats " " "y8" } set has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]] if {$has_y10 == 1} { append vid_formats " " "y10" } set has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]] if {$has_yuv8 == 1} { append vid_formats " " "vuy888" } set has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]] if {$has_yuvx8 == 1} { append vid_formats " " "xvuy8888" } set has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]] if {$has_yuvx10 == 1} { append vid_formats " " "yuvx2101010" } set has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]] if {$has_yuyv8 == 1} { append vid_formats " " "yuyv" } set has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]] if {$has_y_uv8_420 == 1} { append vid_formats " " "nv12" } set has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]] if {$has_y_uv8 == 1} { append vid_formats " " "nv16" } set has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]] if {$has_y_uv10 == 1} { append vid_formats " " "xv20" } set has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]] if {$has_y_uv10_420 == 1} { append vid_formats " " "xv15" } set has_y_u_v8 [get_property CONFIG.HAS_Y_U_V8 [get_cells -hier $drv_handle]] if {$has_y_u_v8 == 1} { append vid_formats " " "y_u_v8" } if {![string match $vid_formats ""]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vid-formats" $vid_formats stringlist } set samples_per_clk [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,pixels-per-clock" $samples_per_clk int set dma_align [expr $samples_per_clk * 8] hsi::utils::add_new_dts_param "$node" "xlnx,dma-align" $dma_align int set has_interlaced [get_property CONFIG.HAS_INTERLACED [get_cells -hier $drv_handle]] if {$has_interlaced == 1} { hsi::utils::add_new_dts_param "$node" "xlnx,fid" "" boolean } set dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dma-addr-width" $dma_addr_width int hsi::utils::add_new_dts_param "$node" "#dma-cells" 1 int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,video-width" $max_data_width int set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-height" $max_rows int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-width" $max_cols int gen_gpio_reset $drv_handle $node } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: framebuf_wr/data/framebuf_wr.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver framebuf_wr OPTION supported_peripherals = (v_frmbuf_wr); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = framebuf_wr; END driver ================================================ FILE: framebuf_wr/data/framebuf_wr.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,axi-frmbuf-wr-v2.2"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set_drv_conf_prop $drv_handle C_S_AXI_CTRL_ADDR_WIDTH xlnx,s-axi-ctrl-addr-width set_drv_conf_prop $drv_handle C_S_AXI_CTRL_DATA_WIDTH xlnx,s-axi-ctrl-data-width set vid_formats "" set has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]] if {$has_bgr8 == 1} { append vid_formats " " "rgb888" } set has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]] if {$has_rgb8 == 1} { append vid_formats " " "bgr888" } set has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]] if {$has_rgbx8 == 1} { append vid_formats " " "xbgr8888" } set has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]] if {$has_bgrx8 == 1} { append vid_formats " " "xrgb8888" } set has_bgrx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]] if {$has_bgrx10 == 1} { append vid_formats " " "xbgr2101010" } set has_uyvy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]] if {$has_uyvy8 == 1} { append vid_formats " " "uyvy" } set has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]] if {$has_y8 == 1} { append vid_formats " " "y8" } set has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]] if {$has_y10 == 1} { append vid_formats " " "y10" } set has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]] if {$has_yuv8 == 1} { append vid_formats " " "vuy888" } set has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]] if {$has_yuvx8 == 1} { append vid_formats " " "xvuy8888" } set has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]] if {$has_yuvx10 == 1} { append vid_formats " " "yuvx2101010" } set has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]] if {$has_yuyv8 == 1} { append vid_formats " " "yuyv" } set has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]] if {$has_y_uv8_420 == 1} { append vid_formats " " "nv12" } set has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]] if {$has_y_uv8 == 1} { append vid_formats " " "nv16" } set has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]] if {$has_y_uv10 == 1} { append vid_formats " " "xv20" } set has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]] if {$has_y_uv10_420 == 1} { append vid_formats " " "xv15" } set has_y_u_v8 [get_property CONFIG.HAS_Y_U_V8 [get_cells -hier $drv_handle]] if {$has_y_u_v8 == 1} { append vid_formats " " "y_u_v8" } if {![string match $vid_formats ""]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vid-formats" $vid_formats stringlist } set samples_per_clk [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,pixels-per-clock" $samples_per_clk int set dma_align [expr $samples_per_clk * 8] hsi::utils::add_new_dts_param "$node" "xlnx,dma-align" $dma_align int set has_interlaced [get_property CONFIG.HAS_INTERLACED [get_cells -hier $drv_handle]] if {$has_interlaced == 1} { hsi::utils::add_new_dts_param "$node" "xlnx,fid" "" boolean } set dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dma-addr-width" $dma_addr_width int hsi::utils::add_new_dts_param "$node" "#dma-cells" 1 int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,video-width" $max_data_width int set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-height" $max_rows int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-width" $max_cols int gen_gpio_reset $drv_handle $node set frmbuf_inips [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] foreach inip $frmbuf_inips { if {[string match -nocase [get_property IP_NAME $inip] "v_mix"] } { set ports_node [add_or_get_dt_node -n "ports" -l frmbuf_wr_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port0_node [add_or_get_dt_node -n "port" -l frmbuf_wr$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int set frmbuf_crtc [add_or_get_dt_node -n "endpoint" -l v_frmbuf_wr$drv_handle -p $port0_node] hsi::utils::add_new_dts_param "$frmbuf_crtc" "remote-endpoint" "mixer_out$inip" reference } } } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: gamma_lut/data/gamma_lut.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver gamma_lut OPTION supported_peripherals = (v_gamma_lut); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = gamma_lut; END driver ================================================ FILE: gamma_lut/data/gamma_lut.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-gamma-lut"] set_drv_prop $drv_handle compatible "$compatible" stringlist set gamma_ip [get_cells -hier $drv_handle] set s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-addr-width" $s_axi_ctrl_addr_width int set s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-data-width" $s_axi_ctrl_data_width int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-height" $max_rows int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-width" $max_cols int set ports_node [add_or_get_dt_node -n "ports" -l gamma_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l gamma_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-width" $max_data_width int set gammaoutip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_video"] foreach outip $gammaoutip { if {[llength $outip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter { TYPE==MASTER || TYPE == INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set gammanode [add_or_get_dt_node -n "endpoint" -l gamma_out$drv_handle -p $port1_node] hsi::utils::add_new_dts_param "$gammanode" "remote-endpoint" $outip$drv_handle reference gen_endpoint $drv_handle "gamma_out$drv_handle" gen_remoteendpoint $drv_handle "$outip$drv_handle" if {[string match -nocase [get_property IP_NAME $outip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $outip $drv_handle } } else { if {[string match -nocase [get_property IP_NAME $outip] "system_ila"]} { continue } set connectip [get_connect_ip $outip $master_intf] if {[llength $connectip]} { set gammanode [add_or_get_dt_node -n "endpoint" -l gamma_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "gamma_out$drv_handle" hsi::utils::add_new_dts_param "$gammanode" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $connectip $drv_handle } } } } else { dtg_warning "$drv_handle pin m_axis_video is not connected..check your design" } } gen_gpio_reset $drv_handle $node } proc gen_frmbuf_wr_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" gamma_out$drv_handle reference } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] set proc_type [get_sw_proc_prop IP_NAME] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle: peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle: peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: generic/data/generic.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver generic OPTION NAME = generic; OPTION supported_os_types = (DTS); DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: generic/data/generic.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set hsi_version [get_hsi_version] set ver [split $hsi_version "."] set value [lindex $ver 0] if {$value >= 2018} { set generic_node [gen_peripheral_nodes $drv_handle] set last [string last "@" $generic_node] if {$last != -1} { hsi::utils::add_new_dts_param "${generic_node}" "/* This is a place holder node for a custom IP, user may need to update the entries */" "" comment } } } ================================================ FILE: globaltimerps/data/globaltimerps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver globaltimerps OPTION supported_peripherals = (ps7_globaltimer); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = globaltimerps; END driver ================================================ FILE: globaltimerps/data/globaltimerps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: gpiops/data/gpiops.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver gpiops OPTION supported_peripherals = (ps7_gpio psu_gpio psv_gpio); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = gpiops; DTGPARAM name = emio-gpio-width, type = int; DTGPARAM name = gpio-mask-high, type = hexint; DTGPARAM name = gpio-mask-low, type = hexint; END driver ================================================ FILE: gpiops/data/gpiops.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { set count 32 set ip [get_cells -hier $drv_handle] set_property CONFIG.emio-gpio-width "[hsi::utils::get_ip_param_value $ip C_EMIO_GPIO_WIDTH]" $drv_handle set gpiomask [hsi::utils::get_ip_param_value $ip "C_MIO_GPIO_MASK"] if {[llength $gpiomask]} { set mask [expr {$gpiomask & 0xffffffff}] set_property CONFIG.gpio-mask-low "$mask" $drv_handle set mask [expr {$gpiomask>>$count}] set mask [expr {$mask & 0xffffffff}] set_property CONFIG.gpio-mask-high "$mask" $drv_handle } } ================================================ FILE: hdmi_ctrl/data/hdmi_ctrl.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver hdmi_ctrl OPTION supported_peripherals = (hdmi_acr_ctrl); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = hdmi_ctrl; END driver ================================================ FILE: hdmi_ctrl/data/hdmi_ctrl.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,hdmi_act_ctrl"] set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: hdmi_gt_ctrl/data/hdmi_gt_ctrl.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver hdmi_gt_ctrl OPTION supported_peripherals = (hdmi_gt_controller); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = hdmi_gt_ctrl; END driver ================================================ FILE: hdmi_gt_ctrl/data/hdmi_gt_ctrl.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set err_irq_en [get_property CONFIG.C_Err_Irq_En [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,err-irq-en" $err_irq_en int set tx_frl_refclk_sel [get_property CONFIG.C_TX_FRL_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-frl-refclk-sel" $tx_frl_refclk_sel int set rx_frl_refclk_sel [get_property CONFIG.C_RX_FRL_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-frl-refclk-sel" $rx_frl_refclk_sel int set input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,input-pixels-per-clock" $input_pixels_per_clock int set nidru [get_property CONFIG.C_NIDRU [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,nidru" $nidru int set use_gt_ch4_hdmi [get_property CONFIG.C_Use_GT_CH4_HDMI [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,use-gt-ch4-hdmi" $use_gt_ch4_hdmi int set nidru_refclk_sel [get_property CONFIG.C_NIDRU_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,nidru-refclk-sel" $nidru_refclk_sel int set Rx_No_Of_Channels [get_property CONFIG.C_Rx_No_Of_Channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-no-of-channels" $Rx_No_Of_Channels int set rx_pll_selection [get_property CONFIG.C_RX_PLL_SELECTION [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-pll-selection" $rx_pll_selection int set rx_protocol [get_property CONFIG.C_Rx_Protocol [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-protocol" $rx_protocol int set rx_refclk_sel [get_property CONFIG.C_RX_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-refclk-sel" $rx_refclk_sel int set tx_pll_selection [get_property CONFIG.C_TX_PLL_SELECTION [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-pll-selection" $tx_pll_selection int set tx_protocol [get_property CONFIG.C_Tx_Protocol [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-protocol" $tx_protocol int set tx_refclk_sel [get_property CONFIG.C_TX_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-refclk-sel" $tx_refclk_sel int set tx_no_of_channels [get_property CONFIG.C_Tx_No_Of_Channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-no-of-channels" $tx_no_of_channels int set tx_buffer_bypass [get_property CONFIG.Tx_Buffer_Bypass [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-buffer-bypass" $tx_buffer_bypass int set transceiver_width [get_property CONFIG.Transceiver_Width [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-width" $transceiver_width int set hdmi_fast_switch [get_property CONFIG.C_Hdmi_Fast_Switch [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,hdmi-fast-switch" $hdmi_fast_switch int for {set ch 0} {$ch < $tx_no_of_channels} {incr ch} { set txpinname "tx_axi4s_ch$ch" set channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname] if {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} { set phy_node [add_or_get_dt_node -n "${txpinname}${channelip}" -l ${drv_handle}txphy_lane${ch} -p $node] hsi::utils::add_new_dts_param "$phy_node" "#phy-cells" 4 int } } set transceiver [get_property CONFIG.Transceiver [get_cells -hier $drv_handle]] switch $transceiver { "GTXE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 1 int } "GTHE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 2 int } "GTPE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 3 int } "GTHE3" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 4 int } "GTHE4" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 5 int } "GTYE4" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 6 int } "GTYE5" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 7 int } } set gt_direction [get_property CONFIG.C_GT_DIRECTION [get_cells -hier $drv_handle]] switch $gt_direction { "SIMPLEX_TX" { hsi::utils::add_new_dts_param "${node}" "xlnx,gt-direction" 1 int } "SIMPLEX_RX" { hsi::utils::add_new_dts_param "${node}" "xlnx,gt-direction" 2 int } "DUPLEX" { hsi::utils::add_new_dts_param "${node}" "xlnx,gt-direction" 3 int } } } ================================================ FILE: hdmi_rx_ss/data/hdmi_rx_ss.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver hdmi_rx_ss OPTION supported_peripherals = (v_hdmi_rx_ss v_hdmi_rxss1); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = hdmi_rx_ss; END driver ================================================ FILE: hdmi_rx_ss/data/hdmi_rx_ss.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-hdmi-rx-ss-3.1"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ports_node [add_or_get_dt_node -n "ports" -l hdmirx_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l hdmirx_port$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "${port_node}" "/* Fill the fields xlnx,video-format and xlnx,video-width based on user requirement */" "" comment hsi::utils::add_new_dts_param "$port_node" "xlnx,video-format" 0 int hsi::utils::add_new_dts_param "$port_node" "xlnx,video-width" 10 int hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set outip [get_connected_stream_ip [get_cells -hier $drv_handle] "VIDEO_OUT"] foreach ip $outip { if {[llength $ip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set hdmi_rx_node [add_or_get_dt_node -n "endpoint" -l hdmirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "hdmirx_out$drv_handle" hsi::utils::add_new_dts_param "$hdmi_rx_node" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle $ip$drv_handle if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"]} { gen_frmbuf_node $ip $drv_handle } } else { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set connectip [get_connect_ip $ip $master_intf] if {[llength $connectip]} { set hdmi_rx_node [add_or_get_dt_node -n "endpoint" -l hdmirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "hdmirx_out$drv_handle" hsi::utils::add_new_dts_param "$hdmi_rx_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle $connectip$drv_handle if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_node $connectip $drv_handle } } } } } set phy_names "" set phys "" set link_data0 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA0_IN"] if {[llength $link_data0]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data0] if {[llength $ip_mem_handles]} { set link_data0_inst $link_data0 set link_data0 [get_property IP_NAME $link_data0] if {[string match -nocase $link_data0 "vid_phy_controller"] || [string match -nocase $link_data0 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy0" append phys "${link_data0_inst}rxphy_lane0 0 1 1 0>," } } else { dtg_warning "connected stream of LINK_DATA0_IN is NULL...check the design" } } set link_data1 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA1_IN"] if {[llength $link_data1]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data1] if {[llength $ip_mem_handles]} { set link_data1_inst $link_data1 set link_data1 [get_property IP_NAME $link_data1] if {[string match -nocase $link_data1 "vid_phy_controller"] || [string match -nocase $link_data1 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy1" append phys " <&${link_data1_inst}rxphy_lane1 0 1 1 0>," } } else { dtg_warning "Connected stream of LINK_DATA1_IN is NULL...check the design" } } set link_data2 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA2_IN"] if {[llength $link_data2]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data2] if {[llength $ip_mem_handles]} { set link_data2_inst $link_data2 set link_data2 [get_property IP_NAME $link_data2] if {[string match -nocase $link_data2 "vid_phy_controller"] || [string match -nocase $link_data2 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy2" append phys " <&${link_data2_inst}rxphy_lane2 0 1 1 0" } } else { dtg_warning "Connected stream of LINK_DATA2_IN is NULL...check the design" } } set link_data3 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA3_IN"] if {[llength $link_data3]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data3] if {[llength $ip_mem_handles]} { set link_data3_inst $link_data3 set link_data3 [get_property IP_NAME $link_data3] if {[string match -nocase $link_data3 "vid_phy_controller"] || [string match -nocase $link_data3 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy3" append phys " <&${link_data3_inst}rxphy_lane3 0 1 1 0" } } else { dtg_warning "Connected stream of LINK_DATA3_IN is NULL...check the design" } } if {![string match -nocase $phy_names ""]} { hsi::utils::add_new_dts_param "$node" "phy-names" $phy_names stringlist } if {![string match -nocase $phys ""]} { hsi::utils::add_new_dts_param "$node" "phys" $phys reference } set input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,input-pixels-per-clock" $input_pixels_per_clock int set max_bits_per_component [get_property CONFIG.C_MAX_BITS_PER_COMPONENT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-bits-per-component" $max_bits_per_component int set edid_ram_size [get_property CONFIG.C_EDID_RAM_SIZE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,edid-ram-size" $edid_ram_size hexint set include_hdcp_1_4 [get_property CONFIG.C_INCLUDE_HDCP_1_4 [get_cells -hier $drv_handle]] if {[string match -nocase $include_hdcp_1_4 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,include-hdcp-1-4" "" boolean } set include_hdcp_2_2 [get_property CONFIG.C_INCLUDE_HDCP_2_2 [get_cells -hier $drv_handle]] if {[string match -nocase $include_hdcp_2_2 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,include-hdcp-2-2" "" boolean } set audio_out_connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "AUDIO_OUT"] if {[llength $audio_out_connect_ip] != 0} { set audio_out_connect_ip_type [get_property IP_NAME $audio_out_connect_ip] if {[string match -nocase $audio_out_connect_ip_type "axis_switch"]} { set connected_ip [hsi::utils::get_connected_stream_ip $audio_out_connect_ip "M00_AXIS"] if {[llength $connected_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enabled" "" boolean } } elseif {[string match -nocase $audio_out_connect_ip_type "audio_formatter"]} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $audio_out_connect_ip reference hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enabled" "" boolean } } else { dtg_warning "$drv_handle pin AUDIO_OUT is not connected... check your design" } } proc gen_frmbuf_node {ip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$ip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $ip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" hdmirx_out$drv_handle reference } ================================================ FILE: hdmi_tx_ss/data/hdmi_tx_ss.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver hdmi_tx_ss OPTION supported_peripherals = (v_hdmi_tx_ss v_hdmi_txss1); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = hdmi_tx_ss; END driver ================================================ FILE: hdmi_tx_ss/data/hdmi_tx_ss.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-hdmi-tx-ss-3.1"] set_drv_prop $drv_handle compatible "$compatible" stringlist set input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,input-pixels-per-clock" $input_pixels_per_clock int set max_bits_per_component [get_property CONFIG.C_MAX_BITS_PER_COMPONENT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-bits-per-component" $max_bits_per_component int set vid_interface [get_property CONFIG.C_VID_INTERFACE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,vid-interface" $vid_interface int set vtcip [get_cells -hier -filter {IP_NAME == "v_tc"}] set base_addr [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]] if {[llength $vtcip]} { generate_vtc_node $drv_handle $base_addr } set phy_names "" set phys "" set link_data0 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA0_OUT"] if {[llength $link_data0]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data0] if {[llength $ip_mem_handles]} { set link_data0_inst $link_data0 set link_data0 [get_property IP_NAME $link_data0] if {[string match -nocase $link_data0 "vid_phy_controller"] || [string match -nocase $link_data0 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy0" append phys "${link_data0_inst}txphy_lane0 0 1 1 1>," } } } else { dtg_warning "connected stream of LINK_DATA0_IN is NULL...check the design" } set link_data1 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA1_OUT"] if {[llength $link_data1]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data1] if {[llength $ip_mem_handles]} { set link_data1_inst $link_data1 set link_data1 [get_property IP_NAME $link_data1] if {[string match -nocase $link_data1 "vid_phy_controller"] || [string match -nocase $link_data1 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy1" append phys " <&${link_data1_inst}txphy_lane1 0 1 1 1>," } } } else { dtg_warning "Connected stream of LINK_DATA1_IN is NULL...check the design" } set link_data2 [get_connected_stream_ip [get_cells -hier $drv_handle] "LINK_DATA2_OUT"] if {[llength $link_data2]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $link_data2] if {[llength $ip_mem_handles]} { set link_data2_inst $link_data2 set link_data2 [get_property IP_NAME $link_data2] if {[string match -nocase $link_data2 "vid_phy_controller"] || [string match -nocase $link_data2 "hdmi_gt_controller"]} { append phy_names " " "hdmi-phy2" append phys " <&${link_data2_inst}txphy_lane2 0 1 1 1" } } } else { dtg_warning "Connected stream of LINK_DATA2_IN is NULL...check the design" } if {![string match -nocase $phy_names ""]} { hsi::utils::add_new_dts_param "$node" "phy-names" $phy_names stringlist } if {![string match -nocase $phys ""]} { hsi::utils::add_new_dts_param "$node" "phys" $phys reference } set include_hdcp_1_4 [get_property CONFIG.C_INCLUDE_HDCP_1_4 [get_cells -hier $drv_handle]] if {[string match -nocase $include_hdcp_1_4 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,include-hdcp-1-4" "" boolean } set include_hdcp_2_2 [get_property CONFIG.C_INCLUDE_HDCP_2_2 [get_cells -hier $drv_handle]] if {[string match -nocase $include_hdcp_2_2 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,include-hdcp-2-2" "" boolean } if {[string match -nocase $include_hdcp_1_4 "true"] || [string match -nocase $include_hdcp_2_2 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp-authenticate" 0x1 int hsi::utils::add_new_dts_param "${node}" "xlnx,hdcp-encrypt" 0x1 int } set audio_in_connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "AUDIO_IN"] if {[llength $audio_in_connect_ip] != 0} { set audio_in_connect_ip_type [get_property IP_NAME $audio_in_connect_ip] if {[string match -nocase $audio_in_connect_ip_type "axis_switch"]} { set connected_ip [hsi::utils::get_connected_stream_ip $audio_in_connect_ip "S00_AXIS"] if {[llength $connected_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enabled" "" boolean } } elseif {[string match -nocase $audio_in_connect_ip_type "audio_formatter"]} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $audio_in_connect_ip reference hsi::utils::add_new_dts_param "${node}" "xlnx,audio-enabled" "" boolean } } else { dtg_warning "$drv_handle pin AUDIO_IN is not connected... check your design" } set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "acr_cts"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { if {[string match -nocase "[get_property IP_NAME $sink_periph]" "hdmi_acr_ctrl"]} { hsi::utils::add_new_dts_param "$node" "xlnx,xlnx-hdmi-acr-ctrl" $sink_periph reference } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: i2s_receiver/data/i2s_receiver.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver i2s_receiver OPTION supported_peripherals = (i2s_receiver); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = i2s_receiver; END driver ================================================ FILE: i2s_receiver/data/i2s_receiver.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,i2s-receiver-1.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "M_AXIS_AUD"] if {![llength $connect_ip]} { dtg_warning "$drv_handle pin M_AXIS_AUD is not connected... check your design" } if {[llength $connect_ip]} { set connect_ip_type [get_property IP_NAME $connect_ip] if {[string match -nocase $connect_ip_type "axis_switch"]} { set connected_ip [hsi::utils::get_connected_stream_ip $connect_ip "M00_AXIS"] if {![llength $connected_ip]} { dtg_warning "$connect_ip pin M00_AXIS is not connected... check your design" } if {[llength $connected_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference } } elseif {[string match -nocase $connect_ip_type "audio_formatter"]} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connect_ip reference } } set dwidth [get_property CONFIG.C_DWIDTH [get_cells -hier $drv_handle]] if {[llength $dwidth]} { hsi::utils::add_new_dts_param "$node" "xlnx,dwidth" $dwidth hexint } set num_channels [get_property CONFIG.C_NUM_CHANNELS [get_cells -hier $drv_handle]] if {[llength $num_channels]} { hsi::utils::add_new_dts_param "$node" "xlnx,num-channels" $num_channels hexint } set depth [get_property CONFIG.C_DEPTH [get_cells -hier $drv_handle]] if {[llength $depth]} { hsi::utils::add_new_dts_param "$node" "xlnx,depth" $depth hexint } set ip [get_cells -hier $drv_handle] set freq "" set clk [get_pins -of_objects $ip "aud_mclk"] if {[llength $clk] } { set freq [get_property CLK_FREQ $clk] hsi::utils::add_new_dts_param $node "aud_mclk" "$freq" int } } ================================================ FILE: i2s_transmitter/data/i2s_transmitter.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver i2s_transmitter OPTION supported_peripherals = (i2s_transmitter); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = i2s_transmitter; END driver ================================================ FILE: i2s_transmitter/data/i2s_transmitter.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,i2s-transmitter-1.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_AUD"] if {![llength $connect_ip]} { dtg_warning "$drv_handle pin S_AXIS_AUD is not connected... check your design" } if {[llength $connect_ip]} { set connect_ip_type [get_property IP_NAME $connect_ip] if {[string match -nocase $connect_ip_type "axis_switch"]} { set connected_ip [hsi::utils::get_connected_stream_ip $connect_ip "S00_AXIS"] if {![llength $connected_ip]} { dtg_warning "$connect_ip pin S00_AXIS is not connected... check your design" } if {[llength $connected_ip] != 0} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference } } elseif {[string match -nocase $connect_ip_type "audio_formatter"]} { hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connect_ip reference } } set dwidth [get_property CONFIG.C_DWIDTH [get_cells -hier $drv_handle]] if {[llength $dwidth]} { hsi::utils::add_new_dts_param "$node" "xlnx,dwidth" $dwidth hexint } set num_channels [get_property CONFIG.C_NUM_CHANNELS [get_cells -hier $drv_handle]] if {[llength $num_channels]} { hsi::utils::add_new_dts_param "$node" "xlnx,num-channels" $num_channels hexint } set depth [get_property CONFIG.C_DEPTH [get_cells -hier $drv_handle]] if {[llength $depth]} { hsi::utils::add_new_dts_param "$node" "xlnx,depth" $depth hexint } set ip [get_cells -hier $drv_handle] set freq "" set clk [get_pins -of_objects $ip "aud_mclk"] if {[llength $clk] } { set freq [get_property CLK_FREQ $clk] hsi::utils::add_new_dts_param $node "aud_mclk" "$freq" int } } ================================================ FILE: i3cpsx/data/i3cpsx.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver i3cpsx OPTION supported_peripherals = (psx_i3c); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = i3cpsx; DTGPARAM name = clock-frequency, type = int , default = 400000; END driver ================================================ FILE: i3cpsx/data/i3cpsx.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } } ================================================ FILE: iicps/data/iicps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver iicps OPTION supported_peripherals = (ps7_i2c psu_i2c psv_i2c psx_i2c); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = iicps; DTGPARAM name = dtg.alias , type = reference, default = i2c; END driver ================================================ FILE: iicps/data/iicps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } ps7_reset_handle $drv_handle CONFIG.C_I2C_RESET CONFIG.i2c-reset } ================================================ FILE: intc/data/intc.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver intc OPTION DRC = intc_drc; OPTION supported_peripherals = (axi_intc); OPTION supported_os_types = (DTS); OPTION NAME = intc; PARAMETER name = dev_type, default = "interrupt-controller", type = string; DTGPARAM name = "#interrupt-cells", default = 2, type = int; DTGPARAM name = interrupt-controller, type = boolean; DTGPARAM name = compatible, type =stringlist, default = "xlnx,xps-intc-1.00.a" ; DTGPARAM name = "xlnx,kind-of-intr", type = hexint, default = 0x0 ; END driver ================================================ FILE: intc/data/intc.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set zocl [get_property CONFIG.dt_zocl [get_os]] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-intc-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set num_intr_inputs [hsi::utils::get_ip_param_value $ip C_NUM_INTR_INPUTS] set kind_of_intr [hsi::utils::get_ip_param_value $ip C_KIND_OF_INTR] # Pad to 32 bits - num_intr_inputs if { $num_intr_inputs != -1 } { set count 0 set par_mask 0 for { set count 0 } { $count < $num_intr_inputs} { incr count} { set mask [expr {1<<$count}] set new_mask [expr {$mask | $par_mask}] set par_mask $new_mask } set kind_of_intr_32 $kind_of_intr set kind_of_intr [expr {$kind_of_intr_32 & $par_mask}] } else { set kind_of_intr 0 } set_property CONFIG.xlnx,kind-of-intr $kind_of_intr $drv_handle if {$zocl} { set num_intr_inputs "0x20" set_drv_prop $drv_handle "xlnx,num-intr-inputs" $num_intr_inputs int } else { set_drv_conf_prop $drv_handle C_NUM_INTR_INPUTS "xlnx,num-intr-inputs" } } ================================================ FILE: isppipeline/data/ispipeline.mdd ================================================ # # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ispipeline OPTION supported_peripherals = (ISPPipeline_accel); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ispipeline; END driver ================================================ FILE: isppipeline/data/ispipeline.tcl ================================================ # # (C) Copyright 2023 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc gen_reset_gpio {drv_handle node} { set ip [get_cells -hier $drv_handle] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$sink_periph 0 1" reference } if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As in versal there is only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 0" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 0" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference } } else { dtg_warning "periph for the pin:$pin is NULL $periph...check the design" } } } } else { dtg_warning "peripheral for the pin:$pin is NULL $sink_periph...check the design" } } } proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,isppipeline-1.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist hsi::utils::add_new_dts_param $node "xlnx,max-height" "/bits/ 16 <2160>" noformating hsi::utils::add_new_dts_param $node "xlnx,max-width" "/bits/ 16 <3840>" noformating hsi::utils::add_new_dts_param $node "xlnx,rgain" "/bits/ 16 <128>" noformating hsi::utils::add_new_dts_param $node "xlnx,bgain" "/bits/ 16 <210>" noformating hsi::utils::add_new_dts_param $node "xlnx,pawb" "/bits/ 16 <350>" noformating hsi::utils::add_new_dts_param $node "xlnx,mode-reg" "" boolean gen_reset_gpio "$drv_handle" "$node" # generating ports node for ispipeline ip set isppipeline_ports_node [add_or_get_dt_node -n "ports" -l isppipeline_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$isppipeline_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$isppipeline_ports_node" "#size-cells" 0 int # find input ip which is connected to s_axis_video set inip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] if {[llength $inip]} { if {[string match -nocase [get_property IP_NAME $inip] "axis_subset_converter"]} { set inip [get_connected_stream_ip [get_cells -hier $inip] "S_AXIS"] } if {[string match -nocase [get_property IP_NAME $inip] "axis_data_fifo"]} { set inip [get_connected_stream_ip [get_cells -hier $inip] "S_AXIS"] } # generating port0 node for ispipeline ip set port0_node [add_or_get_dt_node -n "port" -l isppipeline_port0$drv_handle -u 0 -p $isppipeline_ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int set isppipeline_port_node_endpoint [add_or_get_dt_node -n "endpoint" -l $drv_handle$inip -p $port0_node] hsi::utils::add_new_dts_param "$isppipeline_port_node_endpoint" "remote-endpoint" isppipeline_in$drv_handle reference } # find scanoutip which is connected to m_axis_video set scanoutip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_video"] set port1_node [add_or_get_dt_node -n "port" -l isppipeline_port1$drv_handle -u 1 -p $isppipeline_ports_node] hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int if {[llength $scanoutip]} { # generating port1 node for ispipeline ip if {[string match -nocase [get_property IP_NAME $scanoutip] "axis_broadcaster"]} { set port1_node_endpoint [add_or_get_dt_node -n "endpoint" -l $drv_handle$scanoutip -p $port1_node] gen_endpoint $drv_handle "$drv_handle$scanoutip" hsi::utils::add_new_dts_param "$port1_node_endpoint" "remote-endpoint" $scanoutip$drv_handle reference gen_remoteendpoint $drv_handle "$scanoutip$drv_handle" } if {[string match -nocase [get_property IP_NAME $scanoutip] "axis_switch"]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $scanoutip] if {[llength $ip_mem_handles]} { set port1_node_endpoint [add_or_get_dt_node -n "endpoint" -l $drv_handle$scanoutip -p $port1_node] gen_axis_switch_in_endpoint $drv_handle "$drv_handle$scanoutip" hsi::utils::add_new_dts_param "$port1_node_endpoint" "remote-endpoint" $scanoutip$drv_handle reference gen_axis_switch_in_remo_endpoint $drv_handle "$scanoutip$drv_handle" } } } foreach outip $scanoutip { if {[llength $outip]} { if {[string match -nocase [get_property IP_NAME $outip] "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip] if {[llength $ip_mem_handles]} { set port1_node_endpoint [add_or_get_dt_node -n "endpoint" -l $drv_handle$outip -p $port1_node] if {[string match -nocase [get_property IP_NAME $outip] "v_proc_ss"]} { # generating remote-endpoint only when it is connected to v_proc_ss ip hsi::utils::add_new_dts_param "$port1_node_endpoint" "remote-endpoint" "v_proc_ss$drv_handle" reference } else { gen_endpoint $drv_handle "$drv_handle$outip" hsi::utils::add_new_dts_param "$port1_node_endpoint" "remote-endpoint" $outip$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } } else { set connectip [get_connect_ip $outip $master_intf] if {[llength $connectip]} { set port1_node_endpoint [add_or_get_dt_node -n "endpoint" -l ispipeline_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "$drv_handle$outip" hsi::utils::add_new_dts_param "$port1_node_endpoint" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" } } } else { dtg_warning "$drv_handle pin m_axis_video is not connected..check your design" } } } ================================================ FILE: mig_7series/data/mig_7series.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver mig_7series OPTION supported_peripherals = (mig_7series ddr4 ddr3); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = mig_7series; END driver ================================================ FILE: mig_7series/data/mig_7series.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set remove_pl [get_property CONFIG.remove_pl [get_os]] if {[is_pl_ip $drv_handle] && $remove_pl} { return 0 } set ddr_ip "" set slave [get_cells -hier ${drv_handle}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $slave] set main_memory [get_property CONFIG.main_memory [get_os]] if {![string match -nocase $main_memory "none"]} { set ddr_ip [get_property IP_NAME [get_cells -hier -nocase $main_memory]] } set drv_ip [get_property IP_NAME [get_cells -hier $drv_handle]] if {[regexp $drv_ip $ddr_ip match]} { set master_dts [get_property CONFIG.master_dts [get_os]] set cur_dts [current_dt_tree] set master_dts_obj [get_dt_trees ${master_dts}] set_cur_working_dts $master_dts set parent_node [add_or_get_dt_node -n / -d ${master_dts}] set addr [get_property CONFIG.C0_DDR4_MEMORY_MAP_BASEADDR [get_cells -hier $drv_handle]] set base [get_property CONFIG.C0_DDR4_MEMORY_MAP_BASEADDR [get_cells -hier $drv_handle]] set high [get_property CONFIG.C0_DDR4_MEMORY_MAP_HIGHADDR [get_cells -hier $drv_handle]] if {![llength $addr]} { set addr [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]] } regsub -all {^0x} $addr {} addr set memory_node [add_or_get_dt_node -n memory -u $addr -p $parent_node] if {![llength $base]} { set base [get_property CONFIG.C_BASEADDR [get_cells -hier $drv_handle]] } if {![llength $high]} { set high [get_property CONFIG.C_HIGHADDR [get_cells -hier $drv_handle]] } set size [format 0x%x [expr {${high} - ${base} + 1}]] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } } else { set reg "0x0 $base 0x0 $size" } } else { set reg "$base $size" } hsi::utils::add_new_dts_param "${memory_node}" "reg" $reg inthexlist if {[catch {set dev_type [get_property CONFIG.device_type $drv_handle]} msg]} { set dev_type memory } if {[string_is_empty $dev_type]} {set dev_type memory} hsi::utils::add_new_dts_param "${memory_node}" "device_type" $dev_type string } set ip_mem_handle [lindex [hsi::utils::get_ip_mem_ranges [get_cells -hier $slave]] 0] set addr [string tolower [get_property BASE_VALUE $ip_mem_handle]] set base [string tolower [get_property BASE_VALUE $ip_mem_handle]] set high [string tolower [get_property HIGH_VALUE $ip_mem_handle]] set size [format 0x%x [expr {${high} - ${base} + 1}]] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "psu_cortexa53"]} { if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] if {[regexp -nocase {0x([0-9a-f]{9})} "$size" match]} { set temp $size set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_size "0x[string range $temp $rem $len]" set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_size [format 0x%08x $low_size] set reg "$low_base $high_base $low_size $high_size" } else { set reg "$low_base $high_base 0x0 $size" } } else { set reg "0x0 $base 0x0 $size" } } else { set reg "$base $size" } set_drv_prop_if_empty $drv_handle reg $reg intlist } ================================================ FILE: mipi_csi2_rx/data/mipi_csi2_rx.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver mipi_csi2_rx OPTION supported_peripherals = (mipi_csi2_rx_subsystem); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = mipi_csi2_rx; END driver ================================================ FILE: mipi_csi2_rx/data/mipi_csi2_rx.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,mipi-csi2-rx-subsystem-5.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dphy_en_reg_if [get_property CONFIG.DPY_EN_REG_IF [get_cells -hier $drv_handle]] if {[string match -nocase $dphy_en_reg_if "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,dphy-present" "" boolean } set en_vcx [get_property CONFIG.C_EN_VCX [get_cells -hier $drv_handle]] if {[string match -nocase $en_vcx "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,en-vcx" "" boolean } set en_csi_v2_0 [get_property CONFIG.C_EN_CSI_V2_0 [get_cells -hier $drv_handle]] if {[string match -nocase $en_csi_v2_0 "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,en-csi-v2-0" "" boolean } set dphy_lanes [get_property CONFIG.C_DPHY_LANES [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-lanes" $dphy_lanes int for {set lane 1} {$lane <= $dphy_lanes} {incr lane} { lappend lanes $lane } set en_csi_v2_0 [get_property CONFIG.C_EN_CSI_V2_0 [get_cells -hier $drv_handle]] set en_vcx [get_property CONFIG.C_EN_VCX [get_cells -hier $drv_handle]] set cmn_vc [get_property CONFIG.CMN_VC [get_cells -hier $drv_handle]] if {$en_csi_v2_0 == true && $en_vcx == true && [string match -nocase $cmn_vc "ALL"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vc" 16 int } elseif {$en_csi_v2_0 == true && $en_vcx == false && [string match -nocase $cmn_vc "ALL"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vc" 4 int } elseif {$en_csi_v2_0 == false && [string match -nocase $cmn_vc "ALL"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vc" 4 int } if {[llength $en_csi_v2_0] == 0} { hsi::utils::add_new_dts_param "${node}" "xlnx,vc" $cmn_vc int } set cmn_pxl_format [get_property CONFIG.CMN_PXL_FORMAT [get_cells -hier $drv_handle]] gen_pixel_format $node $cmn_pxl_format set csi_en_activelanes [get_property CONFIG.C_CSI_EN_ACTIVELANES [get_cells -hier $drv_handle]] if {[string match -nocase $csi_en_activelanes "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,en-active-lanes" "" boolean } set cmn_inc_vfb [get_property CONFIG.CMN_INC_VFB [get_cells -hier $drv_handle]] if {[string match -nocase $cmn_inc_vfb "true"]} { hsi::utils::add_new_dts_param "${node}" "xlnx,vfb" "" boolean } set cmn_num_pixels [get_property CONFIG.CMN_NUM_PIXELS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,ppc" "$cmn_num_pixels" int set axis_tdata_width [get_property CONFIG.AXIS_TDATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,axis-tdata-width" "$axis_tdata_width" int set ports_node [add_or_get_dt_node -n "ports" -l mipi_csi_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l mipi_csi_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port_node" "reg" 1 int set port0_node [add_or_get_dt_node -n "port" -l mipi_csi_port0$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$port0_node" "reg" 0 int hsi::utils::add_new_dts_param "${port0_node}" "/* User need to add something like remote-endpoint=<&out> under the node csiss_in:endpoint */" "" comment set csiss_rx_node [add_or_get_dt_node -n "endpoint" -l mipi_csi_in$drv_handle -p $port0_node] if {[llength $lanes]} { hsi::utils::add_new_dts_param "${csiss_rx_node}" "data-lanes" $lanes int } set outip [get_connected_stream_ip [get_cells -hier $drv_handle] "VIDEO_OUT"] if {[llength $outip]} { if {[string match -nocase [get_property IP_NAME $outip] "axis_broadcaster"]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l mipi_csirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "mipi_csirx_out$drv_handle" hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $outip$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } if {[string match -nocase [get_property IP_NAME $outip] "axis_switch"]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip] if {[llength $ip_mem_handles]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l mipi_csirx_out$drv_handle -p $port_node] gen_axis_switch_in_endpoint $drv_handle "mipi_csirx_out$drv_handle" hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $outip$drv_handle reference gen_axis_switch_in_remo_endpoint $drv_handle "$outip$drv_handle" } } } foreach ip $outip { if {[llength $ip]} { set intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set csi_rx_node [add_or_get_dt_node -n "endpoint" -l mipi_csirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "mipi_csirx_out$drv_handle" hsi::utils::add_new_dts_param "$csi_rx_node" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle $ip$drv_handle if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"]} { gen_frmbuf_node $ip $drv_handle } } else { set connectip [get_connect_ip $ip $intfpins] if {[llength $connectip]} { if {[string match -nocase [get_property IP_NAME $connectip] "axis_switch"]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {[llength $ip_mem_handles]} { set mipi_node [add_or_get_dt_node -n "endpoint" -l mipi_csirx_out$drv_handle -p $port_node] gen_axis_switch_in_endpoint $drv_handle "mipi_csirx_out$drv_handle" hsi::utils::add_new_dts_param "$mipi_node" "remote-endpoint" $connectip$drv_handle reference gen_axis_switch_in_remo_endpoint $drv_handle "$connectip$drv_handle" } } elseif {[string match -nocase [get_property IP_NAME $connectip] "ISPPipeline_accel"]} { set isppipeline_node [add_or_get_dt_node -n "endpoint" -l isppipeline_in$connectip -p $port_node] hsi::utils::add_new_dts_param "$isppipeline_node" "remote-endpoint" $connectip$drv_handle reference } else { set csi_rx_node [add_or_get_dt_node -n "endpoint" -l mipi_csirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "mipi_csirx_out$drv_handle" hsi::utils::add_new_dts_param "$csi_rx_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle $connectip$drv_handle if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_node $connectip $drv_handle } } } } } } gen_gpio_reset $drv_handle $node } proc gen_pixel_format {node pxl_format} { set pixel_format "" switch $pxl_format { "YUV422_8bit" { set pixel_format 0x18 } "YUV422_10bit" { set pixel_format 0x1f } "RGB444" { set pixel_format 0x20 } "RGB555" { set pixel_format 0x21 } "RGB565" { set pixel_format 0x22 } "RGB666" { set pixel_format 0x23 } "RGB888" { set pixel_format 0x24 } "RAW6" { set pixel_format 0x28 } "RAW7" { set pixel_format 0x29 } "RAW8" { set pixel_format 0x2a } "RAW10" { set pixel_format 0x2b } "RAW12" { set pixel_format 0x2c } "RAW14" { set pixel_format 0x2d } "RAW16" { set pixel_format 0x2e } "RAW20" { set pixel_format 0x2f } } if {[llength $pixel_format]} { hsi::utils::add_new_dts_param "${node}" "xlnx,csi-pxl-format" $pixel_format hex } } proc gen_frmbuf_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" mipi_csirx_out$drv_handle reference } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "video_aresetn"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "video-reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "video-reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "video-reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $periph" } } } else { # If no axi-slice connected b/w axi_gpio and reset pin # add video-reset-gpios property with gpio number 0 if {[string match -nocase $sink_ip "axi_gpio"]} { set gpio "0" set periph [::hsi::get_cells -of_objects $pin] if {[llength $gpio]} { hsi::utils::add_new_dts_param "$node" "video-reset-gpios" "$periph $gpio 1" reference } } } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: mipi_dsi_tx/data/mipi_dsi_tx.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver mipi_dsi_tx OPTION supported_peripherals = (mipi_dsi_tx_subsystem); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = mipi_dsi_tx; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: mipi_dsi_tx/data/mipi_dsi_tx.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,dsi"] set_drv_prop $drv_handle compatible "$compatible" stringlist set dsi_num_lanes [get_property CONFIG.DSI_LANES [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dsi-num-lanes" $dsi_num_lanes int set dsi_pixels_perbeat [get_property CONFIG.DSI_PIXELS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dsi-pixels-perbeat" $dsi_pixels_perbeat int set dsi_datatype [get_property CONFIG.DSI_DATATYPE [get_cells -hier $drv_handle]] if {[string match -nocase $dsi_datatype "RGB888"]} { hsi::utils::add_new_dts_param "$node" "xlnx,dsi-data-type" 0 int } elseif {[string match -nocase $dsi_datatype "RGB666_L"]} { hsi::utils::add_new_dts_param "$node" "xlnx,dsi-data-type" 1 int } elseif {[string match -nocase $dsi_datatype "RGB666_P"]} { hsi::utils::add_new_dts_param "$node" "xlnx,dsi-data-type" 2 int } elseif {[string match -nocase $dsi_datatype "RGB565"]} { hsi::utils::add_new_dts_param "$node" "xlnx,dsi-data-type" 3 int } set panel_node [add_or_get_dt_node -n "simple_panel" -l simple_panel$drv_handle -u 0 -p $node] hsi::utils::add_new_dts_param "${panel_node}" "/* User needs to add the panel node based on their requirement */" "" comment hsi::utils::add_new_dts_param "$panel_node" "reg" 0 int hsi::utils::add_new_dts_param "$panel_node" "compatible" "auo,b101uan01" string } ================================================ FILE: mixer/data/mixer.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver mixer OPTION supported_peripherals = (v_mix); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = mixer; END driver ================================================ FILE: mixer/data/mixer.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022-2024-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,mixer-3.0 xlnx,mixer-4.0 xlnx,mixer-5.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set mixer_ip [get_cells -hier $drv_handle] set num_layers [get_property CONFIG.NR_LAYERS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,num-layers" $num_layers int set samples_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,ppc" $samples_per_clock int set dma_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dma-addr-width" $dma_addr_width int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,bpc" $max_data_width int set logo_layer [get_property CONFIG.LOGO_LAYER [get_cells -hier $drv_handle]] if {[string match -nocase $logo_layer "true"]} { hsi::utils::add_new_dts_param "$node" "xlnx,logo-layer" "" boolean } set vtcip [get_cells -hier -filter {IP_NAME == "v_tc"}] set mix_outip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_video"] if {![llength $mix_outip]} { dtg_warning "$drv_handle pin m_axis_video is not connected ...check your design" } set enable_csc_coefficient_registers [get_property CONFIG.ENABLE_CSC_COEFFICIENT_REGISTERS [get_cells -hier $drv_handle]] if {$enable_csc_coefficient_registers == 1} { hsi::utils::add_new_dts_param "$node" "xlnx,enable-csc-coefficient-register" "" boolean } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $mix_outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] foreach outip $mix_outip { if {[llength $outip] != 0} { if {[string match -nocase [get_property IP_NAME $outip] "v_hdmi_tx_ss"] || [string match -nocase [get_property IP_NAME $outip] "v_hdmi_txss1"]} { if {[llength $vtcip]} { # Adding bridge param when v_tc ip connected as subcore # in the subsystem core by appending subsystem name. hsi::utils::add_new_dts_param "${node}" "xlnx,bridge" "v_tc_$outip" reference } } if {![string match -nocase [get_property IP_NAME $outip] "v_frmbuf_wr"]} { set mixer_port_node [add_or_get_dt_node -n "port" -l crtc_mixer_port$drv_handle -u 0 -p $node] hsi::utils::add_new_dts_param "$mixer_port_node" "reg" 0 int set mixer_crtc [add_or_get_dt_node -n "endpoint" -l mixer_crtc$drv_handle -p $mixer_port_node] } else { set ports_node [add_or_get_dt_node -n "ports" -l crtc_mixer_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set mixer_port0 [add_or_get_dt_node -n "port" -l crtc_mixer_port$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "$mixer_port0" "reg" 0 int set mixer0_endpoint [add_or_get_dt_node -n "endpoint" -l mixer_crtc$drv_handle -p $mixer_port0] set mixer_port1 [add_or_get_dt_node -n "port" -l crtc_mixer_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$mixer_port1" "reg" 1 int set mixer1_endpoint [add_or_get_dt_node -n "endpoint" -l mixer_out$drv_handle -p $mixer_port1] } set ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip] if {[llength $ip_mem_handles]} { gen_endpoint $drv_handle "mixer_crtc$drv_handle" if {[string match -nocase [get_property IP_NAME $outip] "v_dp_txss1"]} { hsi::utils::add_new_dts_param "$mixer_crtc" "remote-endpoint" "dptx_out$outip" reference gen_remoteendpoint $drv_handle "dptx_out$outip" } elseif {[string match -nocase [get_property IP_NAME $outip] "v_frmbuf_wr"]} { set mix_inip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] if {[llength $mix_inip]} { hsi::utils::add_new_dts_param "$mixer0_endpoint" "remote-endpoint" "sca_out$mix_inip" reference } hsi::utils::add_new_dts_param "$mixer1_endpoint" "remote-endpoint" "v_frmbuf_wr$outip" reference } else { hsi::utils::add_new_dts_param "$mixer_crtc" "remote-endpoint" $outip$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } } else { if {[string match -nocase [get_property IP_NAME $outip] "system_ila"]} { continue } set connectip [get_connect_ip $outip $master_intf] if {[llength $connectip]} { if {[string match -nocase [get_property IP_NAME $connectip] "v_hdmi_tx_ss"] || [string match -nocase [get_property IP_NAME $connectip] "v_hdmi_txss1"]} { if {[llength $vtcip]} { # Adding bridge param when v_tc ip connected as subcore # in the subsystem core by appending subsystem name. hsi::utils::add_new_dts_param "${node}" "xlnx,bridge" "v_tc_$connectip" reference } } gen_endpoint $drv_handle "mixer_crtc$drv_handle" if {[string match -nocase [get_property IP_NAME $outip] "v_dp_txss1"]} { hsi::utils::add_new_dts_param "$mixer_crtc" "remote-endpoint" "dptx_out$outip" reference gen_remoteendpoint $drv_handle "dptx_out$outip" } else { hsi::utils::add_new_dts_param "$mixer_crtc" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" } } } } else { dtg_warning "$drv_handle pin m_axis_video is not connected ...check your design" } } for {set layer 0} {$layer < $num_layers} {incr layer} { switch $layer { "0" { set mixer_node0 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_master$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-id" $layer int set maxwidth [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-max-width" $maxwidth int set maxheight [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-max-height" $maxheight int hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-primary" "" boolean set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video"] foreach connected_ip $connect_ip { if {[llength $connected_ip] != 0} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node0 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node0 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-streaming" "" boolean } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node0 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node0 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-streaming" "" boolean } } } set layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width } "1" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer1_alpha [get_property CONFIG.LAYER1_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer1_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer1_maxwidth [get_property CONFIG.LAYER1_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer1_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video1"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER1_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer1_video_format [get_property CONFIG.LAYER1_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer1_video_format $mixer_node1 $drv_handle $max_data_width } "2" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer2_alpha [get_property CONFIG.LAYER2_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer2_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer2_maxwidth [get_property CONFIG.LAYER2_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer2_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video2"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER2_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer2_video_format [get_property CONFIG.LAYER2_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer2_video_format $mixer_node1 $drv_handle $max_data_width } "3" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer3_alpha [get_property CONFIG.LAYER3_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer3_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer3_maxwidth [get_property CONFIG.LAYER3_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer3_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video3"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER3_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer3_video_format [get_property CONFIG.LAYER3_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer3_video_format $mixer_node1 $drv_handle $max_data_width } "4" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer4_alpha [get_property CONFIG.LAYER4_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer4_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer4_maxwidth [get_property CONFIG.LAYER4_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer4_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video4"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER4_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer4_video_format [get_property CONFIG.LAYER4_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer4_video_format $mixer_node1 $drv_handle $max_data_width } "5" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer5_alpha [get_property CONFIG.LAYER5_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer5_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer5_maxwidth [get_property CONFIG.LAYER5_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer5_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video5"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node0 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node0 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-streaming" "" boolean set layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER5_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer5_video_format [get_property CONFIG.LAYER5_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer5_video_format $mixer_node1 $drv_handle $max_data_width } "6" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer6_alpha [get_property CONFIG.LAYER6_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer6_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer6_maxwidth [get_property CONFIG.LAYER6_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer6_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video6"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_ip] if {[llength $ip_mem_handles]} { hsi::utils::add_new_dts_param $mixer_node0 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node0 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node0" "xlnx,layer-streaming" "" boolean set layer0_video_format [get_property CONFIG.VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer0_video_format $mixer_node0 $drv_handle $max_data_width } else { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_ip] -filter {TYPE==SLAVE || TYPE ==TARGET}] set inip [get_in_connect_ip $connected_ip $master_intf] if {[llength $inip]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$inip 0" reference } hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER6_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer6_video_format [get_property CONFIG.LAYER6_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer6_video_format $mixer_node1 $drv_handle $max_data_width } "7" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer7_alpha [get_property CONFIG.LAYER7_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer7_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer7_maxwidth [get_property CONFIG.LAYER7_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer7_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video7"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER7_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer7_video_format [get_property CONFIG.LAYER7_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer7_video_format $mixer_node1 $drv_handle $max_data_width } "8" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer8_alpha [get_property CONFIG.LAYER8_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer8_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer8_maxwidth [get_property CONFIG.LAYER8_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer8_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video8"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER8_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer8_video_format [get_property CONFIG.LAYER8_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer8_video_format $mixer_node1 $drv_handle $max_data_width } "9" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer9_alpha [get_property CONFIG.LAYER9_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer9_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer9_maxwidth [get_property CONFIG.LAYER9_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer9_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video9"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER9_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer9_video_format [get_property CONFIG.LAYER9_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer9_video_format $mixer_node1 $drv_handle $max_data_width } "10" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer10_alpha [get_property CONFIG.LAYER10_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer10_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer10_maxwidth [get_property CONFIG.LAYER10_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer10_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video10"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER10_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer10_video_format [get_property CONFIG.LAYER10_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer10_video_format $mixer_node1 $drv_handle $max_data_width } "11" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer11_alpha [get_property CONFIG.LAYER11_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer11_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer11_maxwidth [get_property CONFIG.LAYER11_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer11_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video11"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER11_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer11_video_format [get_property CONFIG.LAYER11_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer11_video_format $mixer_node1 $drv_handle $max_data_width } "12" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer12_alpha [get_property CONFIG.LAYER12_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer12_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer12_maxwidth [get_property CONFIG.LAYER12_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer12_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video12"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER12_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer12_video_format [get_property CONFIG.LAYER12_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer12_video_format $mixer_node1 $drv_handle $max_data_width } "13" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer13_alpha [get_property CONFIG.LAYER13_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer13_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer13_maxwidth [get_property CONFIG.LAYER13_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer13_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video13"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER13_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer13_video_format [get_property CONFIG.LAYER13_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer13_video_format $mixer_node1 $drv_handle $max_data_width } "14" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer14_alpha [get_property CONFIG.LAYER14_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer14_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer14_maxwidth [get_property CONFIG.LAYER14_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer14_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video14"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER14_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer14_video_format [get_property CONFIG.LAYER14_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer14_video_format $mixer_node1 $drv_handle $max_data_width } "15" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer15_alpha [get_property CONFIG.LAYER15_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer15_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer15_maxwidth [get_property CONFIG.LAYER15_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer15_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video15"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "v_frmbuf_rd"]} { hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } } set sample [get_property CONFIG.LAYER15_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer15_video_format [get_property CONFIG.LAYER15_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer15_video_format $mixer_node1 $drv_handle $max_data_width } "16" { set mixer_node1 [add_or_get_dt_node -n "layer_$layer" -l xx_mix_overlay_$layer$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set layer16_alpha [get_property CONFIG.LAYER16_ALPHA [get_cells -hier $drv_handle]] if {[string match -nocase $layer16_alpha "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-alpha" "" boolean } set layer16_maxwidth [get_property CONFIG.LAYER16_MAX_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-max-width" $layer16_maxwidth int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_video16"] foreach connected_ip $connect_ip { if {[llength $connected_ip]} { set connected_ip_type [get_property IP_NAME $connected_ip] if {[string match -nocase $connected_ip_type "system_ila"]} { continue } hsi::utils::add_new_dts_param $mixer_node1 "dmas" "$connected_ip 0" reference hsi::utils::add_new_dts_param $mixer_node1 "dma-names" "dma0" string hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-streaming" "" boolean } } set sample [get_property CONFIG.LAYER16_UPSAMPLE [get_cells -hier $drv_handle]] if {[string match -nocase $sample "true"]} { hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-scale" "" boolean } set layer16_video_format [get_property CONFIG.LAYER16_VIDEO_FORMAT [get_cells -hier $drv_handle]] gen_video_format $layer16_video_format $mixer_node1 $drv_handle $max_data_width } default { } } } set mixer_node1 [add_or_get_dt_node -n "logo" -l xx_mix_logo$drv_handle -p $node] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,layer-id" $layer int set logo_width [get_property CONFIG.MAX_LOGO_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,logo-width" $logo_width int set logo_height [get_property CONFIG.MAX_LOGO_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$mixer_node1" "xlnx,logo-height" $logo_height int gen_gpio_reset $drv_handle $node } proc gen_video_format {num node drv_handle max_data_width} { set vid_formats "" switch $num { "0" { append vid_formats " " "BG24" } "1" { append vid_formats " " "YUYV" } "2" { if {$max_data_width == 10} { append vid_formats " " "XV20" } else { append vid_formats " " "NV16" } } "3" { if {$max_data_width == 10} { append vid_formats " " "XV15" } else { append vid_formats " " "NV12" } } "5" { append vid_formats " " "AB24" } "6" { append vid_formats " " "AVUY" } "10" { append vid_formats " " "XB24" } "11" { append vid_formats " " "XV24" } "12" { append vid_formats " " "YUYV" } "13" { append vid_formats " " "AB24" } "14" { append vid_formats " " "AVUY" } "15" { append vid_formats " " "XB30" } "16" { append vid_formats " " "XV30" } "17" { append vid_formats " " "BG16" } "18" { append vid_formats " " "NV16" } "19" { append vid_formats " " "NV12" } "20" { append vid_formats " " "BG24" } "21" { append vid_formats " " "VU24" } "22" { append vid_formats " " "XV20" } "23" { append vid_formats " " "XV15" } "24" { append vid_formats " " "GREY" } "25" { append vid_formats " " "Y10 " } "26" { append vid_formats " " "AR24" } "27" { append vid_formats " " "XR24" } "28" { append vid_formats " " "UYVY" } "29" { append vid_formats " " "RG24" } default { dtg_warning "Not supported format:$num" } } if {![string match -nocase $vid_formats ""]} { hsi::utils::add_new_dts_param "$node" "xlnx,vformat" $vid_formats stringlist } } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only one bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: mrmac/data/mrmac.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver mrmac OPTION supported_peripherals = (mrmac dcmac); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = mrmac; END driver ================================================ FILE: mrmac/data/mrmac.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc add_prop_ifexists {drv_handle hsi_prop dt_prop node {dt_prop_type "string"}} { if {[llength $drv_handle] && [llength $hsi_prop] && [llength $dt_prop] && [llength $node]} { set value [get_property $hsi_prop [get_cells -hier $drv_handle]] if {[llength $value]} { hsi::utils::add_new_dts_param "${node}" "$dt_prop" $value $dt_prop_type } } } proc fix_clockprop {s_clk rx_clk} { regsub -all "\<&" $s_clk {} s_clk regsub -all "\<&" $s_clk {} s_clk regsub -all " " $s_clk "" s_clk # if s_clk and rx_clk not matches and clock not starts # with <& add it. set rx_clk [string trim $rx_clk] if {![string match -nocase "$s_clk" $rx_clk] && \ ![string match -nocase "<&*" "$rx_clk"]} { set rx_clk "<&$rx_clk" } return "$s_clk $rx_clk" } proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "mrmac"]} { set compatible [append compatible " " "xlnx,mrmac-ethernet-1.0"] } set_drv_prop $drv_handle compatible "$compatible" stringlist set mrmac_ip [get_cells -hier $drv_handle] gen_mrmac_clk_property $drv_handle set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set dts_file [current_dt_tree] set mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]] dtg_verbose "mem_ranges:$mem_ranges" foreach mem_range $mem_ranges { set base_addr [string tolower [get_property BASE_VALUE $mem_range]] set base [format %x $base_addr] set high_addr [string tolower [get_property HIGH_VALUE $mem_range]] set slave_intf [get_property SLAVE_INTERFACE $mem_range] dtg_verbose "slave_intf:$slave_intf" set ptp_comp "xlnx,timer-syncer-1588-1.0" if {[string match -nocase $slave_intf "ptp_0_s_axi"]} { set ptp_0_node [add_or_get_dt_node -n "ptp_timer" -l "$slave_intf" -u $base -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$ptp_0_node" "compatible" "$ptp_comp" stringlist set reg [generate_reg_property $base_addr $high_addr] hsi::utils::add_new_dts_param "$ptp_0_node" "reg" $reg inthexlist } if {[string match -nocase $slave_intf "ptp_1_s_axi"]} { set ptp_1_node [add_or_get_dt_node -n "ptp_timer" -l "$slave_intf" -u $base -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$ptp_1_node" "compatible" "$ptp_comp" stringlist set reg [generate_reg_property $base_addr $high_addr] hsi::utils::add_new_dts_param "$ptp_1_node" "reg" $reg inthexlist } if {[string match -nocase $slave_intf "ptp_2_s_axi"]} { set ptp_2_node [add_or_get_dt_node -n "ptp_timer" -l "$slave_intf" -u $base -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$ptp_2_node" "compatible" "$ptp_comp" stringlist set reg [generate_reg_property $base_addr $high_addr] hsi::utils::add_new_dts_param "$ptp_2_node" "reg" $reg inthexlist } if {[string match -nocase $slave_intf "ptp_3_s_axi"]} { set ptp_3_node [add_or_get_dt_node -n "ptp_timer" -l "$slave_intf" -u $base -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$ptp_3_node" "compatible" "$ptp_comp" stringlist set reg [generate_reg_property $base_addr $high_addr] hsi::utils::add_new_dts_param "$ptp_3_node" "reg" $reg inthexlist } if {[string match -nocase $slave_intf "s_axi"]} { set mrmac0_highaddr_hex [format 0x%x [expr $base_addr + 0xFFF]] set reg [generate_reg_property $base_addr $mrmac0_highaddr_hex] hsi::utils::add_new_dts_param "$node" "reg" $reg inthexlist } } set connected_ip [get_connected_stream_ip $mrmac_ip "tx_axis_tdata0"] add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE0_CFG_C0 "xlnx,flex-slice0-cfg-c0" ${node} add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE0_CFG_C1 "xlnx,flex-slice0-cfg-c1" ${node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_DATA_RATE_C0 "xlnx,flex-port0-data-rate-c0" ${node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_DATA_RATE_C1 "xlnx,flex-port0-data-rate-c1" ${node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_ENABLE_TIME_STAMPING_C0 "xlnx,flex-port0-enable-time-stamping-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_ENABLE_TIME_STAMPING_C1 "xlnx,flex-port0-enable-time-stamping-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_MODE_C0 "xlnx,flex-port0-mode-c0" ${node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT0_MODE_C1 "xlnx,flex-port0-mode-c1" ${node} add_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Clocking_C0 "xlnx,port0-1588v2-clocking-c0" ${node} add_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Clocking_C1 "xlnx,port0-1588v2-clocking-c1" ${node} add_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Operation_MODE_C0 "xlnx,port0-1588v2-operation-mode-c0" ${node} add_prop_ifexists $drv_handle CONFIG.PORT0_1588v2_Operation_MODE_C1 "xlnx,port0-1588v2-operation-mode-c1" ${node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C0 "xlnx,mac-port0-enable-time-stamping-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_ENABLE_TIME_STAMPING_C1 "xlnx,mac-port0-enable-time-stamping-c1" ${node} int set MAC_PORT0_RATE_C0 [get_property CONFIG.MAC_PORT0_RATE_C0 [get_cells -hier $drv_handle]] if { [llength $MAC_PORT0_RATE_C0] } { if {[string match -nocase $MAC_PORT0_RATE_C0 "10GE"]} { set number 10000 hsi::utils::add_new_dts_param "${node}" "xlnx,mrmac-rate" $number int } else { hsi::utils::add_new_dts_param "${node}" "xlnx,mrmac-rate" $MAC_PORT0_RATE_C0 string } } add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RATE_C1 "xlnx,mac-port0-rate-c1" ${node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GCP_C0 "xlnx,mac-port0-rx-etype-gcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GCP_C1 "xlnx,mac-port0-rx-etype-gcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GPP_C0 "xlnx,mac-port0-rx-etype-gpp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_GPP_C1 "xlnx,mac-port0-rx-etype-gpp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PCP_C0 "xlnx,mac-port0-rx-etype-pcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PCP_C1 "xlnx,mac-port0-rx-etype-pcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PPP_C0 "xlnx,mac-port0-rx-etype-ppp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_ETYPE_PPP_C1 "xlnx,mac-port0-rx-etype-ppp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_FLOW_C0 "xlnx,mac-port0-rx-flow-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_FLOW_C1 "xlnx,mac-port0-rx-flow-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_GPP_C0 "xlnx,mac-port0-rx-opcode-gpp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_GPP_C1 "xlnx,mac-port0-rx-opcode-gpp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_GCP_C0 "xlnx,mac-port0-rx-opcode-max-gcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_GCP_C1 "xlnx,mac-port0-rx-opcode-max-gcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_PCP_C0 "xlnx,mac-port0-rx-opcode-max-pcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MAX_PCP_C1 "xlnx,mac-port0-rx-opcode-max-pcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_GCP_C0 "xlnx,mac-port0-rx-opcode-min-gcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_GCP_C1 "xlnx,mac-port0-rx-opcode-min-gcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_PCP_C0 "xlnx,mac-port0-rx-opcode-min-pcp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_MIN_PCP_C1 "xlnx,mac-port0-rx-opcode-min-pcp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_PPP_C0 "xlnx,mac-port0-rx-opcode-ppp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_RX_OPCODE_PPP_C1 "xlnx,mac-port0-rx-opcode-ppp-c1" ${node} int set MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT0_RX_PAUSE_DA_MCAST_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-da-mcast-c0" $MAC_PORT0_RX_PAUSE_DA_MCAST_C0 int set MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT0_RX_PAUSE_DA_MCAST_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-da-mcast-c1" $MAC_PORT0_RX_PAUSE_DA_MCAST_C1 int set MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT0_RX_PAUSE_DA_UCAST_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-da-ucast-c0" $MAC_PORT0_RX_PAUSE_DA_UCAST_C0 int set MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT0_RX_PAUSE_DA_UCAST_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-da-ucast-c1" $MAC_PORT0_RX_PAUSE_DA_UCAST_C1 int set MAC_PORT0_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT0_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_SA_C0 [check_size $MAC_PORT0_RX_PAUSE_SA_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-sa-c0" $MAC_PORT0_RX_PAUSE_SA_C0 int set MAC_PORT0_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT0_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_RX_PAUSE_SA_C1 [check_size $MAC_PORT0_RX_PAUSE_SA_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-rx-pause-sa-c1" $MAC_PORT0_RX_PAUSE_SA_C1 int set MAC_PORT0_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT0_TX_DA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_DA_GPP_C0 [check_size $MAC_PORT0_TX_DA_GPP_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-da-gpp-c0" $MAC_PORT0_TX_DA_GPP_C0 int set MAC_PORT0_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT0_TX_DA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_DA_GPP_C1 [check_size $MAC_PORT0_TX_DA_GPP_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-da-gpp-c1" $MAC_PORT0_TX_DA_GPP_C1 int set MAC_PORT0_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT0_TX_DA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_DA_PPP_C0 [check_size $MAC_PORT0_TX_DA_PPP_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-da-ppp-c0" $MAC_PORT0_TX_DA_PPP_C0 int set MAC_PORT0_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT0_TX_DA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_DA_PPP_C1 [check_size $MAC_PORT0_TX_DA_PPP_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-da-ppp-c1" $MAC_PORT0_TX_DA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_GPP_C0 "xlnx,mac-port0-tx-ethertype-gpp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_GPP_C1 "xlnx,mac-port0-tx-ethertype-gpp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_PPP_C0 "xlnx,mac-port0-tx-ethertype-ppp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_ETHERTYPE_PPP_C1 "xlnx,mac-port0-tx-ethertype-ppp-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_FLOW_C0 "xlnx,mac-port0-tx-flow-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_FLOW_C1 "xlnx,mac-port0-tx-flow-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_OPCODE_GPP_C0 "xlnx,mac-port0-tx-opcode-gpp-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT0_TX_OPCODE_GPP_C1 "xlnx,mac-port0-tx-opcode-gpp-c1" ${node} int set MAC_PORT0_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT0_TX_SA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_SA_GPP_C0 [check_size $MAC_PORT0_TX_SA_GPP_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-sa-gpp-c0" $MAC_PORT0_TX_SA_GPP_C0 int set MAC_PORT0_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT0_TX_SA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_SA_GPP_C1 [check_size $MAC_PORT0_TX_SA_GPP_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-sa-gpp-c1" $MAC_PORT0_TX_SA_GPP_C1 int set MAC_PORT0_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT0_TX_SA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_SA_PPP_C0 [check_size $MAC_PORT0_TX_SA_PPP_C0 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-sa-ppp-c0" $MAC_PORT0_TX_SA_PPP_C0 int set MAC_PORT0_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT0_TX_SA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT0_TX_SA_PPP_C1 [check_size $MAC_PORT0_TX_SA_PPP_C1 $node] hsi::utils::add_new_dts_param "${node}" "xlnx,mac-port0-tx-sa-ppp-c1" $MAC_PORT0_TX_SA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch0-rxprogdiv-freq-enable-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch0-rxprogdiv-freq-enable-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch0-rxprogdiv-freq-source-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch0-rxprogdiv-freq-source-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_VAL_C0 "xlnx,gt-ch0-rxprogdiv-freq-val-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RXPROGDIV_FREQ_VAL_C1 "xlnx,gt-ch0-rxprogdiv-freq-val-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_BUFFER_MODE_C0 "xlnx,gt-ch0-rx-buffer-mode-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_BUFFER_MODE_C1 "xlnx,gt-ch0-rx-buffer-mode-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_DATA_DECODING_C0 "xlnx,gt-ch0-rx-data-decoding-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_DATA_DECODING_C1 "xlnx,gt-ch0-rx-data-decoding-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_INT_DATA_WIDTH_C0 "xlnx,gt-ch0-rx-int-data-width-c0" ${node} int add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_INT_DATA_WIDTH_C1 "xlnx,gt-ch0-rx-int-data-width-c1" ${node} int add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_LINE_RATE_C0 "xlnx,gt-ch0-rx-line-rate-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_LINE_RATE_C1 "xlnx,gt-ch0-rx-line-rate-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_OUTCLK_SOURCE_C0 "xlnx,gt-ch0-rx-outclk-source-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_OUTCLK_SOURCE_C1 "xlnx,gt-ch0-rx-outclk-source-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch0-rx-refclk-frequency-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch0-rx-refclk-frequency-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_USER_DATA_WIDTH_C0 "xlnx,gt-ch0-rx-user-data-width-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_RX_USER_DATA_WIDTH_C1 "xlnx,gt-ch0-rx-user-data-width-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch0-txprogdiv-freq-enable-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch0-txprogdiv-freq-enable-c1" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch0-txprogdiv-freq-source-c0" ${node} add_prop_ifexists $drv_handle CONFIG.GT_CH0_TXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch0-txprogdiv-freq-source-c1" ${node} set mrmac_clk_names [get_property CONFIG.zclock-names1 $drv_handle] set mrmac_clks [get_property CONFIG.zclocks1 $drv_handle] set mrmac_clkname_len [llength $mrmac_clk_names] set mrmac_clk_len [expr {[llength [split $mrmac_clks ","]]}] set clk_list [split $mrmac_clks ","] set null "" set_drv_prop $drv_handle "zclock-names1" $null stringlist set refs "" set_drv_prop $drv_handle "zclocks1" "$refs" stringlist set i 0 while {$i < $mrmac_clkname_len} { set clkname [lindex $mrmac_clk_names $i] if {[string match -nocase $clkname "s_axi_aclk"]} { set s_axi_aclk "s_axi_aclk" set s_axi_aclk_index0 $i } if {[string match -nocase $clkname "rx_macif_clk"]} { set rx_macif_clk "rx_macif_clk" set rx_macif_clk_index0 $i } if {[string match -nocase $clkname "tx_macif_clk"]} { set tx_macif_clk "tx_macif_clk" set tx_macif_clk_index0 $i } if {[string match -nocase $clkname "ts_clk0"]} { set ts_clk0 "ts_clk" set ts_clk_index0 $i } if {[string match -nocase $clkname "ts_clk1"]} { set ts_clk1 "ts_clk" set ts_clk_index1 $i } if {[string match -nocase $clkname "ts_clk2"]} { set ts_clk2 "ts_clk" set ts_clk_index2 $i } if {[string match -nocase $clkname "ts_clk3"]} { set ts_clk3 "ts_clk" set ts_clk_index3 $i } if {[string match -nocase $clkname "tx_serdes_clk0"]} { set tx_serdes_clk0 "tx_serdes_clk" set tx_serdes_clk_index0 $i } if {[string match -nocase $clkname "tx_serdes_clk1"]} { set tx_serdes_clk1 "tx_serdes_clk" set tx_serdes_clk_index1 $i } if {[string match -nocase $clkname "tx_serdes_clk2"]} { set tx_serdes_clk2 "tx_serdes_clk" set tx_serdes_clk_index2 $i } if {[string match -nocase $clkname "tx_serdes_clk3"]} { set tx_serdes_clk3 "tx_serdes_clk" set tx_serdes_clk_index3 $i } if {[string match -nocase $clkname "rx_axi_clk0"] || [string match -nocase $clkname "rx_axi_clk"]} { set rx_axi_clk0 "rx_axi_clk" set rx_axi_clk_index0 $i } if {[string match -nocase $clkname "rx_axi_clk1"]} { set rx_axi_clk1 "rx_axi_clk" set rx_axi_clk_index1 $i } if {[string match -nocase $clkname "rx_axi_clk2"]} { set rx_axi_clk2 "rx_axi_clk" set rx_axi_clk_index2 $i } if {[string match -nocase $clkname "rx_axi_clk3"]} { set rx_axi_clk3 "rx_axi_clk" set rx_axi_clk_index3 $i } if {[string match -nocase $clkname "rx_flexif_clk0"]} { set rx_flexif_clk0 "rx_flexif_clk" set rx_flexif_clk_index0 $i } if {[string match -nocase $clkname "rx_flexif_clk1"]} { set rx_flexif_clk1 "rx_flexif_clk" set rx_flexif_clk_index1 $i } if {[string match -nocase $clkname "rx_flexif_clk2"]} { set rx_flexif_clk2 "rx_flexif_clk" set rx_flexif_clk_index2 $i } if {[string match -nocase $clkname "rx_flexif_clk3"]} { set rx_flexif_clk3 "rx_flexif_clk" set rx_flexif_clk_index3 $i } if {[string match -nocase $clkname "rx_ts_clk0"]} { set rx_ts_clk0 "rx_ts_clk" set rx_ts_clk0_index0 $i } if {[string match -nocase $clkname "rx_ts_clk1"]} { set rx_ts_clk1 "rx_ts_clk" set rx_ts_clk1_index1 $i } if {[string match -nocase $clkname "rx_ts_clk2"]} { set rx_ts_clk2 "rx_ts_clk" set rx_ts_clk2_index2 $i } if {[string match -nocase $clkname "rx_ts_clk3"]} { set rx_ts_clk3 "rx_ts_clk" set rx_ts_clk3_index3 $i } if {[string match -nocase $clkname "tx_axi_clk0"] || [string match -nocase $clkname "tx_axi_clk"] } { set tx_axi_clk0 "tx_axi_clk" set tx_axi_clk_index0 $i } if {[string match -nocase $clkname "tx_axi_clk1"]} { set tx_axi_clk1 "tx_axi_clk" set tx_axi_clk_index1 $i } if {[string match -nocase $clkname "tx_axi_clk2"]} { set tx_axi_clk2 "tx_axi_clk" set tx_axi_clk_index2 $i } if {[string match -nocase $clkname "tx_axi_clk3"]} { set tx_axi_clk3 "tx_axi_clk" set tx_axi_clk_index3 $i } if {[string match -nocase $clkname "tx_flexif_clk0"]} { set tx_flexif_clk0 "tx_flexif_clk" set tx_flexif_clk_index0 $i } if {[string match -nocase $clkname "tx_flexif_clk1"]} { set tx_flexif_clk1 "tx_flexif_clk" set tx_flexif_clk_index1 $i } if {[string match -nocase $clkname "tx_flexif_clk2"]} { set tx_flexif_clk2 "tx_flexif_clk" set tx_flexif_clk_index2 $i } if {[string match -nocase $clkname "tx_flexif_clk3"]} { set tx_flexif_clk3 "tx_flexif_clk" set tx_flexif_clk_index3 $i } if {[string match -nocase $clkname "tx_ts_clk0"]} { set tx_ts_clk0 "tx_ts_clk" set tx_ts_clk_index0 $i } if {[string match -nocase $clkname "tx_ts_clk1"]} { set tx_ts_clk1 "tx_ts_clk" set tx_ts_clk_index1 $i } if {[string match -nocase $clkname "tx_ts_clk2"]} { set tx_ts_clk2 "tx_ts_clk" set tx_ts_clk_index2 $i } if {[string match -nocase $clkname "tx_ts_clk3"]} { set tx_ts_clk3 "tx_ts_clk" set tx_ts_clk_index3 $i } incr i } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "mrmac"]} { lappend clknames "$s_axi_aclk" "$rx_axi_clk0" "$rx_flexif_clk0" "$rx_ts_clk0" "$tx_axi_clk0" "$tx_flexif_clk0" "$tx_ts_clk0" set tmpclks0 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index0]"] set txindex0 [lindex $clk_list $tx_ts_clk_index0] regsub -all "\>" $txindex0 {} txindex0 append clkvals0 "[lindex $tmpclks0 0], [lindex $tmpclks0 1], [lindex $clk_list $rx_flexif_clk_index0], [lindex $clk_list $rx_ts_clk0_index0], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index0], $txindex0" hsi::utils::add_new_dts_param "${node}" "clocks" $clkvals0 reference hsi::utils::add_new_dts_param "${node}" "clock-names" $clknames stringlist } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "dcmac"]} { lappend clknames "$s_axi_aclk" "$rx_axi_clk0" "$rx_flexif_clk0" "$tx_axi_clk0" "$tx_flexif_clk0" "$rx_macif_clk" "$ts_clk0" "$tx_macif_clk" "$tx_serdes_clk0" set tmpclks0 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index0]"] set txindex0 [lindex $clk_list $tx_serdes_clk_index0] regsub -all "\>" $txindex0 {} txindex0 append clkvals0 "[lindex $tmpclks0 0], [lindex $tmpclks0 1], [lindex $clk_list $rx_flexif_clk_index0], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index0], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index0], [lindex $clk_list $tx_macif_clk_index0], $txindex0" hsi::utils::add_new_dts_param "${node}" "clocks" $clkvals0 reference hsi::utils::add_new_dts_param "${node}" "clock-names" $clknames stringlist } set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_axis_tdata0"]] dtg_verbose "port0_pins:$port0_pins" foreach pin $port0_pins { set sink_periph [::hsi::get_cells -of_objects $pin] set mux_ip "" set fifo_ip "" if {[llength $sink_periph]} { if {[string match -nocase [get_property IP_NAME $sink_periph] "dcmac_intf_rx"]} { set sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] "M_AXIS"] } if {[string match -nocase [get_property IP_NAME $sink_periph] "axis_data_fifo"]} { set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph] if {[string_is_empty $fifo_width_bytes]} { set fifo_width_bytes 1 } set rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph] # FIFO can be other than 8 bits, and we need the rxmem in bytes set rxethmem [expr $rxethmem * $fifo_width_bytes] hsi::utils::add_new_dts_param "${node}" "xlnx,rxmem" $rxethmem int set fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] "m_axis_tdata"]] set mux_per [::hsi::get_cells -of_objects $fifo_pin] set fiforx_connect_ip "" if {[llength $mux_per] && [string match -nocase [get_property IP_NAME $mux_per] "mrmac_10g_mux"]} { set data_fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per] "rx_m_axis_tdata"]] set data_fifo_per [::hsi::get_cells -of_objects $data_fifo_pin] if {[string match -nocase [get_property IP_NAME $data_fifo_per] "axis_data_fifo"]} { set fiforx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per] "M_AXIS"] dtg_verbose "fiforx_connect_ip:$fiforx_connect_ip" set fiforx_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per] "m_axis_tdata"]] if {[llength $fiforx_pin]} { set fiforx_per [::hsi::get_cells -of_objects $fiforx_pin] } if {[llength $fiforx_per]} { if {[string match -nocase [get_property IP_NAME $fiforx_per] "RX_PTP_PKT_DETECT_TS_PREPEND"]} { set fiforx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx_per] "M_AXIS"] } } } } if {[string match -nocase [get_property IP_NAME $mux_per] "axi_mcdma"]} { set fiforx_connect_ip $mux_per } if {[llength $fiforx_connect_ip]} { if {[string match -nocase [get_property IP_NAME $fiforx_connect_ip] "axi_mcdma"]} { hsi::utils::add_new_dts_param "$node" "axistream-connected" "$fiforx_connect_ip" reference set num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip] set inhex [format %x $num_queues] append numqueues "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating set id 1 for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating hsi::utils::add_new_dts_param $node "xlnx,channel-ids" $id stringlist generate_intr_info $drv_handle $node $fiforx_connect_ip } } } } } #set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_timestamp_tod_0"]] set port0_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_ptp_tstamp_tag_out_0"]] dtg_verbose "port0_pins:$port0_pins" if {[llength $port0_pins]} { set sink_periph [::hsi::get_cells -of_objects $port0_pins] if {[llength $sink_periph]} { if {[string match -nocase [get_property IP_NAME $sink_periph] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] "tx_timestamp_tod"]] set sink_periph [::hsi::get_cells -of_objects $port_pins] } } if {[llength $sink_periph] && [string match -nocase [get_property IP_NAME $sink_periph] "xlconcat"]} { set intf "dout" set intr1_pin [::hsi::get_pins -of_objects $sink_periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_sink_pins $intr1_pin] set xl_per "" if {[llength $sink_pins]} { set xl_per [::hsi::get_cells -of_objects $sink_pins] } if {[llength $xl_per] && [string match -nocase [get_property IP_NAME $xl_per] "axis_dwidth_converter"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per] "m_axis_tdata"]] set axis_per [::hsi::get_cells -of_objects $port_pins] if {[string match -nocase [get_property IP_NAME $axis_per] "axis_clock_converter"]} { set tx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per] "M_AXIS"] if {[llength $tx_ip]} { hsi::utils::add_new_dts_param "$node" "axififo-connected" $tx_ip reference } } } } } else { dtg_warning "tx_timestamp_tod_0 connected pins are NULL...please check the design..." } #set rxtod_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_timestamp_tod_0"]] set rxtod_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_ptp_tstamp_out_0"]] dtg_verbose "rxtod_pins:$rxtod_pins" if {[llength $rxtod_pins]} { set rx_periph [::hsi::get_cells -of_objects $rxtod_pins] if {[llength $rx_periph]} { if {[string match -nocase [get_property IP_NAME $rx_periph] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph] "rx_timestamp_tod"]] set rx_periph [::hsi::get_cells -of_objects $port_pins] } } if {[llength $rx_periph] && [string match -nocase [get_property IP_NAME $rx_periph] "xlconcat"]} { set intf "dout" set in1_pin [::hsi::get_pins -of_objects $rx_periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_sink_pins $in1_pin] set rxxl_per "" if {[llength $sink_pins]} { set rxxl_per [::hsi::get_cells -of_objects $sink_pins] } if {[llength $rxxl_per] && [string match -nocase [get_property IP_NAME $rxxl_per] "axis_dwidth_converter"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rxxl_per] "m_axis_tdata"]] set rx_axis_per [::hsi::get_cells -of_objects $port_pins] if {[string match -nocase [get_property IP_NAME $rx_axis_per] "axis_clock_converter"]} { set rx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per] "M_AXIS"] if {[llength $rx_ip]} { hsi::utils::add_new_dts_param "$node" "xlnx,rxtsfifo" $rx_ip reference } } } } } else { dtg_warning "rx_timestamp_tod_0 connected pins are NULL...please check the design..." } set handle "" set mask_handle "" set ips [get_cells -hier -filter {IP_NAME == "axi_gpio"}] foreach ip $ips { set mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]] foreach mem_range $mem_ranges { set base [string tolower [get_property BASE_VALUE $mem_range]] if {[string match -nocase $base "0xa4010000"]} { set handle $ip break } } } if {[llength $handle]} { hsi::utils::add_new_dts_param "$node" "xlnx,gtctrl" $handle reference } # Workaround: For gtpll we might need to add the below code for v0.1 version. # We can remove this workaround for later versions. foreach ip $ips { set mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $ip]] foreach mem_range $mem_ranges { set base [string tolower [get_property BASE_VALUE $mem_range]] if {[string match -nocase $base "0xa4000000"]} { set mask_handle $ip break } } } if {[llength $mask_handle]} { hsi::utils::add_new_dts_param "$node" "xlnx,gtpll" $mask_handle reference } hsi::utils::add_new_dts_param "$node" "xlnx,phcindex" 0 int hsi::utils::add_new_dts_param "$node" "xlnx,gtlane" 0 int set gt_reset_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "gt_reset_all_in"]] dtg_verbose "gt_reset_pins:$gt_reset_pins" set gt_reset_per "" if {[llength $gt_reset_pins]} { set gt_reset_periph [::hsi::get_cells -of_objects $gt_reset_pins] if {[llength $gt_reset_periph] && [string match -nocase [get_property IP_NAME $gt_reset_periph] "xlconcat"]} { set intf "In0" set in1_pin [::hsi::get_pins -of_objects $gt_reset_periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $gt_reset_periph] $in1_pin]] set gt_per [::hsi::get_cells -of_objects $sink_pins] if {[string match -nocase [get_property IP_NAME $gt_per] "xlslice"]} { set intf "Din" set in1_pin [::hsi::get_pins -of_objects $gt_per -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $gt_per] $in1_pin]] set gt_reset_per [::hsi::get_cells -of_objects $sink_pins] dtg_verbose "gt_reset_per:$gt_reset_per" if {[llength $gt_reset_per]} { hsi::utils::add_new_dts_param "$node" "xlnx,gtctrl" $gt_reset_per reference } } } } set gt_pll_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "mst_rx_resetdone_in"]] dtg_verbose "gt_pll_pins:$gt_pll_pins" set gt_pll_per "" if {[llength $gt_pll_pins]} { set gt_pll_periph [::hsi::get_cells -of_objects $gt_pll_pins] if {[llength $gt_pll_periph] && [string match -nocase [get_property IP_NAME $gt_pll_periph] "xlconcat"]} { set intf "dout" set in1_pin [::hsi::get_pins -of_objects $gt_pll_periph -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $gt_pll_periph] $in1_pin]] foreach pin $sink_pins { if {[string match -nocase $pin "In0"]} { set gt_per [::hsi::get_cells -of_objects $sink_pins] foreach per $gt_per { if {[string match -nocase [get_property IP_NAME $per] "xlconcat"]} { set intf "dout" set in1_pin [::hsi::get_pins -of_objects $per -filter "NAME==$intf"] set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $per] $in1_pin]] if {[llength $sink_pins]} { set gt_pll_per [::hsi::get_cells -of_objects $sink_pins] dtg_verbose "gt_pll_per:$gt_pll_per" if {[llength $gt_pll_per]} { hsi::utils::add_new_dts_param "$node" "xlnx,gtpll" $gt_pll_per reference } } } } } } } } set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set dts_file [current_dt_tree] set mrmac1_base [format 0x%x [expr $base_addr + 0x1000]] set mrmac1_base_hex [format %x $mrmac1_base] set mrmac1_highaddr_hex [format 0x%x [expr $mrmac1_base + 0xFFF]] set port1 1 append new_label $drv_handle "_" $port1 set node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]] set mrmac1_node [add_or_get_dt_node -n $node_prefix -l "$new_label" -u $mrmac1_base_hex -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$mrmac1_node" "compatible" "$compatible" stringlist set mrmac1_reg [generate_reg_property $mrmac1_base $mrmac1_highaddr_hex] hsi::utils::add_new_dts_param "$mrmac1_node" "reg" $mrmac1_reg inthexlist if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "mrmac"]} { lappend clknames1 "$s_axi_aclk" "$rx_axi_clk1" "$rx_flexif_clk1" "$rx_ts_clk1" "$tx_axi_clk1" "$tx_flexif_clk1" "$tx_ts_clk1" set tmpclks1 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index1]"] set txindex1 [lindex $clk_list $tx_ts_clk_index1] regsub -all "\>" $txindex1 {} txindex1 append clkvals "[lindex $tmpclks1 0], [lindex $tmpclks1 1], [lindex $clk_list $rx_flexif_clk_index1], [lindex $clk_list $rx_ts_clk1_index1], [lindex $clk_list $tx_axi_clk_index1], [lindex $clk_list $tx_flexif_clk_index1], $txindex1" hsi::utils::add_new_dts_param "${mrmac1_node}" "clocks" $clkvals reference hsi::utils::add_new_dts_param "${mrmac1_node}" "clock-names" $clknames1 stringlist } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "dcmac"]} { lappend clknames1 "$s_axi_aclk" "$rx_axi_clk0" "$rx_flexif_clk1" "$tx_axi_clk0" "$tx_flexif_clk1" "$rx_macif_clk" "$ts_clk1" "$tx_macif_clk" "$tx_serdes_clk1" set tmpclks1 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index0]"] set txindex1 [lindex $clk_list $tx_serdes_clk_index1] regsub -all "\>" $txindex1 {} txindex1 append clkvals "[lindex $tmpclks1 0], [lindex $tmpclks1 1], [lindex $clk_list $rx_flexif_clk_index1], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index1], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index1], [lindex $clk_list $tx_macif_clk_index0], $txindex1" hsi::utils::add_new_dts_param "${mrmac1_node}" "clocks" $clkvals reference hsi::utils::add_new_dts_param "${mrmac1_node}" "clock-names" $clknames1 stringlist } set port1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_axis_tdata2"]] dtg_verbose "port1_pins:$port1_pins" foreach pin $port1_pins { set sink_periph [::hsi::get_cells -of_objects $pin] set mux_ip "" set fifo_ip "" if {[llength $sink_periph]} { if {[string match -nocase [get_property IP_NAME $sink_periph] "dcmac_intf_rx"]} { set sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] "M_AXIS"] } if {[string match -nocase [get_property IP_NAME $sink_periph] "axis_data_fifo"]} { set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph] if {[string_is_empty $fifo_width_bytes]} { set fifo_width_bytes 1 } set rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph] # FIFO can be other than 8 bits, and we need the rxmem in bytes set rxethmem [expr $rxethmem * $fifo_width_bytes] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,rxmem" $rxethmem int set fifo1_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] "m_axis_tdata"]] set mux_per1 [::hsi::get_cells -of_objects $fifo1_pin] set fiforx_connect_ip1 "" if {[llength $mux_per1] && [string match -nocase [get_property IP_NAME $mux_per1] "mrmac_10g_mux"]} { set data_fifo_pin1 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per1] "rx_m_axis_tdata"]] set data_fifo_per1 [::hsi::get_cells -of_objects $data_fifo_pin1] if {[string match -nocase [get_property IP_NAME $data_fifo_per1] "axis_data_fifo"]} { set fiforx_connect_ip1 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per1] "M_AXIS"] set fiforx1_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per1] "m_axis_tdata"]] if {[llength $fiforx1_pin]} { set fiforx1_per [::hsi::get_cells -of_objects $fiforx1_pin] } if {[llength $fiforx1_per]} { if {[string match -nocase [get_property IP_NAME $fiforx1_per] "RX_PTP_PKT_DETECT_TS_PREPEND"]} { set fiforx_connect_ip1 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx1_per] "M_AXIS"] } } } } if {[string match -nocase [get_property IP_NAME $mux_per1] "axi_mcdma"]} { set fiforx_connect_ip1 $mux_per1 } if {[llength $fiforx_connect_ip1]} { if {[string match -nocase [get_property IP_NAME $fiforx_connect_ip1] "axi_mcdma"]} { hsi::utils::add_new_dts_param "$mrmac1_node" "axistream-connected" "$fiforx_connect_ip1" reference set num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip1] set inhex [format %x $num_queues] append numqueues1 "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $mrmac1_node "xlnx,num-queues" $numqueues1 noformating set id 1 for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } hsi::utils::add_new_dts_param $mrmac1_node "xlnx,num-queues" $numqueues1 noformating hsi::utils::add_new_dts_param $mrmac1_node "xlnx,channel-ids" $id stringlist generate_intr_info $drv_handle $mrmac1_node $fiforx_connect_ip1 } } } } } #set txtodport1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_timestamp_tod_1"]] set txtodport1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_ptp_tstamp_tag_out_1"]] dtg_verbose "txtodport1_pins:$txtodport1_pins" if {[llength $txtodport1_pins]} { set tod1_sink_periph [::hsi::get_cells -of_objects $txtodport1_pins] if {[llength $tod1_sink_periph]} { if {[string match -nocase [get_property IP_NAME $tod1_sink_periph] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod1_sink_periph] "tx_timestamp_tod"]] set tod1_sink_periph [::hsi::get_cells -of_objects $port_pins] } } if {[llength $tod1_sink_periph] && [string match -nocase [get_property IP_NAME $tod1_sink_periph] "xlconcat"]} { set intf "dout" set in1_pin [::hsi::get_pins -of_objects $tod1_sink_periph -filter "NAME==$intf"] set in1sink_pins [::hsi::utils::get_sink_pins $in1_pin] set xl_per1 "" if {[llength $in1sink_pins]} { set xl_per1 [::hsi::get_cells -of_objects $in1sink_pins] } if {[llength $xl_per1] && [string match -nocase [get_property IP_NAME $xl_per1] "axis_dwidth_converter"]} { set port1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per1] "m_axis_tdata"]] set axis_per1 [::hsi::get_cells -of_objects $port1_pins] if {[string match -nocase [get_property IP_NAME $axis_per1] "axis_clock_converter"]} { set tx1_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per1] "M_AXIS"] if {[llength $tx1_ip]} { hsi::utils::add_new_dts_param "$mrmac1_node" "axififo-connected" $tx1_ip reference } } } } } else { dtg_warning "tx_timestamp_tod_1 connected pins are NULL...please check the design..." } #set rxtod1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_timestamp_tod_1"]] set rxtod1_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_ptp_tstamp_out_1"]] dtg_verbose "rxtod1_pins:$rxtod1_pins" if {[llength $rxtod1_pins]} { set rx_periph1 [::hsi::get_cells -of_objects $rxtod1_pins] if {[llength $rx_periph1]} { if {[string match -nocase [get_property IP_NAME $rx_periph1] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph1] "rx_timestamp_tod"]] set rx_periph1 [::hsi::get_cells -of_objects $port_pins] } } if {[llength $rx_periph1] && [string match -nocase [get_property IP_NAME $rx_periph1] "xlconcat"]} { set intf "dout" set inrx1_pin [::hsi::get_pins -of_objects $rx_periph1 -filter "NAME==$intf"] set rxtodsink_pins [::hsi::utils::get_sink_pins $inrx1_pin] set rx_per "" if {[llength $rxtodsink_pins]} { set rx_per [::hsi::get_cells -of_objects $rxtodsink_pins] } if {[llength $rx_per] && [string match -nocase [get_property IP_NAME $rx_per] "axis_dwidth_converter"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per] "m_axis_tdata"]] set rx_axis_per [::hsi::get_cells -of_objects $port_pins] if {[string match -nocase [get_property IP_NAME $rx_axis_per] "axis_clock_converter"]} { set rx_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per] "M_AXIS"] if {[llength $rx_ip]} { hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,rxtsfifo" $rx_ip reference } } } } } else { dtg_warning "rx_timestamp_tod_1 connected pins are NULL...please check the design..." } if {[llength $handle]} { hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,gtctrl" $handle reference } if {[llength $mask_handle]} { hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,gtpll" $mask_handle reference } if {[llength $gt_reset_per]} { hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,gtctrl" $gt_reset_per reference } if {[llength $gt_pll_per]} { hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,gtpll" $gt_pll_per reference } hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,phcindex" 1 int hsi::utils::add_new_dts_param "$mrmac1_node" "xlnx,gtlane" 1 int add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE1_CFG_C0 "xlnx,flex-slice1-cfg-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE1_CFG_C1 "xlnx,flex-slice1-cfg-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_DATA_RATE_C0 "xlnx,flex-port1-data-rate-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_DATA_RATE_C1 "xlnx,flex-port1-data-rate-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_ENABLE_TIME_STAMPING_C0 "xlnx,flex-port1-enable-time-stamping-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_ENABLE_TIME_STAMPING_C1 "xlnx,flex-port1-enable-time-stamping-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_MODE_C0 "xlnx,flex-port1-mode-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT1_MODE_C1 "xlnx,flex-port1-mode-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Clocking_C0 "xlnx,port1-1588v2-clocking-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Clocking_C1 "xlnx,port1-1588v2-clocking-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Operation_MODE_C0 "xlnx,port1-1588v2-operation-mode-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.PORT1_1588v2_Operation_MODE_C1 "xlnx,port1-1588v2-operation-mode-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_ENABLE_TIME_STAMPING_C0 "xlnx,mac-port1-enable-time-stamping-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_ENABLE_TIME_STAMPING_C1 "xlnx,mac-port1-enable-time-stamping-c1" ${mrmac1_node} int set MAC_PORT1_RATE_C0 [get_property CONFIG.MAC_PORT1_RATE_C0 [get_cells -hier $drv_handle]] if {[llength $MAC_PORT1_RATE_C0]} { if {[string match -nocase $MAC_PORT1_RATE_C0 "10GE"]} { set number 10000 hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mrmac-rate" $number int } else { hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mrmac-rate" $MAC_PORT1_RATE_C0 string } } add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RATE_C1 "xlnx,mac-port1-rate-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GCP_C0 "xlnx,mac-port1-rx-etype-gcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GCP_C1 "xlnx,mac-port1-rx-etype-gcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GPP_C0 "xlnx,mac-port1-rx-etype-gpp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_GPP_C1 "xlnx,mac-port1-rx-etype-gpp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PCP_C0 "xlnx,mac-port1-rx-etype-pcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PCP_C1 "xlnx,mac-port1-rx-etype-pcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PPP_C0 "xlnx,mac-port1-rx-etype-ppp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_ETYPE_PPP_C1 "xlnx,mac-port1-rx-etype-ppp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_FLOW_C0 "xlnx,mac-port1-rx-flow-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_FLOW_C1 "xlnx,mac-port1-rx-flow-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_GPP_C0 "xlnx,mac-port1-rx-opcode-gpp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_GPP_C1 "xlnx,mac-port1-rx-opcode-gpp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_GCP_C0 "xlnx,mac-port1-rx-opcode-max-gcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_GCP_C1 "xlnx,mac-port1-rx-opcode-max-gcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_PCP_C0 "xlnx,mac-port1-rx-opcode-max-pcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MAX_PCP_C1 "xlnx,mac-port1-rx-opcode-max-pcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_GCP_C0 "xlnx,mac-port1-rx-opcode-min-gcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_GCP_C1 "xlnx,mac-port1-rx-opcode-min-gcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_PCP_C0 "xlnx,mac-port1-rx-opcode-min-pcp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_MIN_PCP_C1 "xlnx,mac-port1-rx-opcode-min-pcp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_PPP_C0 "xlnx,mac-port1-rx-opcode-ppp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_RX_OPCODE_PPP_C1 "xlnx,mac-port1-rx-opcode-ppp-c1" ${mrmac1_node} int set MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT1_RX_PAUSE_DA_MCAST_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-da-mcast-c0" $MAC_PORT1_RX_PAUSE_DA_MCAST_C0 int set MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT1_RX_PAUSE_DA_MCAST_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-da-mcast-c1" $MAC_PORT1_RX_PAUSE_DA_MCAST_C1 int set MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT1_RX_PAUSE_DA_UCAST_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-da-ucast-c0" $MAC_PORT1_RX_PAUSE_DA_UCAST_C0 int set MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT1_RX_PAUSE_DA_UCAST_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-da-ucast-c1" $MAC_PORT1_RX_PAUSE_DA_UCAST_C1 int set MAC_PORT1_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT1_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_SA_C0 [check_size $MAC_PORT1_RX_PAUSE_SA_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-sa-c0" $MAC_PORT1_RX_PAUSE_SA_C0 int set MAC_PORT1_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT1_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_RX_PAUSE_SA_C1 [check_size $MAC_PORT1_RX_PAUSE_SA_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-rx-pause-sa-c1" $MAC_PORT1_RX_PAUSE_SA_C1 int set MAC_PORT1_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT1_TX_DA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_DA_GPP_C0 [check_size $MAC_PORT1_TX_DA_GPP_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-da-gpp-c0" $MAC_PORT1_TX_DA_GPP_C0 int set MAC_PORT1_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT1_TX_DA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_DA_GPP_C1 [check_size $MAC_PORT1_TX_DA_GPP_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-da-gpp-c1" $MAC_PORT1_TX_DA_GPP_C1 int set MAC_PORT1_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT1_TX_DA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_DA_PPP_C0 [check_size $MAC_PORT1_TX_DA_PPP_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-da-ppp-c0" $MAC_PORT1_TX_DA_PPP_C0 int set MAC_PORT1_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT1_TX_DA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_DA_PPP_C1 [check_size $MAC_PORT1_TX_DA_PPP_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-da-ppp-c1" $MAC_PORT1_TX_DA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_GPP_C0 "xlnx,mac-port1-tx-ethertype-gpp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_GPP_C1 "xlnx,mac-port1-tx-ethertype-gpp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_PPP_C0 "xlnx,mac-port1-tx-ethertype-ppp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_ETHERTYPE_PPP_C1 "xlnx,mac-port1-tx-ethertype-ppp-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_FLOW_C0 "xlnx,mac-port1-tx-flow-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_FLOW_C1 "xlnx,mac-port1-tx-flow-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_OPCODE_GPP_C0 "xlnx,mac-port1-tx-opcode-gpp-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT1_TX_OPCODE_GPP_C1 "xlnx,mac-port1-tx-opcode-gpp-c1" ${mrmac1_node} int set MAC_PORT1_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT1_TX_SA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_SA_GPP_C0 [check_size $MAC_PORT1_TX_SA_GPP_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-sa-gpp-c0" $MAC_PORT1_TX_SA_GPP_C0 int set MAC_PORT1_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT1_TX_SA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_SA_GPP_C1 [check_size $MAC_PORT1_TX_SA_GPP_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-sa-gpp-c1" $MAC_PORT1_TX_SA_GPP_C1 int set MAC_PORT1_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT1_TX_SA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_SA_PPP_C0 [check_size $MAC_PORT1_TX_SA_PPP_C0 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-sa-ppp-c0" $MAC_PORT1_TX_SA_PPP_C0 int set MAC_PORT1_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT1_TX_SA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT1_TX_SA_PPP_C1 [check_size $MAC_PORT1_TX_SA_PPP_C1 $mrmac1_node] hsi::utils::add_new_dts_param "${mrmac1_node}" "xlnx,mac-port1-tx-sa-ppp-c1" $MAC_PORT1_TX_SA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch1-rxprogdiv-freq-enable-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch1-rxprogdiv-freq-enable-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch1-rxprogdiv-freq-source-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch1-rxprogdiv-freq-source-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_VAL_C0 "xlnx,gt-ch1-rxprogdiv-freq-val-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RXPROGDIV_FREQ_VAL_C1 "xlnx,gt-ch1-rxprogdiv-freq-val-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_BUFFER_MODE_C0 "xlnx,gt-ch1-rx-buffer-mode-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_BUFFER_MODE_C1 "xlnx,gt-ch1-rx-buffer-mode-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_DATA_DECODING_C0 "xlnx,gt-ch1-rx-data-decoding-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_DATA_DECODING_C1 "xlnx,gt-ch1-rx-data-decoding-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_INT_DATA_WIDTH_C0 "xlnx,gt-ch1-rx-int-data-width-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_INT_DATA_WIDTH_C1 "xlnx,gt-ch1-rx-int-data-width-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_LINE_RATE_C0 "xlnx,gt-ch1-rx-line-rate-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_LINE_RATE_C1 "xlnx,gt-ch1-rx-line-rate-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_OUTCLK_SOURCE_C0 "xlnx,gt-ch1-rx-outclk-source-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_OUTCLK_SOURCE_C1 "xlnx,gt-ch1-rx-outclk-source-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch1-rx-refclk-frequency-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch1-rx-refclk-frequency-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_USER_DATA_WIDTH_C0 "xlnx,gt-ch1-rx-user-data-width-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_RX_USER_DATA_WIDTH_C1 "xlnx,gt-ch1-rx-user-data-width-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch1-txprogdiv-freq-enable-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch1-txprogdiv-freq-enable-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch1-txprogdiv-freq-source-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch1-txprogdiv-freq-source-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_VAL_C0 "xlnx,gt-ch1-txprogdiv-freq-val-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TXPROGDIV_FREQ_VAL_C1 "xlnx,gt-ch1-txprogdiv-freq-val-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_BUFFER_MODE_C0 "xlnx,gt-ch1-tx-buffer-mode-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_BUFFER_MODE_C1 "xlnx,gt-ch1-tx-buffer-mode-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_DATA_ENCODING_C0 "xlnx,gt-ch1-tx-data-encoding-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_DATA_ENCODING_C1 "xlnx,gt-ch1-tx-data-encoding-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_INT_DATA_WIDTH_C0 "xlnx,gt-ch1-int-data-width-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_INT_DATA_WIDTH_C1 "xlnx,gt-ch1-int-data-width-c1" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_LINE_RATE_C0 "xlnx,gt-ch1-tx-line-rate-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_LINE_RATE_C1 "xlnx,gt-ch1-tx-line-rate-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_OUTCLK_SOURCE_C0 "xlnx,gt-ch1-tx-outclk-source-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_OUTCLK_SOURCE_C1 "xlnx,gt-ch1-tx-outclk-source-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_PLL_TYPE_C0 "xlnx,gt-ch1-tx-pll-type-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_PLL_TYPE_C1 "xlnx,gt-ch1-tx-pll-type-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch1-tx-refclk-frequency-c0" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch1-tx-refclk-frequency-c1" ${mrmac1_node} add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_USER_DATA_WIDTH_C0 "xlnx,gt-ch1-tx-user-data-width-c0" ${mrmac1_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH1_TX_USER_DATA_WIDTH_C1 "xlnx,gt-ch1-tx-user-data-width-c1" ${mrmac1_node} int set mrmac2_base [format 0x%x [expr $base_addr + 0x2000]] set mrmac2_base_hex [format %x $mrmac2_base] set mrmac2_highaddr_hex [format 0x%x [expr $mrmac2_base + 0xFFF]] set port2 2 append label2 $drv_handle "_" $port2 set node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]] set mrmac2_node [add_or_get_dt_node -n $node_prefix -l "$label2" -u $mrmac2_base_hex -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$mrmac2_node" "compatible" "$compatible" stringlist set mrmac2_reg [generate_reg_property $mrmac2_base $mrmac2_highaddr_hex] hsi::utils::add_new_dts_param "$mrmac2_node" "reg" $mrmac2_reg inthexlist if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "mrmac"]} { lappend clknames2 "$s_axi_aclk" "$rx_axi_clk2" "$rx_flexif_clk2" "$rx_ts_clk2" "$tx_axi_clk2" "$tx_flexif_clk2" "$tx_ts_clk2" set tmpclks2 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index2]"] set txindex2 [lindex $clk_list $tx_ts_clk_index2] regsub -all "\>" $txindex2 {} txindex2 append clkvals2 "[lindex $tmpclks2 0], [lindex $tmpclks2 1], [lindex $clk_list $rx_flexif_clk_index2], [lindex $clk_list $rx_ts_clk2_index2], [lindex $clk_list $tx_axi_clk_index2], [lindex $clk_list $tx_flexif_clk_index2], $txindex2" hsi::utils::add_new_dts_param "${mrmac2_node}" "clocks" $clkvals2 reference hsi::utils::add_new_dts_param "${mrmac2_node}" "clock-names" $clknames2 stringlist } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "dcmac"]} { lappend clknames2 "$s_axi_aclk" "$rx_axi_clk0" "$rx_flexif_clk2" "$tx_axi_clk0" "$tx_flexif_clk2" "$rx_macif_clk" "$ts_clk2" "$tx_macif_clk" "$tx_serdes_clk2" set tmpclks2 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index0]"] set txindex2 [lindex $clk_list $tx_serdes_clk_index2] regsub -all "\>" $txindex2 {} txindex2 append clkvals2 "[lindex $tmpclks2 0], [lindex $tmpclks2 1], [lindex $clk_list $rx_flexif_clk_index2], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index2], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index2], [lindex $clk_list $tx_macif_clk_index0], $txindex2" hsi::utils::add_new_dts_param "${mrmac2_node}" "clocks" $clkvals2 reference hsi::utils::add_new_dts_param "${mrmac2_node}" "clock-names" $clknames2 stringlist } set port2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_axis_tdata4"]] foreach pin $port2_pins { set sink_periph [::hsi::get_cells -of_objects $pin] set mux_ip "" set fifo_ip "" if {[llength $sink_periph]} { if {[string match -nocase [get_property IP_NAME $sink_periph] "dcmac_intf_rx"]} { set sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] "M_AXIS"] } if {[string match -nocase [get_property IP_NAME $sink_periph] "axis_data_fifo"]} { set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph] if {[string_is_empty $fifo_width_bytes]} { set fifo_width_bytes 1 } set rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph] # FIFO can be other than 8 bits, and we need the rxmem in bytes set rxethmem [expr $rxethmem * $fifo_width_bytes] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,rxmem" $rxethmem int set fifo2_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] "m_axis_tdata"]] set mux_per2 [::hsi::get_cells -of_objects $fifo2_pin] set fiforx_connect_ip2 "" if {[llength $mux_per2] && [string match -nocase [get_property IP_NAME $mux_per2] "mrmac_10g_mux"]} { set data_fifo_pin2 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per2] "rx_m_axis_tdata"]] set data_fifo_per2 [::hsi::get_cells -of_objects $data_fifo_pin2] if {[string match -nocase [get_property IP_NAME $data_fifo_per2] "axis_data_fifo"]} { set fiforx_connect_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per2] "M_AXIS"] set fiforx2_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per2] "m_axis_tdata"]] set fiforx2_per [::hsi::get_cells -of_objects $fiforx2_pin] if {[string match -nocase [get_property IP_NAME $fiforx2_per] "RX_PTP_PKT_DETECT_TS_PREPEND"]} { set fiforx_connect_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx2_per] "M_AXIS"] } } } if {[string match -nocase [get_property IP_NAME $mux_per2] "axi_mcdma"]} { set fiforx_connect_ip2 $mux_per2 } if {[llength $fiforx_connect_ip2]} { if {[string match -nocase [get_property IP_NAME $fiforx_connect_ip2] "axi_mcdma"]} { hsi::utils::add_new_dts_param "$mrmac2_node" "axistream-connected" "$fiforx_connect_ip2" reference set num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip2] set inhex [format %x $num_queues] append numqueues2 "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $mrmac2_node "xlnx,num-queues" $numqueues2 noformating set id 1 for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } hsi::utils::add_new_dts_param $mrmac2_node "xlnx,num-queues" $numqueues2 noformating hsi::utils::add_new_dts_param $mrmac2_node "xlnx,channel-ids" $id stringlist generate_intr_info $drv_handle $mrmac2_node $fiforx_connect_ip2 } } } } } #set txtodport2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_timestamp_tod_2"]] set txtodport2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_ptp_tstamp_tag_out_2"]] if {[llength $txtodport2_pins]} { set tod2_sink_periph [::hsi::get_cells -of_objects $txtodport2_pins] if {[string match -nocase [get_property IP_NAME $tod2_sink_periph] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod2_sink_periph] "tx_timestamp_tod"]] set tod2_sink_periph [::hsi::get_cells -of_objects $port_pins] } if {[llength $tod2_sink_periph] && [string match -nocase [get_property IP_NAME $tod2_sink_periph] "xlconcat"]} { set intf "dout" set in2_pin [::hsi::get_pins -of_objects $tod2_sink_periph -filter "NAME==$intf"] set in2sink_pins [::hsi::utils::get_sink_pins $in2_pin] set xl_per2 "" if {[llength $in2sink_pins]} { set xl_per2 [::hsi::get_cells -of_objects $in2sink_pins] } if {[llength $xl_per2] && [string match -nocase [get_property IP_NAME $xl_per2] "axis_dwidth_converter"]} { set port2pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per2] "m_axis_tdata"]] set axis_per2 [::hsi::get_cells -of_objects $port2pins] if {[string match -nocase [get_property IP_NAME $axis_per2] "axis_clock_converter"]} { set tx2_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per2] "M_AXIS"] if {[llength $tx2_ip]} { hsi::utils::add_new_dts_param "$mrmac2_node" "axififo-connected" $tx2_ip reference } } } } } else { dtg_warning "tx_timestamp_tod_2 connected pins are NULL...please check the design..." } #set rxtod2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_timestamp_tod_2"]] set rxtod2_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_ptp_tstamp_out_2"]] if {[llength $rxtod2_pins]} { set rx_periph2 [::hsi::get_cells -of_objects $rxtod2_pins] if {[string match -nocase [get_property IP_NAME $rx_periph2] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph2] "rx_timestamp_tod"]] set rx_periph2 [::hsi::get_cells -of_objects $port_pins] } if {[llength $rx_periph2] && [string match -nocase [get_property IP_NAME $rx_periph2] "xlconcat"]} { set intf "dout" set inrx2_pin [::hsi::get_pins -of_objects $rx_periph2 -filter "NAME==$intf"] set rxtodsink_pins [::hsi::utils::get_sink_pins $inrx2_pin] set rx_per2 "" if {[llength $rxtodsink_pins]} { set rx_per2 [::hsi::get_cells -of_objects $rxtodsink_pins] } if {[llength $rx_per2] && [string match -nocase [get_property IP_NAME $rx_per2] "axis_dwidth_converter"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per2] "m_axis_tdata"]] set rx_axis_per2 [::hsi::get_cells -of_objects $port_pins] if {[string match -nocase [get_property IP_NAME $rx_axis_per2] "axis_clock_converter"]} { set rx_ip2 [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per2] "M_AXIS"] if {[llength $rx_ip2]} { hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,rxtsfifo" $rx_ip2 reference } } } } } else { dtg_warning "rx_timestamp_tod_2 connected pins are NULL...please check the design..." } if {[llength $handle]} { hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,gtctrl" $handle reference } if {[llength $mask_handle]} { hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,gtpll" $mask_handle reference } if {[llength $gt_reset_per]} { hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,gtctrl" $gt_reset_per reference } if {[llength $gt_pll_per]} { hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,gtpll" $gt_pll_per reference } hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,phcindex" 2 int hsi::utils::add_new_dts_param "$mrmac2_node" "xlnx,gtlane" 2 int add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE2_CFG_C0 "xlnx,flex-slice2-cfg-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE2_CFG_C1 "xlnx,flex-slice2-cfg-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_DATA_RATE_C0 "xlnx,flex-port2-data-rate-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_DATA_RATE_C1 "xlnx,flex-port2-data-rate-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_ENABLE_TIME_STAMPING_C0 "xlnx,flex-port2-enable-time-stamping-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_ENABLE_TIME_STAMPING_C1 "xlnx,flex-port2-enable-time-stamping-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_MODE_C0 "xlnx,flex-port2-mode-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT2_MODE_C1 "xlnx,flex-port2-mode-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Clocking_C0 "xlnx,port2-1588v2-clocking-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Clocking_C1 "xlnx,port2-1588v2-clocking-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Operation_MODE_C0 "xlnx,port2-1588v2-operation-mode-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.PORT2_1588v2_Operation_MODE_C1 "xlnx,port2-1588v2-operation-mode-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_ENABLE_TIME_STAMPING_C0 "xlnx,mac-port2-enable-time-stamping-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_ENABLE_TIME_STAMPING_C1 "xlnx,mac-port2-enable-time-stamping-c1" ${mrmac2_node} int set MAC_PORT2_RATE_C0 [get_property CONFIG.MAC_PORT2_RATE_C0 [get_cells -hier $drv_handle]] if {[llength ${MAC_PORT2_RATE_C0}]} { if {[string match -nocase $MAC_PORT2_RATE_C0 "10GE"]} { set number 10000 hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mrmac-rate" $number int } else { hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mrmac-rate" $MAC_PORT2_RATE_C0 string } } add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RATE_C1 "xlnx,mac-port2-rate-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GCP_C0 "xlnx,mac-port2-rx-etype-gcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GCP_C1 "xlnx,mac-port2-rx-etype-gcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GPP_C0 "xlnx,mac-port2-rx-etype-gpp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_GPP_C1 "xlnx,mac-port2-rx-etype-gpp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PCP_C0 "xlnx,mac-port2-rx-etype-pcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PCP_C1 "xlnx,mac-port2-rx-etype-pcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PPP_C0 "xlnx,mac-port2-rx-etype-ppp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_ETYPE_PPP_C1 "xlnx,mac-port2-rx-etype-ppp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_FLOW_C0 "xlnx,mac-port2-rx-flow-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_FLOW_C1 "xlnx,mac-port2-rx-flow-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_GPP_C0 "xlnx,mac-port2-rx-opcode-gpp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_GPP_C1 "xlnx,mac-port2-rx-opcode-gpp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_GCP_C0 "xlnx,mac-port2-rx-opcode-max-gcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_GCP_C1 "xlnx,mac-port2-rx-opcode-max-gcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_PCP_C0 "xlnx,mac-port2-rx-opcode-max-pcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MAX_PCP_C1 "xlnx,mac-port2-rx-opcode-max-pcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_GCP_C0 "xlnx,mac-port2-rx-opcode-min-gcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_GCP_C1 "xlnx,mac-port2-rx-opcode-min-gcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_PCP_C0 "xlnx,mac-port2-rx-opcode-min-pcp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_MIN_PCP_C1 "xlnx,mac-port2-rx-opcode-min-pcp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_PPP_C0 "xlnx,mac-port2-rx-opcode-ppp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_RX_OPCODE_PPP_C1 "xlnx,mac-port2-rx-opcode-ppp-c1" ${mrmac2_node} int set MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT2_RX_PAUSE_DA_MCAST_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-da-mcast-c0" $MAC_PORT2_RX_PAUSE_DA_MCAST_C0 int set MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT2_RX_PAUSE_DA_MCAST_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-da-mcast-c1" $MAC_PORT2_RX_PAUSE_DA_MCAST_C1 int set MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT2_RX_PAUSE_DA_UCAST_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-da-ucast-c0" $MAC_PORT2_RX_PAUSE_DA_UCAST_C0 int set MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT2_RX_PAUSE_DA_UCAST_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-da-ucast-c1" $MAC_PORT2_RX_PAUSE_DA_UCAST_C1 int set MAC_PORT2_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT2_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_SA_C0 [check_size $MAC_PORT2_RX_PAUSE_SA_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-sa-c0" $MAC_PORT2_RX_PAUSE_SA_C0 int set MAC_PORT2_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT2_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_RX_PAUSE_SA_C1 [check_size $MAC_PORT2_RX_PAUSE_SA_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-rx-pause-sa-c1" $MAC_PORT2_RX_PAUSE_SA_C1 int set MAC_PORT2_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT2_TX_DA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_DA_GPP_C0 [check_size $MAC_PORT2_TX_DA_GPP_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-da-gpp-c0" $MAC_PORT2_TX_DA_GPP_C0 int set MAC_PORT2_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT2_TX_DA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_DA_GPP_C1 [check_size $MAC_PORT2_TX_DA_GPP_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-da-gpp-c1" $MAC_PORT2_TX_DA_GPP_C1 int set MAC_PORT2_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT2_TX_DA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_DA_PPP_C0 [check_size $MAC_PORT2_TX_DA_PPP_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-da-ppp-c0" $MAC_PORT2_TX_DA_PPP_C0 int set MAC_PORT2_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT2_TX_DA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_DA_PPP_C1 [check_size $MAC_PORT2_TX_DA_PPP_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-da-ppp-c1" $MAC_PORT2_TX_DA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_GPP_C0 "xlnx,mac-port2-tx-ethertype-gpp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_GPP_C1 "xlnx,mac-port2-tx-ethertype-gpp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_PPP_C0 "xlnx,mac-port2-tx-ethertype-ppp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_ETHERTYPE_PPP_C1 "xlnx,mac-port2-tx-ethertype-ppp-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_FLOW_C0 "xlnx,mac-port2-tx-flow-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_FLOW_C1 "xlnx,mac-port2-tx-flow-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_OPCODE_GPP_C0 "xlnx,mac-port2-tx-opcode-gpp-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT2_TX_OPCODE_GPP_C1 "xlnx,mac-port2-tx-opcode-gpp-c1" ${mrmac2_node} int set MAC_PORT2_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT2_TX_SA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_SA_GPP_C0 [check_size $MAC_PORT2_TX_SA_GPP_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-sa-gpp-c0" $MAC_PORT2_TX_SA_GPP_C0 int set MAC_PORT2_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT2_TX_SA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_SA_GPP_C1 [check_size $MAC_PORT2_TX_SA_GPP_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-sa-gpp-c1" $MAC_PORT2_TX_SA_GPP_C1 int set MAC_PORT2_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT2_TX_SA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_SA_PPP_C0 [check_size $MAC_PORT2_TX_SA_PPP_C0 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-sa-ppp-c0" $MAC_PORT2_TX_SA_PPP_C0 int set MAC_PORT2_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT2_TX_SA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT2_TX_SA_PPP_C1 [check_size $MAC_PORT2_TX_SA_PPP_C1 $mrmac2_node] hsi::utils::add_new_dts_param "${mrmac2_node}" "xlnx,mac-port2-tx-sa-ppp-c1" $MAC_PORT2_TX_SA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch2-rxprogdiv-freq-enable-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch2-rxprogdiv-freq-enable-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch2-rxprogdiv-freq-source-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch2-rxprogdiv-freq-source-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_VAL_C0 "xlnx,gt-ch2-rxprogdiv-freq-val-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RXPROGDIV_FREQ_VAL_C1 "xlnx,gt-ch2-rxprogdiv-freq-val-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_BUFFER_MODE_C0 "xlnx,gt-ch2-rx-buffer-mode-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_BUFFER_MODE_C1 "xlnx,gt-ch2-rx-buffer-mode-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_DATA_DECODING_C0 "xlnx,gt-ch2-rx-data-decoding-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_DATA_DECODING_C1 "xlnx,gt-ch2-rx-data-decoding-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_INT_DATA_WIDTH_C0 "xlnx,gt-ch2-rx-int-data-width-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_INT_DATA_WIDTH_C1 "xlnx,gt-ch2-rx-int-data-width-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_LINE_RATE_C0 "xlnx,gt-ch2-rx-line-rate-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_LINE_RATE_C1 "xlnx,gt-ch2-rx-line-rate-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_OUTCLK_SOURCE_C0 "xlnx,gt-ch2-rx-outclk-source-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_OUTCLK_SOURCE_C1 "xlnx,gt-ch2-rx-outclk-source-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch2-rx-refclk-frequency-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch2-rx-refclk-frequency-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_USER_DATA_WIDTH_C0 "xlnx,gt-ch2-rx-user-data-width-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_RX_USER_DATA_WIDTH_C1 "xlnx,gt-ch2-rx-user-data-width-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch2-txprogdiv-freq-enable-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch2-txprogdiv-freq-enable-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch2-txprogdiv-freq-source-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch2-txprogdiv-freq-source-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_BUFFER_MODE_C0 "xlnx,gt-ch2-tx-buffer-mode-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_BUFFER_MODE_C1 "xlnx,gt-ch2-tx-buffer-mode-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_DATA_ENCODING_C0 "xlnx,gt-ch2-tx-data-encoding-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_DATA_ENCODING_C1 "xlnx,gt-ch2-tx-data-encoding-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_INT_DATA_WIDTH_C0 "xlnx,gt-ch2-int-data-width-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_INT_DATA_WIDTH_C1 "xlnx,gt-ch2-int-data-width-c1" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_LINE_RATE_C0 "xlnx,gt-ch2-tx-line-rate-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_LINE_RATE_C1 "xlnx,gt-ch2-tx-line-rate-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_OUTCLK_SOURCE_C0 "xlnx,gt-ch2-tx-outclk-source-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_OUTCLK_SOURCE_C1 "xlnx,gt-ch2-tx-outclk-source-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_PLL_TYPE_C0 "xlnx,gt-ch2-tx-pll-type-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_PLL_TYPE_C1 "xlnx,gt-ch2-tx-pll-type-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch2-tx-refclk-frequency-c0" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch2-tx-refclk-frequency-c1" ${mrmac2_node} add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_USER_DATA_WIDTH_C0 "xlnx,gt-ch2-tx-user-data-width-c0" ${mrmac2_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH2_TX_USER_DATA_WIDTH_C1 "xlnx,gt-ch2-tx-user-data-width-c1" ${mrmac2_node} int set mrmac3_base [format 0x%x [expr $base_addr + 0x3000]] set mrmac3_base_hex [format %x $mrmac3_base] set mrmac3_highaddr_hex [format 0x%x [expr $mrmac3_base + 0xFFF]] set port3 3 append label3 $drv_handle "_" $port3 set node_prefix [get_property IP_NAME [get_cells -hier $drv_handle]] set mrmac3_node [add_or_get_dt_node -n $node_prefix -l "$label3" -u $mrmac3_base_hex -d $dts_file -p $bus_node] hsi::utils::add_new_dts_param "$mrmac3_node" "compatible" "$compatible" stringlist set mrmac3_reg [generate_reg_property $mrmac3_base $mrmac3_highaddr_hex] hsi::utils::add_new_dts_param "$mrmac3_node" "reg" $mrmac3_reg inthexlist set port3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_axis_tdata6"]] foreach pin $port3_pins { set sink_periph [::hsi::get_cells -of_objects $pin] set mux_ip "" set fifo_ip "" if {[llength $sink_periph]} { if {[string match -nocase [get_property IP_NAME $sink_periph] "dcmac_intf_rx"]} { set sink_periph [hsi::utils::get_connected_stream_ip [get_cells -hier $sink_periph] "M_AXIS"] } if {[string match -nocase [get_property IP_NAME $sink_periph] "axis_data_fifo"]} { set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $sink_periph] if {[string_is_empty $fifo_width_bytes]} { set fifo_width_bytes 1 } set rxethmem [get_property CONFIG.FIFO_DEPTH $sink_periph] # FIFO can be other than 8 bits, and we need the rxmem in bytes set rxethmem [expr $rxethmem * $fifo_width_bytes] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,rxmem" $rxethmem int set fifo3_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $sink_periph] "m_axis_tdata"]] set mux_per3 [::hsi::get_cells -of_objects $fifo3_pin] set fiforx_connect_ip3 "" if {[llength $mux_per3] && [string match -nocase [get_property IP_NAME $mux_per3] "mrmac_10g_mux"]} { set data_fifo_pin3 [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_per3] "rx_m_axis_tdata"]] set data_fifo_per3 [::hsi::get_cells -of_objects $data_fifo_pin3] if {[string match -nocase [get_property IP_NAME $data_fifo_per3] "axis_data_fifo"]} { set fiforx_connect_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $data_fifo_per3] "M_AXIS"] set fiforx3_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per3] "m_axis_tdata"]] set fiforx3_per [::hsi::get_cells -of_objects $fiforx3_pin] if {[string match -nocase [get_property IP_NAME $fiforx3_per] "RX_PTP_PKT_DETECT_TS_PREPEND"]} { set fiforx_connect_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $fiforx3_per] "M_AXIS"] } } } if {[string match -nocase [get_property IP_NAME $mux_per3] "axi_mcdma"]} { set fiforx_connect_ip3 $mux_per3 } if {[llength $fiforx_connect_ip3]} { if {[string match -nocase [get_property IP_NAME $fiforx_connect_ip3] "axi_mcdma"]} { hsi::utils::add_new_dts_param "$mrmac3_node" "axistream-connected" "$fiforx_connect_ip3" reference set num_queues [get_property CONFIG.c_num_mm2s_channels $fiforx_connect_ip3] set inhex [format %x $num_queues] append numqueues3 "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param $mrmac3_node "xlnx,num-queues" $numqueues3 noformating set id 1 for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } hsi::utils::add_new_dts_param $mrmac3_node "xlnx,num-queues" $numqueues3 noformating hsi::utils::add_new_dts_param $mrmac3_node "xlnx,channel-ids" $id stringlist generate_intr_info $drv_handle $mrmac3_node $fiforx_connect_ip3 } } } } } #set txtodport3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_timestamp_tod_3"]] set txtodport3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "tx_ptp_tstamp_tag_out_3"]] if {[llength $txtodport3_pins]} { set tod3_sink_periph [::hsi::get_cells -of_objects $txtodport3_pins] if {[string match -nocase [get_property IP_NAME $tod3_sink_periph] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $tod3_sink_periph] "tx_timestamp_tod"]] set tod3_sink_periph [::hsi::get_cells -of_objects $port_pins] } if {[llength $tod3_sink_periph] && [string match -nocase [get_property IP_NAME $tod3_sink_periph] "xlconcat"]} { set intf "dout" set in3_pin [::hsi::get_pins -of_objects $tod3_sink_periph -filter "NAME==$intf"] set in3sink_pins [::hsi::utils::get_sink_pins $in3_pin] set xl_per3 "" if {[llength $in3sink_pins]} { set xl_per3 [::hsi::get_cells -of_objects $in3sink_pins] } if {[llength $xl_per3] && [string match -nocase [get_property IP_NAME $xl_per3] "axis_dwidth_converter"]} { set port3pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $xl_per3] "m_axis_tdata"]] set axis_per3 [::hsi::get_cells -of_objects $port3pins] if {[string match -nocase [get_property IP_NAME $axis_per3] "axis_clock_converter"]} { set tx3_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $axis_per3] "M_AXIS"] if {[llength $tx3_ip]} { hsi::utils::add_new_dts_param "$mrmac3_node" "axififo-connected" $tx3_ip reference } } } } } else { dtg_warning "tx_timestamp_tod_3 connected pins are NULL...please check the design..." } #set rxtod3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_timestamp_tod_3"]] set rxtod3_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mrmac_ip] "rx_ptp_tstamp_out_3"]] if {[llength $rxtod3_pins]} { set rx_periph3 [::hsi::get_cells -of_objects $rxtod3_pins] if {[string match -nocase [get_property IP_NAME $rx_periph3] "mrmac_ptp_timestamp_if"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_periph3] "rx_timestamp_tod"]] set rx_periph3 [::hsi::get_cells -of_objects $port_pins] } if {[llength $rx_periph3] && [string match -nocase [get_property IP_NAME $rx_periph3] "xlconcat"]} { set intf "dout" set inrx3_pin [::hsi::get_pins -of_objects $rx_periph3 -filter "NAME==$intf"] set rxtodsink_pins [::hsi::utils::get_sink_pins $inrx3_pin] set rx_per3 "" if {[llength $rxtodsink_pins]} { set rx_per3 [::hsi::get_cells -of_objects $rxtodsink_pins] } if {[llength $rx_per3] && [string match -nocase [get_property IP_NAME $rx_per3] "axis_dwidth_converter"]} { set port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $rx_per3] "m_axis_tdata"]] set rx_axis_per3 [::hsi::get_cells -of_objects $port_pins] if {[string match -nocase [get_property IP_NAME $rx_axis_per3] "axis_clock_converter"]} { set rx_ip3 [hsi::utils::get_connected_stream_ip [get_cells -hier $rx_axis_per3] "M_AXIS"] if {[llength $rx_ip3]} { hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,rxtsfifo" $rx_ip3 reference } } } } } else { dtg_warning "rx_timestamp_tod_3 connected pins are NULL...please check the design..." } if {[llength $handle]} { hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,gtctrl" $handle reference } if {[llength $mask_handle]} { hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,gtpll" $mask_handle reference } if {[llength $gt_reset_per]} { hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,gtctrl" $gt_reset_per reference } if {[llength $gt_pll_per]} { hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,gtpll" $gt_pll_per reference } hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,phcindex" 3 int hsi::utils::add_new_dts_param "$mrmac3_node" "xlnx,gtlane" 3 int if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "mrmac"]} { lappend clknames3 "$s_axi_aclk" "$rx_axi_clk3" "$rx_flexif_clk3" "$rx_ts_clk3" "$tx_axi_clk3" "$tx_flexif_clk3" "$tx_ts_clk3" set tmpclks3 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index3]"] set txindex3 [lindex $clk_list $tx_ts_clk_index3] regsub -all "\>" $txindex3 {} txindex3 append clkvals3 "[lindex $tmpclks3 0], [lindex $tmpclks3 1], [lindex $clk_list $rx_flexif_clk_index3], [lindex $clk_list $rx_ts_clk3_index3], [lindex $clk_list $tx_axi_clk_index3], [lindex $clk_list $tx_flexif_clk_index3], $txindex3" hsi::utils::add_new_dts_param "${mrmac3_node}" "clocks" $clkvals3 reference hsi::utils::add_new_dts_param "${mrmac3_node}" "clock-names" $clknames3 stringlist } if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "dcmac"]} { lappend clknames3 "$s_axi_aclk" "$rx_axi_clk0" "$rx_flexif_clk3" "$tx_axi_clk0" "$tx_flexif_clk3" "$rx_macif_clk" "$ts_clk3" "$tx_macif_clk" "$tx_serdes_clk3" set tmpclks3 [fix_clockprop "[lindex $clk_list $s_axi_aclk_index0]" "[lindex $clk_list $rx_axi_clk_index0]"] set txindex3 [lindex $clk_list $tx_serdes_clk_index3] regsub -all "\>" $txindex3 {} txindex3 append clkvals3 "[lindex $tmpclks3 0], [lindex $tmpclks3 1], [lindex $clk_list $rx_flexif_clk_index3], [lindex $clk_list $tx_axi_clk_index0], [lindex $clk_list $tx_flexif_clk_index3], [lindex $clk_list $rx_macif_clk_index0], [lindex $clk_list $ts_clk_index3], [lindex $clk_list $tx_macif_clk_index0], $txindex3" hsi::utils::add_new_dts_param "${mrmac3_node}" "clocks" $clkvals3 reference hsi::utils::add_new_dts_param "${mrmac3_node}" "clock-names" $clknames3 stringlist } add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE3_CFG_C0 "xlnx,flex-slice3-cfg-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.C_FEC_SLICE3_CFG_C1 "xlnx,flex-slice3-cfg-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_DATA_RATE_C0 "xlnx,flex-port3-data-rate-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_DATA_RATE_C1 "xlnx,flex-port3-data-rate-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_ENABLE_TIME_STAMPING_C0 "xlnx,flex-port3-enable-time-stamping-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_ENABLE_TIME_STAMPING_C1 "xlnx,flex-port3-enable-time-stamping-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_MODE_C0 "xlnx,flex-port3-mode-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.C_FLEX_PORT3_MODE_C1 "xlnx,flex-port3-mode-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Clocking_C0 "xlnx,port3-1588v2-clocking-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Clocking_C1 "xlnx,port3-1588v2-clocking-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Operation_MODE_C0 "xlnx,port3-1588v2-operation-mode-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.PORT3_1588v2_Operation_MODE_C1 "xlnx,port3-1588v2-operation-mode-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_ENABLE_TIME_STAMPING_C0 "xlnx,mac-port3-enable-time-stamping-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_ENABLE_TIME_STAMPING_C1 "xlnx,mac-port3-enable-time-stamping-c1" ${mrmac3_node} int set MAC_PORT3_RATE_C0 [get_property CONFIG.MAC_PORT3_RATE_C0 [get_cells -hier $drv_handle]] if {[llength $MAC_PORT3_RATE_C0]} { if {[string match -nocase $MAC_PORT3_RATE_C0 "10GE"]} { set number 10000 hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mrmac-rate" $number int } else { hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mrmac-rate" $MAC_PORT3_RATE_C0 string } } add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RATE_C1 "xlnx,mac-port3-rate-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GCP_C0 "xlnx,mac-port3-rx-etype-gcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GCP_C1 "xlnx,mac-port3-rx-etype-gcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GPP_C0 "xlnx,mac-port3-rx-etype-gpp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_GPP_C1 "xlnx,mac-port3-rx-etype-gpp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PCP_C0 "xlnx,mac-port3-rx-etype-pcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PCP_C1 "xlnx,mac-port3-rx-etype-pcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PPP_C0 "xlnx,mac-port3-rx-etype-ppp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_ETYPE_PPP_C1 "xlnx,mac-port3-rx-etype-ppp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_FLOW_C0 "xlnx,mac-port3-rx-flow-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_FLOW_C1 "xlnx,mac-port3-rx-flow-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_GPP_C0 "xlnx,mac-port3-rx-opcode-gpp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_GPP_C1 "xlnx,mac-port3-rx-opcode-gpp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_GCP_C0 "xlnx,mac-port3-rx-opcode-max-gcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_GCP_C1 "xlnx,mac-port3-rx-opcode-max-gcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_PCP_C0 "xlnx,mac-port3-rx-opcode-max-pcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MAX_PCP_C1 "xlnx,mac-port3-rx-opcode-max-pcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_GCP_C0 "xlnx,mac-port3-rx-opcode-min-gcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_GCP_C1 "xlnx,mac-port3-rx-opcode-min-gcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_PCP_C0 "xlnx,mac-port3-rx-opcode-min-pcp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_MIN_PCP_C1 "xlnx,mac-port3-rx-opcode-min-pcp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_PPP_C0 "xlnx,mac-port3-rx-opcode-ppp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_RX_OPCODE_PPP_C1 "xlnx,mac-port3-rx-opcode-ppp-c1" ${mrmac3_node} int set MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_DA_MCAST_C0 [check_size $MAC_PORT3_RX_PAUSE_DA_MCAST_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-da-mcast-c0" $MAC_PORT3_RX_PAUSE_DA_MCAST_C0 int set MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_DA_MCAST_C1 [check_size $MAC_PORT3_RX_PAUSE_DA_MCAST_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-da-mcast-c1" $MAC_PORT3_RX_PAUSE_DA_MCAST_C1 int set MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_DA_UCAST_C0 [check_size $MAC_PORT3_RX_PAUSE_DA_UCAST_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-da-ucast-c0" $MAC_PORT3_RX_PAUSE_DA_UCAST_C0 int set MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_DA_UCAST_C1 [check_size $MAC_PORT3_RX_PAUSE_DA_UCAST_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-da-ucast-c1" $MAC_PORT3_RX_PAUSE_DA_UCAST_C1 int set MAC_PORT3_RX_PAUSE_SA_C0 [get_property CONFIG.MAC_PORT3_RX_PAUSE_SA_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_SA_C0 [check_size $MAC_PORT3_RX_PAUSE_SA_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-sa-c0" $MAC_PORT3_RX_PAUSE_SA_C0 int set MAC_PORT3_RX_PAUSE_SA_C1 [get_property CONFIG.MAC_PORT3_RX_PAUSE_SA_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_RX_PAUSE_SA_C1 [check_size $MAC_PORT3_RX_PAUSE_SA_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-rx-pause-sa-c1" $MAC_PORT3_RX_PAUSE_SA_C1 int set MAC_PORT3_TX_DA_GPP_C0 [get_property CONFIG.MAC_PORT3_TX_DA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_DA_GPP_C0 [check_size $MAC_PORT3_TX_DA_GPP_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-da-gpp-c0" $MAC_PORT3_TX_DA_GPP_C0 int set MAC_PORT3_TX_DA_GPP_C1 [get_property CONFIG.MAC_PORT3_TX_DA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_DA_GPP_C1 [check_size $MAC_PORT3_TX_DA_GPP_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-da-gpp-c1" $MAC_PORT3_TX_DA_GPP_C1 int set MAC_PORT3_TX_DA_PPP_C0 [get_property CONFIG.MAC_PORT3_TX_DA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_DA_PPP_C0 [check_size $MAC_PORT3_TX_DA_PPP_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-da-ppp-c0" $MAC_PORT3_TX_DA_PPP_C0 int set MAC_PORT3_TX_DA_PPP_C1 [get_property CONFIG.MAC_PORT3_TX_DA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_DA_PPP_C1 [check_size $MAC_PORT3_TX_DA_PPP_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-da-ppp-c1" $MAC_PORT3_TX_DA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_GPP_C0 "xlnx,mac-port3-tx-ethertype-gpp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_GPP_C1 "xlnx,mac-port3-tx-ethertype-gpp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_PPP_C0 "xlnx,mac-port3-tx-ethertype-ppp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_ETHERTYPE_PPP_C1 "xlnx,mac-port3-tx-ethertype-ppp-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_FLOW_C0 "xlnx,mac-port3-tx-flow-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_FLOW_C1 "xlnx,mac-port3-tx-flow-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_OPCODE_GPP_C0 "xlnx,mac-port3-tx-opcode-gpp-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.MAC_PORT3_TX_OPCODE_GPP_C1 "xlnx,mac-port3-tx-opcode-gpp-c1" ${mrmac3_node} int set MAC_PORT3_TX_SA_GPP_C0 [get_property CONFIG.MAC_PORT3_TX_SA_GPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_SA_GPP_C0 [check_size $MAC_PORT3_TX_SA_GPP_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-sa-gpp-c0" $MAC_PORT3_TX_SA_GPP_C0 int set MAC_PORT3_TX_SA_GPP_C1 [get_property CONFIG.MAC_PORT3_TX_SA_GPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_SA_GPP_C1 [check_size $MAC_PORT3_TX_SA_GPP_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-sa-gpp-c1" $MAC_PORT3_TX_SA_GPP_C1 int set MAC_PORT3_TX_SA_PPP_C0 [get_property CONFIG.MAC_PORT3_TX_SA_PPP_C0 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_SA_PPP_C0 [check_size $MAC_PORT3_TX_SA_PPP_C0 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-sa-ppp-c0" $MAC_PORT3_TX_SA_PPP_C0 int set MAC_PORT3_TX_SA_PPP_C1 [get_property CONFIG.MAC_PORT3_TX_SA_PPP_C1 [get_cells -hier $drv_handle]] set MAC_PORT3_TX_SA_PPP_C1 [check_size $MAC_PORT3_TX_SA_PPP_C1 $mrmac3_node] hsi::utils::add_new_dts_param "${mrmac3_node}" "xlnx,mac-port3-tx-sa-ppp-c1" $MAC_PORT3_TX_SA_PPP_C1 int add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch3-rxprogdiv-freq-enable-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch3-rxprogdiv-freq-enable-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch3-rxprogdiv-freq-source-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch3-rxprogdiv-freq-source-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_VAL_C0 "xlnx,gt-ch3-rxprogdiv-freq-val-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RXPROGDIV_FREQ_VAL_C1 "xlnx,gt-ch3-rxprogdiv-freq-val-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_BUFFER_MODE_C0 "xlnx,gt-ch3-rx-buffer-mode-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_BUFFER_MODE_C1 "xlnx,gt-ch3-rx-buffer-mode-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_DATA_DECODING_C0 "xlnx,gt-ch3-rx-data-decoding-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_DATA_DECODING_C1 "xlnx,gt-ch3-rx-data-decoding-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_INT_DATA_WIDTH_C0 "xlnx,gt-ch3-rx-int-data-width-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_INT_DATA_WIDTH_C1 "xlnx,gt-ch3-rx-int-data-width-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_LINE_RATE_C0 "xlnx,gt-ch3-rx-line-rate-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_LINE_RATE_C1 "xlnx,gt-ch3-rx-line-rate-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_OUTCLK_SOURCE_C0 "xlnx,gt-ch3-rx-outclk-source-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_OUTCLK_SOURCE_C1 "xlnx,gt-ch3-rx-outclk-source-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch3-rx-refclk-frequency-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch3-rx-refclk-frequency-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_USER_DATA_WIDTH_C0 "xlnx,gt-ch3-rx-user-data-width-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_RX_USER_DATA_WIDTH_C1 "xlnx,gt-ch3-rx-user-data-width-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_ENABLE_C0 "xlnx,gt-ch3-txprogdiv-freq-enable-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_ENABLE_C1 "xlnx,gt-ch3-txprogdiv-freq-enable-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_SOURCE_C0 "xlnx,gt-ch3-txprogdiv-freq-source-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TXPROGDIV_FREQ_SOURCE_C1 "xlnx,gt-ch3-txprogdiv-freq-source-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_BUFFER_MODE_C0 "xlnx,gt-ch3-tx-buffer-mode-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_BUFFER_MODE_C1 "xlnx,gt-ch3-tx-buffer-mode-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_DATA_ENCODING_C0 "xlnx,gt-ch3-tx-data-encoding-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_DATA_ENCODING_C1 "xlnx,gt-ch3-tx-data-encoding-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_INT_DATA_WIDTH_C0 "xlnx,gt-ch3-int-data-width-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_INT_DATA_WIDTH_C1 "xlnx,gt-ch3-int-data-width-c1" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_LINE_RATE_C0 "xlnx,gt-ch3-tx-line-rate-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_LINE_RATE_C1 "xlnx,gt-ch3-tx-line-rate-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_OUTCLK_SOURCE_C0 "xlnx,gt-ch3-tx-outclk-source-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_OUTCLK_SOURCE_C1 "xlnx,gt-ch3-tx-outclk-source-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_PLL_TYPE_C0 "xlnx,gt-ch3-tx-pll-type-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_PLL_TYPE_C1 "xlnx,gt-ch3-tx-pll-type-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_REFCLK_FREQUENCY_C0 "xlnx,gt-ch3-tx-refclk-frequency-c0" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_REFCLK_FREQUENCY_C1 "xlnx,gt-ch3-tx-refclk-frequency-c1" ${mrmac3_node} add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_USER_DATA_WIDTH_C0 "xlnx,gt-ch3-tx-user-data-width-c0" ${mrmac3_node} int add_prop_ifexists $drv_handle CONFIG.GT_CH3_TX_USER_DATA_WIDTH_C1 "xlnx,gt-ch3-tx-user-data-width-c1" ${mrmac3_node} int } proc generate_intr_info {drv_handle node fifo_ip} { set ips [get_cells -hier $drv_handle] foreach ip [get_drivers] { if {[string compare -nocase $ip $fifo_ip] == 0} { set target_handle $ip } } set intr_val [get_property CONFIG.interrupts $target_handle] set intr_parent [get_property CONFIG.interrupt-parent $target_handle] set int_names [get_property CONFIG.interrupt-names $target_handle] hsi::utils::add_new_dts_param "${node}" "interrupts" $intr_val int hsi::utils::add_new_dts_param "${node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${node}" "interrupt-names" $int_names stringlist } proc check_size {base node} { if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} { set temp $base set temp [string trimleft [string trimleft $temp 0] x] set len [string length $temp] set rem [expr {${len} - 8}] set high_base "0x[string range $temp $rem $len]" set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]" set low_base [format 0x%08x $low_base] set reg "$low_base $high_base" } else { set reg "$base" } return $reg } proc gen_mrmac_clk_property {drv_handle} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "microblaze"]} { return } set clocks "" set axi 0 set is_clk_wiz 0 set is_pl_clk 0 set updat "" global bus_clk_list set clocknames "" set clk_pins [get_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==clk&&DIRECTION==I || TYPE==gt_usrclk&&DIRECTION==I}] set ip [get_property IP_NAME [get_cells -hier $drv_handle]] foreach clk $clk_pins { set ip [get_cells -hier $drv_handle] set port_width [::hsi::utils::get_port_width $clk] set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] $clk]] if {$port_width >= 2} { for {set i 0} { $i < $port_width} {incr i} { set peri [::hsi::get_cells -of_objects $pins] set mrclk "$clk$i" if {[llength $peri]} { if {[string match -nocase [common::get_property IP_NAME $peri] "xlconcat"]} { set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects [get_cells $peri] In$i]] -filter "DIRECTION==O"] set clk_peri [::hsi::get_cells -of_objects $pins] } } set valid_clk_list "clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9" set pl_clk "" set clkout "" foreach pin $pins { if {[lsearch $valid_clk_list $pin] >= 0} { set clkout $pin set is_clk_wiz 1 set periph [::hsi::get_cells -of_objects $pin] } } if {[llength $clkout]} { set number [regexp -all -inline -- {[0-9]+} $clkout] set clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set axi_clk "s_axi_aclk" foreach clk1 $clk_wiz { if {[regexp $axi_clk $clk1 match]} { set axi 1 } } if {[string match -nocase $axi "0"]} { dtg_warning "no s_axi_aclk for clockwizard" set pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set clk_list "pl_clk*" set clk_pl "" set num "" foreach clk_wiz_pin $pins { set clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]] foreach pin $clk_wiz_pins { if {[regexp $clk_list $pin match]} { set clk_pl $pin } } } if {[llength $clk_pl]} { set num [regexp -all -inline -- {[0-9]+} $clk_pl] } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $num { "0" { set def_dts [get_property CONFIG.pcw_dts [get_os]] set fclk_node [add_or_get_dt_node -n "&fclk0" -d $def_dts] hsi::utils::add_new_dts_param "${fclk_node}" "status" "okay" string } "1" { set def_dts [get_property CONFIG.pcw_dts [get_os]] set fclk_node [add_or_get_dt_node -n "&fclk1" -d $def_dts] hsi::utils::add_new_dts_param "${fclk_node}" "status" "okay" string } "2" { set def_dts [get_property CONFIG.pcw_dts [get_os]] set fclk_node [add_or_get_dt_node -n "&fclk2" -d $def_dts] hsi::utils::add_new_dts_param "${fclk_node}" "status" "okay" string } "3" { set def_dts [get_property CONFIG.pcw_dts [get_os]] set fclk_node [add_or_get_dt_node -n "&fclk3" -d $def_dts] hsi::utils::add_new_dts_param "${fclk_node}" "status" "okay" string } } } set dts_file "pl.dtsi" set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL" continue } set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } if {![string match -nocase $axi "0"]} { switch $number { "1" { set peri "$periph 0" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "2" { set peri "$periph 1" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "3" { set peri "$periph 2" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "4" { set peri "$periph 3" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "5" { set peri "$periph 4" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "6" { set peri "$periph 5" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "7" { set peri "$periph 6" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } } } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } elseif {[string match -nocase $proctype "ps7_cortexa9"]} { set clklist "FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3" } foreach pin $pins { if {[lsearch $clklist $pin] >= 0} { set pl_clk $pin set is_pl_clk 1 } } if {[string match -nocase $proctype "psv_cortexa72"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "zynqmp_clk 71" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "zynqmp_clk 72" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "zynqmp_clk 73" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "zynqmp_clk 74" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "ps7_cortexa9"]} { switch $pl_clk { "FCLK_CLK0" { set pl_clk0 "clkc 15" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "FCLK_CLK1" { set pl_clk1 "clkc 16" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "FCLK_CLK2" { set pl_clk2 "clkc 17" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "FCLK_CLK3" { set pl_clk3 "clkc 18" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_debug "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $is_clk_wiz "0"]&& [string match -nocase $is_pl_clk "0"]} { set dts_file "pl.dtsi" set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL" continue } set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } append clocknames " " "$mrclk" set is_pl_clk 0 set is_clk_wiz 0 set axi 0 } } else { set valid_clk_list "clk_out0 clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 clk_out8 clk_out9" set pl_clk "" set clkout "" foreach pin $pins { if {[lsearch $valid_clk_list $pin] >= 0} { set clkout $pin set is_clk_wiz 1 set periph [::hsi::get_cells -of_objects $pin] } } if {[llength $clkout]} { set number [regexp -all -inline -- {[0-9]+} $clkout] set clk_wiz [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set axi_clk "s_axi_aclk" foreach clk1 $clk_wiz { if {[regexp $axi_clk $clk1 match]} { set axi 1 } } if {[string match -nocase $axi "0"]} { dtg_warning "no s_axi_aclk for clockwizard" set pins [get_pins -of_objects [get_cells -hier $periph] -filter TYPE==clk] set clk_list "pl_clk*" set clk_pl "" set num "" foreach clk_wiz_pin $pins { set clk_wiz_pins [get_pins -of_objects [get_nets -of_objects $clk_wiz_pin]] foreach pin $clk_wiz_pins { if {[regexp $clk_list $pin match]} { set clk_pl $pin } } } if {[llength $clk_pl]} { set num [regexp -all -inline -- {[0-9]+} $clk_pl] } set dts_file "pl.dtsi" set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL" continue } set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } if {![string match -nocase $axi "0"]} { switch $number { "1" { set peri "$periph 0" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "2" { set peri "$periph 1" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "3" { set peri "$periph 2" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "4" { set peri "$periph 3" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "5" { set peri "$periph 4" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "6" { set peri "$periph 5" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } "7" { set peri "$periph 6" set clocks [lappend clocks $peri] set updat [lappend updat $peri] } } } } if {[string match -nocase $proctype "psu_cortexa53"] || [string match -nocase $proctype "psv_cortexa72"]} { set clklist "pl_clk0 pl_clk1 pl_clk2 pl_clk3" } elseif {[string match -nocase $proctype "ps7_cortexa9"]} { set clklist "FCLK_CLK0 FCLK_CLK1 FCLK_CLK2 FCLK_CLK3" } foreach pin $pins { if {[lsearch $clklist $pin] >= 0} { set pl_clk $pin set is_pl_clk 1 } } if {[string match -nocase $proctype "psv_cortexa72"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "versal_clk 65" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "versal_clk 66" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "versal_clk 67" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "versal_clk 68" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "psu_cortexa53"]} { switch $pl_clk { "pl_clk0" { set pl_clk0 "zynqmp_clk 71" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "pl_clk1" { set pl_clk1 "zynqmp_clk 72" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "pl_clk2" { set pl_clk2 "zynqmp_clk 73" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "pl_clk3" { set pl_clk3 "zynqmp_clk 74" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $proctype "ps7_cortexa9"]} { switch $pl_clk { "FCLK_CLK0" { set pl_clk0 "clkc 15" set clocks [lappend clocks $pl_clk0] set updat [lappend updat $pl_clk0] } "FCLK_CLK1" { set pl_clk1 "clkc 16" set clocks [lappend clocks $pl_clk1] set updat [lappend updat $pl_clk1] } "FCLK_CLK2" { set pl_clk2 "clkc 17" set clocks [lappend clocks $pl_clk2] set updat [lappend updat $pl_clk2] } "FCLK_CLK3" { set pl_clk3 "clkc 18" set clocks [lappend clocks $pl_clk3] set updat [lappend updat $pl_clk3] } default { dtg_warning "not supported pl_clk:$pl_clk" } } } if {[string match -nocase $is_clk_wiz "0"]&& [string match -nocase $is_pl_clk "0"]} { set dts_file "pl.dtsi" set bus_node [add_or_get_bus_node $drv_handle $dts_file] set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "$clk"] if {[llength $clk_freq] == 0} { dtg_warning "clock frequency for the $clk is NULL" continue } set clk_freq [expr int($clk_freq)] set iptype [get_property IP_NAME [get_cells -hier $drv_handle]] if {![string equal $clk_freq ""]} { if {[lsearch $bus_clk_list $clk_freq] < 0} { set bus_clk_list [lappend bus_clk_list $clk_freq] } set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq] set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \ -d ${dts_file} -p ${bus_node}] set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}] set updat [lappend updat misc_clk_${bus_clk_cnt}] hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int } } append clocknames " " "$clk" set is_pl_clk 0 set is_clk_wiz 0 set axi 0 } } set_drv_prop_if_empty $drv_handle "zclock-names1" $clocknames stringlist set ip [get_property IP_NAME [get_cells -hier $drv_handle]] set refs [lindex $updat 0] for {set clk_count 1} {$clk_count < [llength $updat]} {incr clk_count +1} { append refs ">, <&[lindex $updat $clk_count]" } set_drv_prop $drv_handle "zclocks1" "$refs" reference } ================================================ FILE: multi_scaler/data/multi_scaler.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver multi_scaler OPTION supported_peripherals = (v_multi_scaler); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = multi_scaler; END driver ================================================ FILE: multi_scaler/data/multi_scaler.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-multi-scaler-v1.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set max_outs [get_property CONFIG.MAX_OUTS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-chan" $max_outs int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-width" $max_cols int set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,max-height" $max_rows int set taps [get_property CONFIG.TAPS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,num-taps" $taps int set aximm_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,dma-addr-width" $aximm_addr_width hexint set pixes_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]] set pixel $pixes_per_clock append pixel_per_clock "/bits/ 8 <$pixel>" hsi::utils::add_new_dts_param "$node" "xlnx,pixels-per-clock" $pixel_per_clock noformating set has_bgr8 [get_property CONFIG.HAS_BGR8 [get_cells -hier $drv_handle]] set vid_formats "" if {$has_bgr8 == 1} { append vid_formats " " "rgb888" } set has_bgra8 [get_property CONFIG.HAS_BGRA8 [get_cells -hier $drv_handle]] if {$has_bgra8 == 1} { append vid_formats " " "argb8888" } set has_bgrx8 [get_property CONFIG.HAS_BGRX8 [get_cells -hier $drv_handle]] if {$has_bgrx8 == 1} { append vid_formats " " "xrgb8888" } set has_rgb8 [get_property CONFIG.HAS_RGB8 [get_cells -hier $drv_handle]] if {$has_rgb8 == 1} { append vid_formats " " "bgr888" } set has_rgbx8 [get_property CONFIG.HAS_RGBX8 [get_cells -hier $drv_handle]] if {$has_rgbx8 == 1} { append vid_formats " " "xbgr8888" } set has_rgba8 [get_property CONFIG.HAS_RGBA8 [get_cells -hier $drv_handle]] if {$has_rgba8 == 1} { append vid_formats " " "abgr8888" } set has_rgbx10 [get_property CONFIG.HAS_RGBX10 [get_cells -hier $drv_handle]] if {$has_rgbx10 == 1} { append vid_formats " " "xbgr2101010" } set has_uyuy8 [get_property CONFIG.HAS_UYVY8 [get_cells -hier $drv_handle]] if {$has_uyuy8 == 1} { append vid_formats " " "uyvy" } set has_y8 [get_property CONFIG.HAS_Y8 [get_cells -hier $drv_handle]] if {$has_y8 == 1} { append vid_formats " " "y8" } set has_y10 [get_property CONFIG.HAS_Y10 [get_cells -hier $drv_handle]] if {$has_y10 == 1} { append vid_formats " " "y10" } set has_yuv8 [get_property CONFIG.HAS_YUV8 [get_cells -hier $drv_handle]] if {$has_yuv8 == 1} { append vid_formats " " "vuy888" } set has_yuvx8 [get_property CONFIG.HAS_YUVX8 [get_cells -hier $drv_handle]] if {$has_yuvx8 == 1} { append vid_formats " " "xvuy8888" } set has_yuva8 [get_property CONFIG.HAS_YUVA8 [get_cells -hier $drv_handle]] if {$has_yuva8 == 1} { append vid_formats " " "avuy8888" } set has_yuvx10 [get_property CONFIG.HAS_YUVX10 [get_cells -hier $drv_handle]] if {$has_yuvx10 == 1} { append vid_formats " " "yuvx2101010" } set has_yuyv8 [get_property CONFIG.HAS_YUYV8 [get_cells -hier $drv_handle]] if {$has_yuyv8 == 1} { append vid_formats " " "yuyv" } set has_y_uv8_420 [get_property CONFIG.HAS_Y_UV8_420 [get_cells -hier $drv_handle]] if {$has_y_uv8_420 == 1} { append vid_formats " " "nv12" } set has_y_uv8 [get_property CONFIG.HAS_Y_UV8 [get_cells -hier $drv_handle]] if {$has_y_uv8 == 1} { append vid_formats " " "nv16" } set has_y_uv10 [get_property CONFIG.HAS_Y_UV10 [get_cells -hier $drv_handle]] if {$has_y_uv10 == 1} { append vid_formats " " "xv20" } set has_y_uv10_420 [get_property CONFIG.HAS_Y_UV10_420 [get_cells -hier $drv_handle]] if {$has_y_uv10_420 == 1} { append vid_formats " " "xv15" } hsi::utils::add_new_dts_param "${node}" "xlnx,vid-formats" $vid_formats stringlist gen_gpio_reset $drv_handle $node } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only one bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: nandps/data/nandps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver nandps OPTION supported_peripherals = (ps7_nand psu_nand psv_nand); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = nandps; END driver ================================================ FILE: nandps/data/nandps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc ns_to_cycle {drv_handle prop_name nand_cycle_time} { return [expr [get_property CONFIG.$prop_name [get_cells -hier $drv_handle]]/${nand_cycle_time}] } proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set hw_ver [get_hw_version] # Parameter name changed in 2014.4 # TODO: check with 2014.3 switch -exact $hw_ver { "2014.2" { set nand_par_prefix "C_NAND_CYCLE_" set nand_cycle_time 1 } "2014.4" - default { set nand_par_prefix "NAND-CYCLE-" set nand_cycle_time [expr "1000000000/[get_property CONFIG.C_NAND_CLK_FREQ_HZ [get_cells -hier $drv_handle]]"] } } if {![regexp -nocase "psu_nand*" $drv_handle match]} { set_drv_prop $drv_handle "arm,nand-cycle-t0" [ns_to_cycle $drv_handle "${nand_par_prefix}T0" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t1" [ns_to_cycle $drv_handle "${nand_par_prefix}T1" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t2" [ns_to_cycle $drv_handle "${nand_par_prefix}T2" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t3" [ns_to_cycle $drv_handle "${nand_par_prefix}T3" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t4" [ns_to_cycle $drv_handle "${nand_par_prefix}T4" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t5" [ns_to_cycle $drv_handle "${nand_par_prefix}T5" $nand_cycle_time] set_drv_prop $drv_handle "arm,nand-cycle-t6" [ns_to_cycle $drv_handle "${nand_par_prefix}T6" $nand_cycle_time] set bus_width [get_property CONFIG.C_NAND_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_property $drv_handle "nand-bus-width" int $bus_width } } ================================================ FILE: norps/data/norps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver norps OPTION supported_peripherals = (ps7_sram); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = norps; DTGPARAM name = bank-width, type = int, default = 1; END driver ================================================ FILE: norps/data/norps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } # TODO: if addr25 is used, should we consider set the reg size to 64MB? # enable reg generation for ps ip gen_reg_property $drv_handle "enable_ps_ip" } ================================================ FILE: nvme_aggr/data/nvme_aggr.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver nvme_aggr OPTION supported_peripherals = (nvme_subsystem); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = nvme_aggr; END driver ================================================ FILE: nvme_aggr/data/nvme_aggr.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set proc_type [get_sw_proc_prop IP_NAME] set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set nvme_ip [get_cells -hier $drv_handle] set ip_name [get_property IP_NAME $nvme_ip] if {[string match -nocase $proc_type "psu_cortexa53"] || [string match -nocase $proc_type "psv_cortexa72"] || [string match -nocase $proc_type "psx_cortexa78"]} { hsi::utils::add_new_dts_param $node "#address-cells" 2 int hsi::utils::add_new_dts_param $node "#size-cells" 2 int hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean } elseif {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"]} { hsi::utils::add_new_dts_param $node "#address-cells" 1 int hsi::utils::add_new_dts_param $node "#size-cells" 1 int hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean } set intr_val [get_property CONFIG.interrupts $drv_handle] set intr_parent [get_property CONFIG.interrupt-parent $drv_handle] set intr_names [get_property CONFIG.interrupt-names $drv_handle] set ha_intr "" set tc_intr "" set mapper_intr "" foreach intr1 $intr_names { if {[string match -nocase $intr1 "hc_interrupt"]} { lappend ha_intr $intr1 } if {[string match -nocase $intr1 "nvme_tc_intr"]} { lappend tc_intr $intr1 } if {[string match -nocase $intr1 "mapper_interrupt"]} { lappend tc_intr $intr1 } } set periph_list [get_cells -hier] set nvme_inst_name [get_cells -filter {IP_NAME =~ "*nvme*"}] foreach periph $periph_list { if {[string match -nocase "${nvme_inst_name}_nvmeha_0" $periph] } { set addr [get_property CONFIG.HA_S_AXI_LITE_OFFSET $nvme_ip] set addr [format %0x $addr] gen_ha_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $ha_intr } if {[string match -nocase "${nvme_inst_name}_nvme_tc_0" $periph] } { set addr [get_property CONFIG.TC_S_AXI_LITE_OFFSET $nvme_ip] set addr [format %0x $addr] gen_tc_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $tc_intr } if {[string match -nocase "${nvme_inst_name}_nvme_mapper_0" $periph] } { set addr [get_property CONFIG.MAPER_S_AXI_LITE_OFFSET $nvme_ip] set addr [format %0x $addr] gen_mapper_node $periph $addr $node $drv_handle $proc_type $nvme_ip $intr_parent $mapper_intr } } } proc gen_ha_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} { set ha_node [add_or_get_dt_node -n "nvme_ha" -l nvme_ha_0 -u $addr -p $parent_node] set lite_size [get_property CONFIG.HA_S_AXI_LITE_SIZE $nvme_ip] set full_off [get_property CONFIG.HA_SW_S_AXI_OFFSET $nvme_ip] set full_size [get_property CONFIG.HA_SW_S_AXI_SIZE $nvme_ip] set ssd_off [get_property CONFIG.HA_S_AXI_SSD_OFFSET $nvme_ip] set ssd_size [get_property CONFIG.HA_S_AXI_SSD_SIZE $nvme_ip] if {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"]} { set ha_reg "0x$addr $lite_size $full_off $full_size $ssd_off $ssd_size" } else { set ha_reg "0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size 0x0 $ssd_off 0x0 $ssd_size" } hsi::utils::add_new_dts_param "${ha_node}" "reg" $ha_reg int hsi::utils::add_new_dts_param "${ha_node}" "compatible" "xlnx,nvmeha-1.0" string set intr_len [llength $intr] for {set i 0} {$i < $intr_len} {incr i} { lappend intr_num [get_intr_id $nvme_ip [lindex $intr $i]] } regsub -all "\{||\t" $intr_num {} intr_num regsub -all "\}||\t" $intr_num {} intr_num hsi::utils::add_new_dts_param ${ha_node} "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${ha_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${ha_node}" "interrupt-names" $intr stringlist gen_property "CONFIG.C_NUM_SQ" "xlnx,num-sq" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_0" "xlnx,num-sq-hw-0" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_1" "xlnx,num-sq-hw-1" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_2" "xlnx,num-sq-hw-2" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_3" "xlnx,num-sq-hw-3" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_4" "xlnx,num-sq-hw-4" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_5" "xlnx,num-sq-hw-5" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_6" "xlnx,num-sq-hw-6" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_7" "xlnx,num-sq-hw-7" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_8" "xlnx,num-sq-hw-8" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_9" "xlnx,num-sq-hw-9" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_10" "xlnx,num-sq-hw-10" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_11" "xlnx,num-sq-hw-11" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_12" "xlnx,num-sq-hw-12" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_13" "xlnx,num-sq-hw-13" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_14" "xlnx,num-sq-hw-14" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_15" "xlnx,num-sq-hw-15" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_16" "xlnx,num-sq-hw-16" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_17" "xlnx,num-sq-hw-17" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_18" "xlnx,num-sq-hw-18" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_19" "xlnx,num-sq-hw-19" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_20" "xlnx,num-sq-hw-20" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_21" "xlnx,num-sq-hw-21" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_22" "xlnx,num-sq-hw-22" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_23" "xlnx,num-sq-hw-23" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_24" "xlnx,num-sq-hw-24" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_25" "xlnx,num-sq-hw-25" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_26" "xlnx,num-sq-hw-26" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_27" "xlnx,num-sq-hw-27" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_28" "xlnx,num-sq-hw-28" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_29" "xlnx,num-sq-hw-29" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_30" "xlnx,num-sq-hw-30" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_HW_31" "xlnx,num-sq-hw-31" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_0" "xlnx,num-sq-sw-0" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_1" "xlnx,num-sq-sw-1" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_2" "xlnx,num-sq-sw-2" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_3" "xlnx,num-sq-sw-3" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_4" "xlnx,num-sq-sw-4" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_5" "xlnx,num-sq-sw-5" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_6" "xlnx,num-sq-sw-6" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_7" "xlnx,num-sq-sw-7" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_8" "xlnx,num-sq-sw-8" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_9" "xlnx,num-sq-sw-9" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_10" "xlnx,num-sq-sw-10" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_11" "xlnx,num-sq-sw-11" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_12" "xlnx,num-sq-sw-12" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_13" "xlnx,num-sq-sw-13" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_14" "xlnx,num-sq-sw-14" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_15" "xlnx,num-sq-sw-15" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_16" "xlnx,num-sq-sw-16" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_17" "xlnx,num-sq-sw-17" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_18" "xlnx,num-sq-sw-18" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_19" "xlnx,num-sq-sw-19" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_20" "xlnx,num-sq-sw-20" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_21" "xlnx,num-sq-sw-21" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_22" "xlnx,num-sq-sw-22" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_23" "xlnx,num-sq-sw-23" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_24" "xlnx,num-sq-sw-24" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_25" "xlnx,num-sq-sw-25" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_26" "xlnx,num-sq-sw-26" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_27" "xlnx,num-sq-sw-27" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_28" "xlnx,num-sq-sw-28" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_29" "xlnx,num-sq-sw-29" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_30" "xlnx,num-sq-sw-30" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SQ_SW_31" "xlnx,num-sq-sw-31" $nvme_ip $ha_node gen_property "CONFIG.C_NUM_SSD" "xlnx,num-ssd" $nvme_ip $ha_node gen_property "CONFIG.C_SQ_DEPTH_HW" "xlnx,sq-depth-hw" $nvme_ip $ha_node gen_property "CONFIG.C_SQ_DEPTH_SW" "xlnx,sq-depth-sw" $nvme_ip $ha_node } proc gen_tc_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} { set tc_node [add_or_get_dt_node -n "nvme_tc" -l nvme_tc_0 -u $addr -p $parent_node] set lite_size [get_property CONFIG.TC_S_AXI_LITE_SIZE $nvme_ip] set full_off [get_property CONFIG.TC_SW_S_AXI_OFFSET $nvme_ip] set full_size [get_property CONFIG.TC_SW_S_AXI_SIZE $nvme_ip] if {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"]} { set tc_reg "0x$addr $lite_size $full_off $full_size" } else { set tc_reg "0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size" } hsi::utils::add_new_dts_param "${tc_node}" "reg" $tc_reg int hsi::utils::add_new_dts_param "${tc_node}" "compatible" "xlnx,nvme-tc-1.0" string set intr_len [llength $intr] for {set i 0} {$i < $intr_len} {incr i} { lappend intr_num [get_intr_id $nvme_ip [lindex $intr $i]] } regsub -all "\{||\t" $intr_num {} intr_num regsub -all "\}||\t" $intr_num {} intr_num hsi::utils::add_new_dts_param ${tc_node} "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${tc_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${tc_node}" "interrupt-names" $intr stringlist set debug_en [get_property CONFIG.DEBUG_EN $nvme_ip] if {[string match -nocase $debug_en "true"]} { hsi::utils::add_new_dts_param "${tc_node}" "xlnx,debug-en" "0x1" int } else { hsi::utils::add_new_dts_param "${tc_node}" "xlnx,debug-en" "0x0" int } gen_property "CONFIG.C_ARB_BURST" "xlnx,arb-burst" $nvme_ip $tc_node gen_property "CONFIG.C_CAP_MAX_HOST_Q_DEPTH" "xlnx,cap-max-host-q-depth" $nvme_ip $tc_node gen_property "CONFIG.C_CAP_MPSMAX" "xlnx,cap-mpsmax" $nvme_ip $tc_node gen_property "CONFIG.C_CAP_MPSMIN" "xlnx,cap-mpsmin" $nvme_ip $tc_node gen_property "CONFIG.C_CAP_TIMEOUT" "xlnx,cap-timeout" $nvme_ip $tc_node gen_property "CONFIG.C_LBA_DATA_SIZE" "xlnx,lba-data-size" $nvme_ip $tc_node gen_property "CONFIG.C_MAX_DMA_SIZE" "xlnx,max-dma-size" $nvme_ip $tc_node gen_property "CONFIG.C_MDTS" "xlnx,mdts" $nvme_ip $tc_node gen_property "CONFIG.C_NUM_CMD_INDX" "xlnx,num-cmd-indx" $nvme_ip $tc_node gen_property "CONFIG.C_NUM_FUNC" "xlnx,num-func" $nvme_ip $tc_node gen_property "CONFIG.C_NUM_HSQ" "xlnx,num-hsq" $nvme_ip $tc_node gen_property "CONFIG.C_NUM_SGLS_PER_INDX" "xlnx,num-sgls-per-indx" $nvme_ip $tc_node gen_property "CONFIG.C_PERF_MON_EN" "xlnx,perf-mon-en" $nvme_ip $tc_node gen_property "CONFIG.C_S_AXI_ID_WIDTH" "xlnx,s-axi-id-width" $nvme_ip $tc_node gen_property "CONFIG.C_SGL_SUPPORT" "xlnx,sgl-support" $nvme_ip $tc_node } proc gen_mapper_node {periph addr parent_node drv_handle proc_type nvme_ip intr_parent intr} { set mapper_node [add_or_get_dt_node -n "nvme_mapper" -l nvme_mapper_0 -u $addr -p $parent_node] set lite_size [get_property CONFIG.MAPPER_S_AXI_LITE_SIZE $nvme_ip] set full_off [get_property CONFIG.MAPPER_SW_S_AXI_OFFSET $nvme_ip] set full_size [get_property CONFIG.MAPPER_SW_S_AXI_SIZE $nvme_ip] if {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"]} { set mapper_reg "0x$addr $lite_size $full_off $full_size" } else { set mapper_reg "0x0 0x$addr 0x0 $lite_size 0x0 $full_off 0x0 $full_size" } hsi::utils::add_new_dts_param "${mapper_node}" "reg" $mapper_reg int hsi::utils::add_new_dts_param "${mapper_node}" "compatible" "xlnx,nvme-mapper-1.0" string set en_p2p [get_property CONFIG.EN_P2P_BUFFERS $nvme_ip] if {[string match -nocase $en_p2p "true"]} { hsi::utils::add_new_dts_param "${mapper_node}" "xlnx,en-p2p-buffer" "" boolean } gen_property "CONFIG.MAX_PRP_PER_CMD" "xlnx,max-prp-per-cmd" $periph $mapper_node gen_property "CONFIG.NUM_UID_SUPPORT" "xlnx,num-uid-support" $periph $mapper_node gen_property "CONFIG.P2P_PF_NUM" "xlnx,p2p-pf-num" $periph $mapper_node } proc gen_property {property pro_dt_name nvme_ip node} { set num_sgls [get_property $property $nvme_ip] set num_sgls 0x[format %0x $num_sgls] hsi::utils::add_new_dts_param "$node" $pro_dt_name $num_sgls int } ================================================ FILE: ocmcps/data/ocmcps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ocmcps OPTION supported_peripherals = (ps7_ocmc psu_ocm psv_ocm psx_ocm); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ocmcps; END driver ================================================ FILE: ocmcps/data/ocmcps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: ospips/data/ospips.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ospips OPTION supported_peripherals = (psu_ospi psv_pmc_ospi psx_pmc_ospi); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ospips; DTGPARAM name = dtg.alias , default = spi; END driver ================================================ FILE: ospips/data/ospips.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ospi_handle [get_cells -hier $drv_handle] set ospi_mode [hsi::utils::get_ip_param_value $ospi_handle "C_OSPI_MODE"] set is_stacked 0 set is_dual 0 if {$ospi_mode == 1} { set is_stacked 1 } set_property CONFIG.is-dual $is_dual $drv_handle set_property CONFIG.is-stacked $is_stacked $drv_handle } ================================================ FILE: pl310ps/data/pl310ps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver pl310ps OPTION supported_peripherals = (ps7_pl310); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = pl310ps; END driver ================================================ FILE: pl310ps/data/pl310ps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: pmups/data/pmups.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver pmups OPTION supported_peripherals = (ps7_pmu); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = pmups; END driver ================================================ FILE: pmups/data/pmups.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: pr_decoupler/data/pr_decoupler.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver pr_decoupler OPTION supported_peripherals = (pr_decoupler dfx_decoupler); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = pr_decoupler; END driver ================================================ FILE: pr_decoupler/data/pr_decoupler.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,pr-decoupler"] set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.mdd ================================================ # # (C) Copyright 2021-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ptp_1588_timer_syncer OPTION supported_peripherals = (ptp_1588_timer_syncer); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ptp_1588_timer_syncer; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: ptp_1588_timer_syncer/data/ptp_1588_timer_syncer.tcl ================================================ # # (C) Copyright 2021-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set ip_ver [get_comp_ver $drv_handle] if {[string match -nocase $ip_ver "2.0"] || [string match -nocase $ip_ver "3.0"]} { set compatible [append compatible " " "xlnx,timer-syncer-1588-3.0"] } elseif {[string match -nocase $ip_ver "1.0"]} { set compatible [append compatible " " "xlnx,timer-syncer-1588-1.0"] } set_drv_prop $drv_handle compatible "$compatible" stringlist } ================================================ FILE: qspips/data/qspips.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver qspips OPTION supported_peripherals = (ps7_qspi psu_qspi psv_pmc_qspi psx_pmc_qspi); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = qspips; DTGPARAM name = is-dual, type = int; DTGPARAM name = dtg.alias , default = spi; END driver ================================================ FILE: qspips/data/qspips.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set slave [get_cells -hier $drv_handle] set qspi_mode [hsi::utils::get_ip_param_value $slave "C_QSPI_MODE"] #for versal setting spi-max-frequency to 40MHZ if fbclk disabled in design set pspmc [get_cells -hier -filter {IP_NAME == "pspmc"}] if {[llength $pspmc]} { set fbclk [get_property CONFIG.PMC_QSPI_FBCLK [get_cells -hier $pspmc]] if {[llength $fbclk]} { if {[regexp "ENABLE 0" $fbclk matched]} { set_spi_max_frequency $drv_handle } } } #for versal-net setting spi-max-frequency to 40MHZ if fbclk disabled in design set psxwizard [get_cells -hier -filter {IP_NAME == "psx_wizard"}] if {[llength $psxwizard]} { set psx_pmcx_config [get_property CONFIG.PSX_PMCX_CONFIG [get_cells -hier $psxwizard]] if {[llength $psx_pmcx_config]} { set qspi_fbclk "" if {[dict exists $psx_pmcx_config "PMCX_QSPI_FBCLK"]} { set qspi_fbclk [dict get $psx_pmcx_config "PMCX_QSPI_FBCLK"] set qspi_fbclk_enabled "" if {[dict exists $qspi_fbclk "ENABLE"]} { set qspi_fbclk_enabled [dict get $qspi_fbclk "ENABLE"] if {$qspi_fbclk_enabled == 0} { set_spi_max_frequency $drv_handle } } } } } set is_stacked 0 if { $qspi_mode == 2} { set is_dual 1 } elseif { $qspi_mode == 1} { set is_dual 0 set is_stacked 1 } elseif { $qspi_mode == 0} { set is_dual 0 } set_property CONFIG.is-dual $is_dual $drv_handle # Set num-cs value to 2 if qspi is dual/stacked else 1 set numcs 1 if { $is_dual == 1 || $is_stacked == 1 } { set numcs 2 } hsi::utils::add_new_property $drv_handle "num-cs" int $numcs if {$is_stacked} { set_property CONFIG.is-stacked $is_stacked $drv_handle } set bus_width [get_property CONFIG.C_QSPI_BUS_WIDTH [get_cells -hier $drv_handle]] switch $bus_width { "3" { hsi::utils::add_new_property $drv_handle "spi-tx-bus-width" int 8 hsi::utils::add_new_property $drv_handle "spi-rx-bus-width" int 8 } "2" { hsi::utils::add_new_property $drv_handle "spi-tx-bus-width" int 4 hsi::utils::add_new_property $drv_handle "spi-rx-bus-width" int 4 } "1" { hsi::utils::add_new_property $drv_handle "spi-tx-bus-width" int 2 hsi::utils::add_new_property $drv_handle "spi-rx-bus-width" int 2 } "0" { hsi::utils::add_new_property $drv_handle "spi-tx-bus-width" int 1 hsi::utils::add_new_property $drv_handle "spi-rx-bus-width" int 1 } default { dtg_warning "Unsupported bus_width:$bus_width" } } # these are board level information # set primary_flash [hsi::utils::add_new_child_node $drv_handle "primary_flash"] # hsi::utils::add_new_property $primary_flash "dts.device_type" string "ps7-qspi" # hsi::utils::add_new_property $primary_flash reg hexint 0 # hsi::utils::add_new_property $primary_flash spi-max-frequency int 50000000 } #when fbclk disabled in the design #this function will set the spi-max-freq to 40MHZ proc set_spi_max_frequency {drv_handle} { set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } hsi::utils::add_new_dts_param "${node}" "/* hw design is missing feedback clock that's why spi-max-frequency is 40MHz */" "" comment hsi::utils::add_new_property $drv_handle spi-max-frequency int 40000000 } ================================================ FILE: ramps/data/ramps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ramps OPTION supported_peripherals = (ps7_ram); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ramps; DTGPARAM name = compatible, type = stringlist, default = "xlnx,ps7-ocm" ; DTGPARAM name = reg, type = hexintlist , default = "0xfffc0000 0x40000"; END driver ================================================ FILE: ramps/data/ramps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { set ip [get_cells -hier $drv_handle] if { [string match -nocase $ip "ps7_ram_1"] } { set_property NAME none $drv_handle } } ================================================ FILE: rfdc/data/rfdc.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver rfdc OPTION supported_peripherals = (usp_rf_data_converter); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = rfdc; END driver ================================================ FILE: rfdc/data/rfdc.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set instances [llength [::hsi::utils::get_common_driver_ips $drv_handle]] hsi::utils::add_new_property $drv_handle "num-insts" hexlist $instances add_param_list_property $drv_handle "DEVICE_ID" "C_BASEADDR" "C_High_Speed_ADC" "C_Sysref_Master" "C_Sysref_Master" "C_Sysref_Source" "C_Sysref_Source" "C_IP_Type" "C_Silicon_Revision" \ "C_DAC0_Enable" "C_DAC0_PLL_Enable" "C_DAC0_Sampling_Rate" "C_DAC0_Refclk_Freq" "C_DAC0_Fabric_Freq" "C_DAC0_FBDIV" "C_DAC0_OutDiv" "C_DAC0_Refclk_Div" "C_DAC0_Band" "C_DAC0_Fs_Max" "C_DAC0_Slices" "DAC0_Link_Coupling" \ "C_DAC_Slice00_Enable" "C_DAC_Invsinc_Ctrl00" "C_DAC_Mixer_Mode00" "C_DAC_Decoder_Mode00" \ "C_DAC_Slice01_Enable" "C_DAC_Invsinc_Ctrl01" "C_DAC_Mixer_Mode01" "C_DAC_Decoder_Mode01" \ "C_DAC_Slice02_Enable" "C_DAC_Invsinc_Ctrl02" "C_DAC_Mixer_Mode02" "C_DAC_Decoder_Mode02" \ "C_DAC_Slice03_Enable" "C_DAC_Invsinc_Ctrl03" "C_DAC_Mixer_Mode03" "C_DAC_Decoder_Mode03" \ "C_DAC_Data_Type00" "C_DAC_Data_Width00" "C_DAC_Interpolation_Mode00" "C_DAC_Fifo00_Enable" "C_DAC_Adder00_Enable" "C_DAC_Mixer_Type00" "C_DAC_NCO_Freq00" \ "C_DAC_Data_Type01" "C_DAC_Data_Width01" "C_DAC_Interpolation_Mode01" "C_DAC_Fifo01_Enable" "C_DAC_Adder01_Enable" "C_DAC_Mixer_Type01" "C_DAC_NCO_Freq01" \ "C_DAC_Data_Type02" "C_DAC_Data_Width02" "C_DAC_Interpolation_Mode02" "C_DAC_Fifo02_Enable" "C_DAC_Adder02_Enable" "C_DAC_Mixer_Type02" "C_DAC_NCO_Freq02" \ "C_DAC_Data_Type03" "C_DAC_Data_Width03" "C_DAC_Interpolation_Mode03" "C_DAC_Fifo03_Enable" "C_DAC_Adder03_Enable" "C_DAC_Mixer_Type03" "C_DAC_NCO_Freq03" \ "C_DAC1_Enable" "C_DAC1_PLL_Enable" "C_DAC1_Sampling_Rate" "C_DAC1_Refclk_Freq" "C_DAC1_Fabric_Freq" "C_DAC1_FBDIV" "C_DAC1_OutDiv" "C_DAC1_Refclk_Div" "C_DAC1_Band" "C_DAC1_Fs_Max" "C_DAC1_Slices" "DAC1_Link_Coupling" \ "C_DAC_Slice10_Enable" "C_DAC_Invsinc_Ctrl10" "C_DAC_Mixer_Mode10" "C_DAC_Decoder_Mode10" \ "C_DAC_Slice11_Enable" "C_DAC_Invsinc_Ctrl11" "C_DAC_Mixer_Mode11" "C_DAC_Decoder_Mode11" \ "C_DAC_Slice12_Enable" "C_DAC_Invsinc_Ctrl12" "C_DAC_Mixer_Mode12" "C_DAC_Decoder_Mode12" \ "C_DAC_Slice13_Enable" "C_DAC_Invsinc_Ctrl13" "C_DAC_Mixer_Mode13" "C_DAC_Decoder_Mode13" \ "C_DAC_Data_Type10" "C_DAC_Data_Width10" "C_DAC_Interpolation_Mode10" "C_DAC_Fifo10_Enable" "C_DAC_Adder10_Enable" "C_DAC_Mixer_Type10" "C_DAC_NCO_Freq10" \ "C_DAC_Data_Type11" "C_DAC_Data_Width11" "C_DAC_Interpolation_Mode11" "C_DAC_Fifo11_Enable" "C_DAC_Adder11_Enable" "C_DAC_Mixer_Type11" "C_DAC_NCO_Freq11" \ "C_DAC_Data_Type12" "C_DAC_Data_Width12" "C_DAC_Interpolation_Mode12" "C_DAC_Fifo12_Enable" "C_DAC_Adder12_Enable" "C_DAC_Mixer_Type12" "C_DAC_NCO_Freq12" \ "C_DAC_Data_Type13" "C_DAC_Data_Width13" "C_DAC_Interpolation_Mode13" "C_DAC_Fifo13_Enable" "C_DAC_Adder13_Enable" "C_DAC_Mixer_Type13" "C_DAC_NCO_Freq13" \ "C_DAC2_Enable" "C_DAC2_PLL_Enable" "C_DAC2_Sampling_Rate" "C_DAC2_Refclk_Freq" "C_DAC2_Fabric_Freq" "C_DAC2_FBDIV" "C_DAC2_OutDiv" "C_DAC2_Refclk_Div" "C_DAC2_Band" "C_DAC2_Fs_Max" "C_DAC2_Slices" "DAC2_Link_Coupling" \ "C_DAC_Slice20_Enable" "C_DAC_Invsinc_Ctrl20" "C_DAC_Mixer_Mode20" "C_DAC_Decoder_Mode20" \ "C_DAC_Slice21_Enable" "C_DAC_Invsinc_Ctrl21" "C_DAC_Mixer_Mode21" "C_DAC_Decoder_Mode21" \ "C_DAC_Slice22_Enable" "C_DAC_Invsinc_Ctrl22" "C_DAC_Mixer_Mode22" "C_DAC_Decoder_Mode22" \ "C_DAC_Slice23_Enable" "C_DAC_Invsinc_Ctrl23" "C_DAC_Mixer_Mode23" "C_DAC_Decoder_Mode23" \ "C_DAC_Data_Type20" "C_DAC_Data_Width20" "C_DAC_Interpolation_Mode20" "C_DAC_Fifo20_Enable" "C_DAC_Adder20_Enable" "C_DAC_Mixer_Type20" "C_DAC_NCO_Freq20" \ "C_DAC_Data_Type21" "C_DAC_Data_Width21" "C_DAC_Interpolation_Mode21" "C_DAC_Fifo21_Enable" "C_DAC_Adder21_Enable" "C_DAC_Mixer_Type21" "C_DAC_NCO_Freq21" \ "C_DAC_Data_Type22" "C_DAC_Data_Width22" "C_DAC_Interpolation_Mode22" "C_DAC_Fifo22_Enable" "C_DAC_Adder22_Enable" "C_DAC_Mixer_Type22" "C_DAC_NCO_Freq22" \ "C_DAC_Data_Type23" "C_DAC_Data_Width23" "C_DAC_Interpolation_Mode23" "C_DAC_Fifo23_Enable" "C_DAC_Adder23_Enable" "C_DAC_Mixer_Type23" "C_DAC_NCO_Freq23" \ "C_DAC3_Enable" "C_DAC3_PLL_Enable" "C_DAC3_Sampling_Rate" "C_DAC3_Refclk_Freq" "C_DAC3_Fabric_Freq" "C_DAC3_FBDIV" "C_DAC3_OutDiv" "C_DAC3_Refclk_Div" "C_DAC3_Band" "C_DAC3_Fs_Max" "C_DAC3_Slices" "DAC3_Link_Coupling" \ "C_DAC_Slice30_Enable" "C_DAC_Invsinc_Ctrl30" "C_DAC_Mixer_Mode30" "C_DAC_Decoder_Mode30" \ "C_DAC_Slice31_Enable" "C_DAC_Invsinc_Ctrl31" "C_DAC_Mixer_Mode31" "C_DAC_Decoder_Mode31" \ "C_DAC_Slice32_Enable" "C_DAC_Invsinc_Ctrl32" "C_DAC_Mixer_Mode32" "C_DAC_Decoder_Mode32" \ "C_DAC_Slice33_Enable" "C_DAC_Invsinc_Ctrl33" "C_DAC_Mixer_Mode33" "C_DAC_Decoder_Mode33" \ "C_DAC_Data_Type30" "C_DAC_Data_Width30" "C_DAC_Interpolation_Mode30" "C_DAC_Fifo30_Enable" "C_DAC_Adder30_Enable" "C_DAC_Mixer_Type30" "C_DAC_NCO_Freq30" \ "C_DAC_Data_Type31" "C_DAC_Data_Width31" "C_DAC_Interpolation_Mode31" "C_DAC_Fifo31_Enable" "C_DAC_Adder31_Enable" "C_DAC_Mixer_Type31" "C_DAC_NCO_Freq31" \ "C_DAC_Data_Type32" "C_DAC_Data_Width32" "C_DAC_Interpolation_Mode32" "C_DAC_Fifo32_Enable" "C_DAC_Adder32_Enable" "C_DAC_Mixer_Type32" "C_DAC_NCO_Freq32" \ "C_DAC_Data_Type33" "C_DAC_Data_Width33" "C_DAC_Interpolation_Mode33" "C_DAC_Fifo33_Enable" "C_DAC_Adder33_Enable" "C_DAC_Mixer_Type33" "C_DAC_NCO_Freq33" \ "C_ADC0_Enable" "C_ADC0_PLL_Enable" "C_ADC0_Sampling_Rate" "C_ADC0_Refclk_Freq" "C_ADC0_Fabric_Freq" "C_ADC0_FBDIV" "C_ADC0_OutDiv" "C_ADC0_Refclk_Div" "C_ADC0_Band" "C_ADC0_Fs_Max" "C_ADC0_Slices" \ "C_ADC_Slice00_Enable" "C_ADC_Mixer_Mode00" \ "C_ADC_Slice01_Enable" "C_ADC_Mixer_Mode01" \ "C_ADC_Slice02_Enable" "C_ADC_Mixer_Mode02" \ "C_ADC_Slice03_Enable" "C_ADC_Mixer_Mode03" \ "C_ADC_Data_Type00" "C_ADC_Data_Width00" "C_ADC_Decimation_Mode00" "C_ADC_Fifo00_Enable" "C_ADC_Mixer_Type00" "C_ADC_NCO_Freq00" \ "C_ADC_Data_Type01" "C_ADC_Data_Width01" "C_ADC_Decimation_Mode01" "C_ADC_Fifo01_Enable" "C_ADC_Mixer_Type01" "C_ADC_NCO_Freq01" \ "C_ADC_Data_Type02" "C_ADC_Data_Width02" "C_ADC_Decimation_Mode02" "C_ADC_Fifo02_Enable" "C_ADC_Mixer_Type02" "C_ADC_NCO_Freq02" \ "C_ADC_Data_Type03" "C_ADC_Data_Width03" "C_ADC_Decimation_Mode03" "C_ADC_Fifo03_Enable" "C_ADC_Mixer_Type03" "C_ADC_NCO_Freq03" \ "C_ADC1_Enable" "C_ADC1_PLL_Enable" "C_ADC1_Sampling_Rate" "C_ADC1_Refclk_Freq" "C_ADC1_Fabric_Freq" "C_ADC1_FBDIV" "C_ADC1_OutDiv" "C_ADC1_Refclk_Div" "C_ADC1_Band" "C_ADC1_Fs_Max" "C_ADC1_Slices" \ "C_ADC_Slice10_Enable" "C_ADC_Mixer_Mode10" \ "C_ADC_Slice11_Enable" "C_ADC_Mixer_Mode11" \ "C_ADC_Slice12_Enable" "C_ADC_Mixer_Mode12" \ "C_ADC_Slice13_Enable" "C_ADC_Mixer_Mode13" \ "C_ADC_Data_Type10" "C_ADC_Data_Width10" "C_ADC_Decimation_Mode10" "C_ADC_Fifo10_Enable" "C_ADC_Mixer_Type10" "C_ADC_NCO_Freq10" \ "C_ADC_Data_Type11" "C_ADC_Data_Width11" "C_ADC_Decimation_Mode11" "C_ADC_Fifo11_Enable" "C_ADC_Mixer_Type11" "C_ADC_NCO_Freq11" \ "C_ADC_Data_Type12" "C_ADC_Data_Width12" "C_ADC_Decimation_Mode12" "C_ADC_Fifo12_Enable" "C_ADC_Mixer_Type12" "C_ADC_NCO_Freq12" \ "C_ADC_Data_Type13" "C_ADC_Data_Width13" "C_ADC_Decimation_Mode13" "C_ADC_Fifo13_Enable" "C_ADC_Mixer_Type13" "C_ADC_NCO_Freq13" \ "C_ADC2_Enable" "C_ADC2_PLL_Enable" "C_ADC2_Sampling_Rate" "C_ADC2_Refclk_Freq" "C_ADC2_Fabric_Freq" "C_ADC2_FBDIV" "C_ADC2_OutDiv" "C_ADC2_Refclk_Div" "C_ADC2_Band" "C_ADC2_Fs_Max" "C_ADC2_Slices" \ "C_ADC_Slice20_Enable" "C_ADC_Mixer_Mode20" \ "C_ADC_Slice21_Enable" "C_ADC_Mixer_Mode21" \ "C_ADC_Slice22_Enable" "C_ADC_Mixer_Mode22" \ "C_ADC_Slice23_Enable" "C_ADC_Mixer_Mode23" \ "C_ADC_Data_Type20" "C_ADC_Data_Width20" "C_ADC_Decimation_Mode20" "C_ADC_Fifo20_Enable" "C_ADC_Mixer_Type20" "C_ADC_NCO_Freq20" \ "C_ADC_Data_Type21" "C_ADC_Data_Width21" "C_ADC_Decimation_Mode21" "C_ADC_Fifo21_Enable" "C_ADC_Mixer_Type21" "C_ADC_NCO_Freq21" \ "C_ADC_Data_Type22" "C_ADC_Data_Width22" "C_ADC_Decimation_Mode22" "C_ADC_Fifo22_Enable" "C_ADC_Mixer_Type22" "C_ADC_NCO_Freq22" \ "C_ADC_Data_Type23" "C_ADC_Data_Width23" "C_ADC_Decimation_Mode23" "C_ADC_Fifo23_Enable" "C_ADC_Mixer_Type23" "C_ADC_NCO_Freq23" \ "C_ADC3_Enable" "C_ADC3_PLL_Enable" "C_ADC3_Sampling_Rate" "C_ADC3_Refclk_Freq" "C_ADC3_Fabric_Freq" "C_ADC3_FBDIV" "C_ADC3_OutDiv" "C_ADC3_Refclk_Div" "C_ADC3_Band" "C_ADC3_Fs_Max" "C_ADC3_Slices" \ "C_ADC_Slice30_Enable" "C_ADC_Mixer_Mode30" \ "C_ADC_Slice31_Enable" "C_ADC_Mixer_Mode31" \ "C_ADC_Slice32_Enable" "C_ADC_Mixer_Mode32" \ "C_ADC_Slice33_Enable" "C_ADC_Mixer_Mode33" \ "C_ADC_Data_Type30" "C_ADC_Data_Width30" "C_ADC_Decimation_Mode30" "C_ADC_Fifo30_Enable" "C_ADC_Mixer_Type30" "C_ADC_NCO_Freq30" \ "C_ADC_Data_Type31" "C_ADC_Data_Width31" "C_ADC_Decimation_Mode31" "C_ADC_Fifo31_Enable" "C_ADC_Mixer_Type31" "C_ADC_NCO_Freq31" \ "C_ADC_Data_Type32" "C_ADC_Data_Width32" "C_ADC_Decimation_Mode32" "C_ADC_Fifo32_Enable" "C_ADC_Mixer_Type32" "C_ADC_NCO_Freq32" \ "C_ADC_Data_Type33" "C_ADC_Data_Width33" "C_ADC_Decimation_Mode33" "C_ADC_Fifo33_Enable" "C_ADC_Mixer_Type33" "C_ADC_NCO_Freq33" } proc convert_hex_string_to_byte_code {var} { return [string trimright [regsub -all {..} $var {& }]] } proc convert_double_to_le_byte_code_format {var} { set result "" set double [binary format q $var] binary scan $double H* result return [convert_hex_string_to_byte_code $result] } proc convert_int_to_le_byte_code_format {var} { set result "" set integer [binary format i $var] binary scan $integer H* result return [convert_hex_string_to_byte_code $result] } # # Given a list of arguments, add them in param-list property, # in byte code format # proc add_param_list_property {drv_handle args} { set args [::hsi::utils::get_exact_arg_list $args] # Get all peripherals connected to this driver set periphs [::hsi::utils::get_common_driver_ips $drv_handle] set device_id 0 foreach periph $periphs { if {[string compare -nocase $periph $drv_handle] == 0} { break } incr device_id } foreach arg $args { if {[string compare -nocase "DEVICE_ID" $arg] == 0} { set value $device_id } else { set value [common::get_property CONFIG.$arg $periph] } if {[llength $value] == 0} { set value 0 } if { [string first "_Sampling_Rate" $arg] > -1 || [string first "_Refclk_Freq" $arg] > -1 || [string first "_Fabric_Freq" $arg] > -1 || [string first "_Fs_Max" $arg] > -1 || [string match "*_NCO_Freq*" $arg]} { append data " " [convert_double_to_le_byte_code_format $value] } elseif { [string first "C_BASEADDR" $arg] > -1 } { set high_addr 0x00000000 #Check if address is greater than 4GB (i.e more than 32 bit) if {[regexp -nocase {([0-9a-f]{9})} "$value" match]} { set high_addr "0x[string range $value 10 17]" } set low_addr [string range $value 0 9] append data " " [convert_int_to_le_byte_code_format $low_addr] append data " " [convert_int_to_le_byte_code_format $high_addr] } else { if {[string compare -nocase "false" $value] == 0} { set value 0 } elseif {[string compare -nocase "true" $value] == 0} { set value 1 } append data " " [convert_int_to_le_byte_code_format $value] } } hsi::utils::add_new_property $drv_handle "param-list" bytelist $data } ================================================ FILE: scene_change_detector/data/scene_change_detector.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver scene_change_detector OPTION supported_peripherals = (v_scenechange); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = scene_change_detector; END driver ================================================ FILE: scene_change_detector/data/scene_change_detector.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible "xlnx,v-scd" set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-data-width" $max_data_width int set memory_scd [get_property CONFIG.MEMORY_BASED [get_cells -hier $drv_handle]] if {$memory_scd == 1} { set max_nr_streams [get_property CONFIG.MAX_NR_STREAMS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,numstreams" $max_nr_streams int hsi::utils::add_new_dts_param $node "#address-cells" 1 int hsi::utils::add_new_dts_param $node "#size-cells" 0 int hsi::utils::add_new_dts_param $node "xlnx,memorybased" "" boolean hsi::utils::add_new_dts_param "$node" "#dma-cells" 1 int set aximm_addr_width [get_property CONFIG.AXIMM_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,addrwidth" $aximm_addr_width hexint for {set stream 0} {$stream < $max_nr_streams} {incr stream} { set scd_node [add_or_get_dt_node -n "subdev@$stream" -p $node] set port_node [add_or_get_dt_node -n "port@0" -l port_$stream -p $scd_node] hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set endpoint [add_or_get_dt_node -n "endpoint" -l scd_in$stream -p $port_node] hsi::utils::add_new_dts_param "$endpoint" "remote-endpoint" vcap0_out$stream reference } set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set dts_file [current_dt_tree] set dma_names "" set dmas "" set vcap_scd [add_or_get_dt_node -n "video_cap" -l videocap -d $dts_file -p $bus_node] for {set stream 0} {$stream < $max_nr_streams} {incr stream} { append dma_names " " "port$stream" set peri "$drv_handle $stream" set dmas [lappend dmas $peri] } hsi::utils::add_new_dts_param "$vcap_scd" "dma-names" $dma_names stringlist generate_dmas $vcap_scd $dmas set ports_vcap [add_or_get_dt_node -n "ports" -l ports_vcap -p $vcap_scd] hsi::utils::add_new_dts_param $ports_vcap "#address-cells" 1 int hsi::utils::add_new_dts_param $ports_vcap "#size-cells" 0 int hsi::utils::add_new_dts_param $vcap_scd "compatible" "xlnx,video" string for {set stream 0} {$stream < $max_nr_streams} {incr stream} { set port_vcap_node [add_or_get_dt_node -n "port@$stream" -l port$stream -p $ports_vcap] hsi::utils::add_new_dts_param "$port_vcap_node" "reg" $stream int hsi::utils::add_new_dts_param "$port_vcap_node" "direction" output string set vcap_endpoint [add_or_get_dt_node -n "endpoint" -l vcap0_out$stream -p $port_vcap_node] hsi::utils::add_new_dts_param "$vcap_endpoint" "remote-endpoint" scd_in$stream reference } } else { set max_nr_streams [get_property CONFIG.MAX_NR_STREAMS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,numstreams" $max_nr_streams int hsi::utils::add_new_dts_param $node "#address-cells" 1 int hsi::utils::add_new_dts_param $node "#size-cells" 0 int set scd_ports_node [add_or_get_dt_node -n "scd" -l scd_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$scd_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$scd_ports_node" "#size-cells" 0 int set connect_out_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "M_AXIS_VIDEO"] if {![llength $connect_out_ip]} { dtg_warning "$drv_handle pin M_AXIS_VIDEO is not connected... check your design" } foreach connected_out_ip $connect_out_ip { if {[llength $connected_out_ip]} { if {[string match -nocase [get_property IP_NAME $connected_out_ip] "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connected_out_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connected_out_ip] if {[llength $ip_mem_handles]} { set scd_port1_node [add_or_get_dt_node -n "port" -l scd_port1$drv_handle -u 1 -p $scd_ports_node] hsi::utils::add_new_dts_param "$scd_port1_node" "reg" 1 int set scd_node [add_or_get_dt_node -n "endpoint" -l scd_out$drv_handle -p $scd_port1_node] hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $connected_out_ip$drv_handle reference if {[string match -nocase [get_property IP_NAME $connected_out_ip] "v_frmbuf_wr"]} { gen_frmbuf_node $connected_out_ip $drv_handle } } else { set connectip [get_connect_ip $connected_out_ip $master_intf] if {[llength $connectip]} { set scd_port1_node [add_or_get_dt_node -n "port" -l scd_port1$drv_handle -u 1 -p $scd_ports_node] hsi::utils::add_new_dts_param "$scd_port1_node" "reg" 1 int set scd_node [add_or_get_dt_node -n "endpoint" -l scd_out$drv_handle -p $scd_port1_node] hsi::utils::add_new_dts_param "$scd_node" "remote-endpoint" $connectip$drv_handle reference if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_node $connectip $drv_handle } } } } else { dtg_warning "$drv_handle pin M_AXIS_VIDEO is not connected... check your design" } } } gen_gpio_reset $drv_handle $node } proc gen_frmbuf_node {ip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$ip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $ip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" scd_out$drv_handle reference } proc generate_dmas {vcap_scd dmas} { set len [llength $dmas] switch $len { "1" { set refs [lindex $dmas 0] hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "2" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "3" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "4" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "5" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "6" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "7" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]>, <&[lindex $dmas 6]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } "8" { set refs [lindex $dmas 0] append refs ">, <&[lindex $dmas 1]>, <&[lindex $dmas 2]>, <&[lindex $dmas 3]>, <&[lindex $dmas 4]>, <&[lindex $dmas 5]>, <&[lindex $dmas 6]>, <&[lindex $dmas 7]" hsi::utils::add_new_dts_param "$vcap_scd" "dmas" $refs reference } } } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"]} { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle: peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: scugic/data/scugic.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver scugic OPTION supported_peripherals = (ps7_scugic psu_acpu_gic psv_acpu_gic psx_acpu_gic); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = scugic; DTGPARAM name = num_cpus, type = int, default = 2; DTGPARAM name = num_interrupts, type = int, default = 96; END driver ================================================ FILE: scugic/data/scugic.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set default_dts [set_drv_def_dts $drv_handle] set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set cpm_ip [get_cells -hier -filter IP_NAME==psv_cpm] if {[string match -nocase $proctype "psv_cortexa72"] && \ [string match -nocase [get_property CONFIG.APU_GIC_ITS_CTL [get_cells -hier $drv_handle]] "0xF9020000"] && \ [llength $cpm_ip]} { set gic_node [add_or_get_dt_node -n "&gic_its" -d $default_dts] hsi::utils::add_new_dts_param "${gic_node}" "status" "okay" string } } ================================================ FILE: scutimer/data/scutimer.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver scutimer OPTION supported_peripherals = (ps7_scutimer); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = scutimer; END driver ================================================ FILE: scutimer/data/scutimer.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: scuwdt/data/scuwdt.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver scuwdt OPTION supported_peripherals = (ps7_scuwdt psu_wdt psv_wdt); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = scuwdt; END driver ================================================ FILE: scuwdt/data/scuwdt.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: sdfec/data/sdfec.mdd ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sdfec OPTION supported_peripherals = (sd_fec); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sdfec; PARAMETER name = dev_type, default = "sd-fec", type = string; DTGPARAM name = compatible, type = stringlist, default = "xlnx,fec-engine"; END driver ================================================ FILE: sdfec/data/sdfec.tcl ================================================ # # (C) Copyright 2017-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set_drv_prop $drv_handle compatible "$compatible" stringlist set ldpc_decode [get_property CONFIG.LDPC_Decode [get_cells -hier $drv_handle]] set ldpc_encode [get_property CONFIG.LDPC_Encode [get_cells -hier $drv_handle]] set turbo_decode [get_property CONFIG.Turbo_Decode [get_cells -hier $drv_handle]] if {[string match -nocase $turbo_decode "true"]} { set sdfec_code "turbo" } else { set sdfec_code "ldpc" } set_drv_property $drv_handle xlnx,sdfec-code $sdfec_code string set sdfec_dout_words [get_property CONFIG.C_S_DOUT_WORDS_MODE [get_cells -hier $drv_handle]] set sdfec_dout_width [get_property CONFIG.DOUT_Lanes [get_cells -hier $drv_handle]] set sdfec_din_words [get_property CONFIG.C_S_DIN_WORDS_MODE [get_cells -hier $drv_handle]] set sdfec_din_width [get_property CONFIG.DIN_Lanes [get_cells -hier $drv_handle]] set_drv_property $drv_handle xlnx,sdfec-dout-words $sdfec_dout_words int set_drv_property $drv_handle xlnx,sdfec-dout-width $sdfec_dout_width int set_drv_property $drv_handle xlnx,sdfec-din-words $sdfec_din_words int set_drv_property $drv_handle xlnx,sdfec-din-width $sdfec_din_width int } ================================================ FILE: sdi_rx/data/sdi_rx.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sdi_rx OPTION supported_peripherals = (v_smpte_uhdsdi_rx_ss); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sdi_rx; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: sdi_rx/data/sdi_rx.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-smpte-uhdsdi-rx-ss"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ports_node [add_or_get_dt_node -n "ports" -l sdirx_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port_node [add_or_get_dt_node -n "port" -l sdirx_port$drv_handle -u 0 -p $ports_node] hsi::utils::add_new_dts_param "${port_node}" "/* Fill the fields xlnx,video-format and xlnx,video-width based on user requirement */" "" comment hsi::utils::add_new_dts_param "$port_node" "xlnx,video-format" 0 int hsi::utils::add_new_dts_param "$port_node" "xlnx,video-width" 10 int hsi::utils::add_new_dts_param "$port_node" "reg" 0 int set sdirxip [get_connected_stream_ip [get_cells -hier $drv_handle] "VIDEO_OUT"] foreach ip $sdirxip { if {[llength $ip]} { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set intfpins [::hsi::get_intf_pins -of_objects [get_cells -hier $ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set sdi_rx_node [add_or_get_dt_node -n "endpoint" -l sdirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "sdirx_out$drv_handle" hsi::utils::add_new_dts_param "$sdi_rx_node" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle $ip$drv_handle if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $ip $drv_handle } } else { set connectip [get_connect_ip $ip $intfpins] if {[llength $connectip]} { set sdi_rx_node [add_or_get_dt_node -n "endpoint" -l sdirx_out$drv_handle -p $port_node] gen_endpoint $drv_handle "sdirx_out$drv_handle" hsi::utils::add_new_dts_param "$sdi_rx_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle $connectip$drv_handle if {[string match -nocase [get_property IP_NAME $connectip] "axi_vdma"] || [string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"]} { gen_frmbuf_wr_node $connectip $drv_handle } } } } } } proc gen_frmbuf_wr_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_sdirx$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" sdirx_out$drv_handle reference } ================================================ FILE: sdi_tx/data/sdi_tx.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sdi_tx OPTION supported_peripherals = (v_smpte_uhdsdi_tx_ss); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sdi_tx; DTGPARAM name = dtg.ip_params, type = boolean; END driver ================================================ FILE: sdi_tx/data/sdi_tx.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,sdi-tx"] set_drv_prop $drv_handle compatible "$compatible" stringlist set exdes_board [get_property CONFIG.C_EXDES_BOARD [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,exdes-board" $exdes_board string set exdes_config [get_property CONFIG.C_EXDES_CONFIG [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,exdes-config" $exdes_config string set adv_features [get_property CONFIG.C_INCLUDE_ADV_FEATURES [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,include-adv-features" $adv_features string set axilite [get_property CONFIG.C_INCLUDE_AXILITE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,include-axilite" $axilite string set edh [get_property CONFIG.C_INCLUDE_EDH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,include-edh" $edh string set linerate [get_property CONFIG.C_LINE_RATE [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,line-rate" $linerate string set pixelclock [get_property CONFIG.C_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,pixels-per-clock" $pixelclock string set video_intf [get_property CONFIG.C_VIDEO_INTF [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "$node" "xlnx,video-intf" $video_intf string set ports_node [add_or_get_dt_node -n "ports" -l sditx_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set audio_connected_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "SDI_TX_ANC_DS_OUT"] if {[llength $audio_connected_ip] != 0} { set audio_connected_ip_type [get_property IP_NAME $audio_connected_ip] if {[string match -nocase $audio_connected_ip_type "v_uhdsdi_audio"]} { set sdi_audio_port [add_or_get_dt_node -n "port" -l sdi_audio_port -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$sdi_audio_port" "reg" 1 int set sdi_audio_node [add_or_get_dt_node -n "endpoint" -l sdi_audio_sink_port -p $sdi_audio_port] hsi::utils::add_new_dts_param "$sdi_audio_node" "remote-endpoint" sditx_audio_embed_src reference } } else { dtg_warning "$drv_handle:connected ip for audio port pin SDI_TX_ANC_DS_OUT is NULL" } } ================================================ FILE: sdps/data/sdps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sdps OPTION supported_peripherals = (ps7_sdioi psu_sd psv_pmc_sd psx_pmc_sd); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sdps; DTGPARAM name = clock-frequency , type = int ; END driver ================================================ FILE: sdps/data/sdps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ip [get_cells -hier $drv_handle] set clk_freq [hsi::utils::get_ip_param_value $ip C_SDIO_CLK_FREQ_HZ] set_property CONFIG.clock-frequency "$clk_freq" $drv_handle set_drv_conf_prop $drv_handle C_MIO_BANK xlnx,mio-bank hexint } ================================================ FILE: slcrps/data/slcrps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver slcrps OPTION supported_peripherals = (ps7_slcr); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = slcrps; END driver ================================================ FILE: slcrps/data/slcrps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] gen_clocks_node $node } proc gen_clocks_node {parent_node} { set clocks_child_name "clkc" set dts_file [get_property CONFIG.pcw_dts [get_os]] set clkc_node [add_or_get_dt_node -l $clocks_child_name -n $clocks_child_name -u 100 -d $dts_file -p $parent_node] if {[catch {set ps_clk_freq [get_property CONFIG.C_INPUT_CRYSTAL_FREQ_HZ [get_cells -hier ps7_clockc_0]]} msg]} { set ps_clk_freq "" } if {[string_is_empty ${ps_clk_freq}]} { puts "WARNING: DTG failed to detect the ps-clk-frequency, Using default value - 33333333" set ps_clk_freq 33333333 } hsi::utils::add_new_dts_param "${clkc_node}" "ps-clk-frequency" ${ps_clk_freq} int set fclk_val "0" set clk_pin_list [get_pins [get_cells -hier ps7_clockc_0] -regexp FCLK_CLK[0-3]] foreach clk_pin ${clk_pin_list} { dtg_debug "clk_pin: $clk_pin" set clk_net [get_nets -of_objects $clk_pin] set connected_pin_names [get_pins -of_objects $clk_net] foreach target_pin ${connected_pin_names} { dtg_debug " target_pin: $target_pin" set connected_ip [get_cells -of_objects $target_pin] if {[is_pl_ip $connected_ip]} { regsub -all {FCLK_CLK} $clk_pin {} fclk_pin set fclk_val [expr [expr 1 << $fclk_pin] | $fclk_val] dtg_debug " PL IP: $connected_ip, CLK_PIN: $clk_pin, FCLK_PIN: $fclk_pin, FCLK_VAL: [format %x $fclk_val]" # Here could be break } elseif {![string match "ps7_clockc_0" $connected_ip]} { dtg_debug " PS IP: $connected_ip" } } } hsi::utils::add_new_dts_param "${clkc_node}" "fclk-enable" "0x[format %x $fclk_val]" int return $clkc_node } ================================================ FILE: smccps/data/smccps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver smccps OPTION supported_peripherals = (ps7_smcc); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = smccps; END driver ================================================ FILE: smccps/data/smccps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: spips/data/spips.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver spips OPTION supported_peripherals = (ps7_spi psu_spi psv_spi psx_spi); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = spips; DTGPARAM name = num-cs , type = int, default = 1; DTGPARAM name = is-decoded-cs , type = int, default = 0; DTGPARAM name = dtg.alias , default = spi; END driver ================================================ FILE: spips/data/spips.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { set ip [get_cells -hier $drv_handle] set cs-num 0 # SPI PS only have chip select range 0 - 2 foreach n {0 1 2} { set cs_en [get_property CONFIG.C_HAS_SS${n} $ip] if {[string equal "1" $cs_en]} { inc cs-num } } if {${cs-num} != 0} { set_property CONFIG.num-cs ${cs-num} $drv_handle } # the is-decoded-cs property is hard coded as we do not know if the # board has external decoder connected or not # Once we had the board level information, is-decoded-cs need to be # generated based on it. } ================================================ FILE: sync_ip/data/sync_ip.mdd ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sync_ip OPTION supported_peripherals = (sync_ip); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sync_ip; END driver ================================================ FILE: sync_ip/data/sync_ip.tcl ================================================ # # (C) Copyright 2019-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set enable_enc_dec [get_property CONFIG.ENABLE_ENC_DEC [get_cells -hier $drv_handle]] if {$enable_enc_dec == 0} { #encode case hsi::utils::add_new_dts_param "${node}" "xlnx,encode" "" boolean set no_of_enc_chan [get_property CONFIG.NO_OF_ENC_CHAN [get_cells -hier $drv_handle]] set no_of_enc_chan [expr $no_of_enc_chan + 1] hsi::utils::add_new_dts_param "${node}" "xlnx,num-chan" $no_of_enc_chan int } else { #decode case set no_of_dec_chan [get_property CONFIG.NO_OF_DEC_CHAN [get_cells -hier $drv_handle]] set no_of_dec_chan [expr $no_of_dec_chan + 1] hsi::utils::add_new_dts_param "${node}" "xlnx,num-chan" $no_of_dec_chan int } } ================================================ FILE: sysmonpsv/data/sysmonpsv.mdd ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver sysmon OPTION supported_peripherals = (psv_pmc_sysmon slv1_psv_pmc_sysmon slv2_psv_pmc_sysmon slv3_psv_pmc_sysmon); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = sysmonpsv; END driver ================================================ FILE: sysmonpsv/data/sysmonpsv.tcl ================================================ # # (C) Copyright 2020-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set num_supply_channels 0 set periph_list [get_cells -hier] set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } hsi::utils::add_new_dts_param $node "#address-cells" 2 int hsi::utils::add_new_dts_param $node "#size-cells" 2 int set ssitvalue [get_property IS_SSIT [get_current_part $drv_handle]] if {[llength $ssitvalue]} { hsi::utils::add_new_dts_param "$node" "xlnx,ssit-device" "$ssitvalue" bool } set slrsvalue [get_property NUM_OF_SLRS [get_current_part $drv_handle]] if {[llength $slrsvalue] && $slrsvalue != "-1"} { hsi::utils::add_new_dts_param "$node" "xlnx,num-of-slr" "$slrsvalue" int } for {set supply_num 0} {$supply_num < 160} {incr supply_num} { set meas "C_MEAS_${supply_num}" set id "${meas}_ROOT_ID" set value [get_property CONFIG.$meas [get_cells -hier $drv_handle]] if {[llength $value] != 0} { set local_value [string tolower [get_property CONFIG.$meas [get_cells -hier $drv_handle]]] set id_value [get_property CONFIG.$id [get_cells -hier $drv_handle]] set default_dts [get_property CONFIG.pcw_dts [get_os]] set supply_node [add_or_get_dt_node -n "supply@$id_value" -p $node -d ${default_dts}] hsi::utils::add_new_dts_param "$supply_node" "reg" "$id_value" int hsi::utils::add_new_dts_param "$supply_node" "xlnx,name" "$local_value" string incr num_supply_channels } } append numsupplies "/bits/8 <$num_supply_channels>" hsi::utils::add_new_dts_param $node "xlnx,numchannels" $numsupplies noformating } ================================================ FILE: tmrctr/data/tmrctr.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver tmrctr OPTION supported_peripherals = (axi_timer); OPTION driver_state = ACTIVE; OPTION NAME = tmrctr; OPTION supported_os_types = (DTS); DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = dev_type, default = timer , type = string; DTGPARAM name = clock-frequency, type = int, default = 100000000; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-timer-1.00.a" END driver ================================================ FILE: tmrctr/data/tmrctr.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-timer-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist #adding clock frequency set ip [get_cells -hier $drv_handle] set clk [get_pins -of_objects $ip "S_AXI_ACLK"] if {[llength $clk] } { set freq [get_property CLK_FREQ $clk] set_property clock-frequency "$freq" $drv_handle } set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_aclk" } } } ================================================ FILE: tpg/data/tpg.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver tpg OPTION supported_peripherals = (v_tpg); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = tpg; END driver ================================================ FILE: tpg/data/tpg.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set tpg_count [hsi::utils::get_os_parameter_value "tpg_count"] if { [llength $tpg_count] == 0 } { set tpg_count 0 } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-tpg-8.0"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set s_axi_ctrl_addr_width [get_property CONFIG.C_S_AXI_CTRL_ADDR_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-addr-width" $s_axi_ctrl_addr_width int set s_axi_ctrl_data_width [get_property CONFIG.C_S_AXI_CTRL_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,s-axi-ctrl-data-width" $s_axi_ctrl_data_width int set max_data_width [get_property CONFIG.MAX_DATA_WIDTH [get_cells -hier $drv_handle]] set pixels_per_clock [get_property CONFIG.SAMPLES_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,ppc" $pixels_per_clock int set max_cols [get_property CONFIG.MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-width" $max_cols int set max_rows [get_property CONFIG.MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-height" $max_rows int set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] if {[string match -nocase $proctype "ps7_cortexa9"]} { # Workaround for issue (TBF) return } set ports_node [add_or_get_dt_node -n "ports" -l tpg_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l tpg_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int hsi::utils::add_new_dts_param "${port1_node}" "/* Fill the field xlnx,video-format based on user requirement */" "" comment hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-format" 2 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-width" $max_data_width int set connect_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_VIDEO"] if {![llength $connect_ip]} { dtg_warning "$drv_handle pin S_AXIS_VIDEO is not connected..check your design" } foreach connected_ip $connect_ip { if {[llength $connected_ip] != 0} { set connected_ip_type [get_property IP_NAME $connected_ip] set ports_node "" set sink_periph "" if {[llength $connected_ip_type] != 0} { if {[string match -nocase $connected_ip_type "system_ila"]} { continue } if {[string match -nocase $connected_ip_type "v_vid_in_axi4s"]} { set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $connected_ip "vid_active_video"]]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "v_tc"]} { hsi::utils::add_new_dts_param "$node" "xlnx,vtc" "$sink_periph" reference } } } } } } set connect_out_ip [get_connected_stream_ip [get_cells -hier $drv_handle] "M_AXIS_VIDEO"] if {![llength $connect_out_ip]} { dtg_warning "$drv_handle pin M_AXIS_VIDEO is not connected ...check your design" } foreach out_ip $connect_out_ip { if {[llength $out_ip] != 0} { set connected_out_ip_type [get_property IP_NAME $out_ip] if {[llength $connected_out_ip_type] != 0} { if {[string match -nocase $connected_out_ip_type "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $out_ip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $out_ip] if {[string match -nocase [get_property IP_NAME $out_ip] "axis_switch"]} { if {[llength $ip_mem_handles]} { set tpg_node [add_or_get_dt_node -n "endpoint" -l tpg_out$drv_handle -p $port1_node] gen_axis_switch_in_endpoint $drv_handle "tpg_out$drv_handle" hsi::utils::add_new_dts_param "$tpg_node" "remote-endpoint" $out_ip$drv_handle reference gen_axis_switch_in_remo_endpoint $drv_handle "$out_ip$drv_handle" } } if {[llength $ip_mem_handles]} { set tpg_node [add_or_get_dt_node -n "endpoint" -l tpg_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "tpg_out$drv_handle" hsi::utils::add_new_dts_param "$tpg_node" "remote-endpoint" $out_ip$drv_handle reference gen_remoteendpoint $drv_handle "$out_ip$drv_handle" if {[string match -nocase [get_property IP_NAME $out_ip] "v_frmbuf_wr"] || [string match -nocase [get_property IP_NAME $out_ip] "axi_vdma"]} { gen_frmbuf_node $out_ip $drv_handle } } else { set connectip [get_connect_ip $out_ip $master_intf] if {[llength $connectip]} { set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip] if {[llength $ip_mem_handles]} { set tpg_node [add_or_get_dt_node -n "endpoint" -l tpg_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "tpg_out$drv_handle" hsi::utils::add_new_dts_param "$tpg_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"] || [string match -nocase [get_property IP_NAME $connectip] "axi_vdma"]} { gen_frmbuf_node $connectip $drv_handle } } } } } } else { dtg_warning "$drv_handle pin M_AXIS_VIDEO is not connected ...check your design" } } gen_gpio_reset $drv_handle $node } proc gen_frmbuf_node {ip drv_handle} { set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$ip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int if {[string match -nocase $proctype "ps7_cortexa9"]} { #Workaround for issue (TBF) set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -p $vcap_ports_node] } else { set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] } hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $ip$drv_handle -p $vcap_port_node] hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" tpg_out$drv_handle reference } proc gen_gpio_reset {drv_handle node} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "ap_rst_n"]] foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] set proc_type [get_sw_proc_prop IP_NAME] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: tsn/data/tsn.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver tsn OPTION supported_peripherals = (tsn_endpoint_ethernet_mac); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = tsn; END driver ================================================ FILE: tsn/data/tsn.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set proc_type [get_sw_proc_prop IP_NAME] set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set eth_ip [get_cells -hier $drv_handle] set ip_name [get_property IP_NAME $eth_ip] global tsn_ep_node global tsn_emac0_node global tsn_emac1_node global tsn_ex_ep_node set tsn_ep_node "tsn_ep" set tsn_emac0_node "tsn_emac_0" set tsn_emac1_node "tsn_emac_1" set tsn_ex_ep_node "tsn_ex_ep" set end_point_ip "" set end1 "" set connectrx_ip "" set connecttx_ip "" set connected_ip [hsi::utils::get_connected_stream_ip $eth_ip "tx_axis_be"] if {[llength $connected_ip] != 0} { set end1_ip [hsi::utils::get_connected_stream_ip $connected_ip "S00_AXIS"] if {[llength $end1_ip] != 0} { set end1 [lappend end1 $end1_ip] } else { set connecttx_ip [lappend connecttx_ip $connected_ip] } } set connect_ip [hsi::utils::get_connected_stream_ip $eth_ip "rx_axis_be"] if {[llength $connect_ip] != 0} { set end_ip [hsi::utils::get_connected_stream_ip $connect_ip "M00_AXIS"] if {[llength $end_ip]!= 0} { set end_point_ip [lappend end_point_ip $end_ip] } else { set connectrx_ip [lappend connectrx_ip $connect_ip] } } foreach ip [get_drivers] { if {[string compare -nocase $ip $end_ip] == 0} { set target_handle $ip } } set connectedrx_ipname [get_property IP_NAME $end_ip] set id 1 set queue "" if {$connectedrx_ipname == "axi_mcdma"} { set num_queues [get_property CONFIG.c_num_s2mm_channels $end_ip] set rx_queues [get_property CONFIG.c_num_mm2s_channels $end_ip] if {$num_queues > $rx_queues} { set queue $num_queues } else { set queue $rx_queues } for {set i 2} {$i <= $num_queues} {incr i} { set i [format "%x" $i] append id "\"" append id ",\"" $i set i [expr 0x$i] } set int1 [get_property CONFIG.interrupts $target_handle] set int2 [get_property CONFIG.interrupt-parent $target_handle] set int3 [get_property CONFIG.interrupt-names $target_handle] } set inhex [format %x $queue] append queues "/bits/ 16 <0x$inhex>" set connected_ip [hsi::utils::get_connected_stream_ip $eth_ip "tx_axis_res"] if {[llength $connected_ip] != 0} { set end1_ip [hsi::utils::get_connected_stream_ip $connected_ip "S00_AXIS"] if {[llength $end1_ip] != 0} { set end1 [lappend end1 $end1_ip] } else { set connecttx_ip [lappend connecttx_ip $connected_ip] } } set connect_ip [hsi::utils::get_connected_stream_ip $eth_ip "rx_axis_res"] if {[llength $connect_ip] != 0} { set end_ip [hsi::utils::get_connected_stream_ip $connect_ip "M00_AXIS"] if {[llength $end_ip] != 0} { set end_point_ip [lappend end_point_ip $end_ip] } else { set connectrx_ip [lappend connectrx_ip $connect_ip] } } set connected_ip [hsi::utils::get_connected_stream_ip $eth_ip "tx_axis_st"] if {[llength $connected_ip] != 0} { set end1_ip [hsi::utils::get_connected_stream_ip $connected_ip "S00_AXIS"] if {[llength $end1_ip] != 0} { set end1 [lappend end1 $end1_ip] } else { set connecttx_ip [lappend connecttx_ip $connected_ip] } } set connect_ip [hsi::utils::get_connected_stream_ip $eth_ip "rx_axis_st"] if {[llength $connect_ip] != 0} { set end_ip [hsi::utils::get_connected_stream_ip $connect_ip "M00_AXIS"] if {[llength $end_ip] != 0} { set end_point_ip [lappend end_point_ip $end_ip] } else { set connectrx_ip [lappend connectrx_ip $connect_ip] } } set baseaddr [get_baseaddr $eth_ip no_prefix] set num_queues [get_property CONFIG.NUM_PRIORITIES $eth_ip] if {[string match -nocase $proc_type "psu_cortexa53"]} { hsi::utils::add_new_dts_param $node "#address-cells" 2 int hsi::utils::add_new_dts_param $node "#size-cells" 2 int hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean } elseif {[string match -nocase $proc_type "ps7_cortexa9"]} { hsi::utils::add_new_dts_param $node "#address-cells" 1 int hsi::utils::add_new_dts_param $node "#size-cells" 1 int hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean } set freq "" set clk [get_pins -of_objects $eth_ip "S_AXI_ACLK"] if {[llength $clk] } { set freq [get_property CLK_FREQ $clk] } set inhex [format %x $num_queues] append numqueues "/bits/ 16 <0x$inhex>" set intr_val [get_property CONFIG.interrupts $drv_handle] set intr_parent [get_property CONFIG.interrupt-parent $drv_handle] set intr_names [get_property CONFIG.interrupt-names $drv_handle] set mac0intr "" set mac1intr "" set ep_sched_irq "" foreach intr1 $intr_names { set num [regexp -all -inline -- {[0-9]+} $intr1] if {$num == 1} { lappend mac0intr $intr1 } if {$num == 2} { lappend mac1intr $intr1 } if {[string match -nocase $intr1 "interrupt_ptp_timer"]} { lappend mac0intr $intr1 } if {[string match -nocase $intr1 "tsn_ep_scheduler_irq"]} { lappend ep_sched_irq $intr1 } } set switch_present "" set periph_list [get_cells -hier] set tsn_inst_name [get_cells -filter {IP_NAME =~ "*tsn*"}] foreach periph $periph_list { if {[string match -nocase "${tsn_inst_name}_switch_core_top_0" $periph] } { set switch_offset [get_property CONFIG.SWITCH_OFFSET $eth_ip] set high_addr [get_property CONFIG.C_HIGHADDR $eth_ip] set one 0x1 set switch_present 0x1 set switch_addr [format %08x [expr 0x$baseaddr + $switch_offset]] set switch_size [format %08x [expr $high_addr - 0x$switch_addr]] set switch_size [format %08x [expr 0x${switch_size} + 1]] gen_switch_node $periph $switch_addr $switch_size $numqueues $node $drv_handle $proc_type $eth_ip } if {[string match -nocase "${tsn_inst_name}" $periph] } { set baseaddr [get_baseaddr $eth_ip no_prefix] set tmac0_size [get_property CONFIG.TEMAC_1_SIZE $eth_ip] if { $switch_present != 1 } { gen_mac0_node $periph $baseaddr $tmac0_size $node $proc_type $drv_handle $numqueues $freq $intr_parent $mac0intr $eth_ip $queues $id $end1 $end_point_ip $connectrx_ip $connecttx_ip $tsn_inst_name } else { set end_point_ip "" set connectrx_ip "" set connecttx_ip "" gen_mac0_node $periph $baseaddr $tmac0_size $node $proc_type $drv_handle $numqueues $freq $intr_parent $mac0intr $eth_ip $queues $id $end1 $end_point_ip $connectrx_ip $connecttx_ip $tsn_inst_name } } if {[string match -nocase "${tsn_inst_name}_tsn_temac_2" $periph] } { set baseaddr [get_baseaddr $eth_ip no_prefix] set tmac1_offset [get_property CONFIG.TEMAC_2_OFFSET $eth_ip] set tmac1_size [get_property CONFIG.TEMAC_2_SIZE $eth_ip] set addr_off [format %08x [expr 0x$baseaddr + $tmac1_offset]] gen_mac1_node $periph $addr_off $tmac1_size $numqueues $intr_parent $node $drv_handle $proc_type $freq $eth_ip $mac1intr $baseaddr $queues $tsn_inst_name } if {[string match -nocase "${tsn_inst_name}_tsn_endpoint_block_0" $periph]} { set ep_offset [get_property CONFIG.EP_SCHEDULER_OFFSET $eth_ip] if {[llength $ep_offset] != 0} { set ep_addr [format %08x [expr 0x$baseaddr + $ep_offset]] set ep_size [get_property CONFIG.EP_SCHEDULER_SIZE $eth_ip] if { $switch_present == 1 } { gen_ep_node $periph $ep_addr $ep_size $numqueues $node $drv_handle $proc_type $ep_sched_irq $eth_ip $intr_parent $int3 $int1 $id $end1 $end_point_ip $connectrx_ip $connecttx_ip } else { set end_point_ip "" set connectrx_ip "" set connecttx_ip "" gen_ep_node $periph $ep_addr $ep_size $numqueues $node $drv_handle $proc_type $ep_sched_irq $eth_ip $intr_parent $int3 $int1 $id $end1 $end_point_ip $connectrx_ip $connecttx_ip } } } } } proc get_checksum {value} { if {[string compare -nocase $value "None"] == 0} { set value 0 } elseif {[string compare -nocase $value "Partial"] == 0} { set value 1 } else { set value 2 } return $value } proc get_phytype {value} { if {[string compare -nocase $value "MII"] == 0} { set value 0 } elseif {[string compare -nocase $value "GMII"] == 0} { set value 1 } elseif {[string compare -nocase $value "RGMII"] == 0} { set value 3 } elseif {[string compare -nocase $value "SGMII"] == 0} { set value 4 } else { set value 5 } return $value } proc pcspma_phy_node {slave tsn_inst_name} { set phyaddr [get_property CONFIG.PHYADDR $slave] set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr] if {[string match -nocase $slave "${tsn_inst_name}_tsn_temac_2"]} { set phyaddr "2" } else { set phyaddr "1" } set phymode "phy$phyaddr" return "$phyaddr $phymode" } proc gen_phy_node args { set mdio_node [lindex $args 0] set phy_name [lindex $args 1] set phya [lindex $args 2] set phy_node [add_or_get_dt_node -l ${phy_name} -n phy -u $phya -p $mdio_node] hsi::utils::add_new_dts_param "${phy_node}" "reg" 0 int hsi::utils::add_new_dts_param "${phy_node}" "device_type" "ethernet-phy" string hsi::utils::add_new_dts_param "${phy_node}" "compatible" "marvell,88e1111" string return $phy_node } proc gen_ep_node {periph ep_addr ep_size numqueues parent_node drv_handle proc_type ep_sched_irq eth_ip intr_parent int3 int1 id end1 end_point_ip connectrx_ip connecttx_ip} { global tsn_ep_node set ep_node [add_or_get_dt_node -n "tsn_ep" -l $tsn_ep_node -u $ep_addr -p $parent_node] if {[string match -nocase $proc_type "ps7_cortexa9"]} { set ep_reg "0x$ep_addr $ep_size" } else { set ep_reg "0x0 0x$ep_addr 0x0 $ep_size" } foreach intr $int3 { lappend ep_sched_irq $intr } if {[llength $ep_sched_irq] != 0} { set intr_num [get_intr_id $eth_ip [lindex $ep_sched_irq 0]] } foreach int $int1 { lappend intr_num $int } hsi::utils::add_new_dts_param "${ep_node}" "interrupt-names" $ep_sched_irq stringlist hsi::utils::add_new_dts_param ${ep_node} "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${ep_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${ep_node}" "reg" $ep_reg int hsi::utils::add_new_dts_param "${ep_node}" "compatible" "xlnx,tsn-ep" string hsi::utils::add_new_dts_param "${ep_node}" "xlnx,num-tc" $numqueues noformating hsi::utils::add_new_dts_param "${ep_node}" "xlnx,channel-ids" $id string set mac_addr "00 0A 35 00 01 05" hsi::utils::add_new_dts_param $ep_node "local-mac-address" ${mac_addr} bytelist hsi::utils::add_new_dts_param "$ep_node" "xlnx,eth-hasnobuf" "" boolean global tsn_ex_ep_node set tsn_ex_ep [get_property CONFIG.EN_EP_PORT_EXTN $eth_ip] if {[string match -nocase $tsn_ex_ep "true"]} { set tsn_ex_ep_node [add_or_get_dt_node -n "tsn_ex_ep" -l $tsn_ex_ep_node -p $parent_node] hsi::utils::add_new_dts_param "${tsn_ex_ep_node}" "compatible" "xlnx,tsn-ex-ep" string set mac_addr "00 0A 35 00 01 06" set en_pkt_switch [get_property CONFIG.EN_EP_PKT_SWITCH $eth_ip] if {[string match -nocase $en_pkt_switch "true"]} { hsi::utils::add_new_dts_param "$tsn_ex_ep_node" "packet-switch" 1 int } hsi::utils::add_new_dts_param $tsn_ex_ep_node "local-mac-address" ${mac_addr} bytelist hsi::utils::add_new_dts_param "$tsn_ex_ep_node" "tsn,endpoint" $tsn_ep_node reference } set len [llength $end1] switch $len { "1" { set ref_id [lindex $end1 0] hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } "2" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } "3" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]>, <&[lindex $end1 2]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } } set len3 [llength $connecttx_ip] switch $len3 { "1" { set ref_id [lindex $connecttx_ip 0] hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } "2" { set ref_id [lindex $connecttx_ip 0] append ref_id ">, <&[lindex $connecttx_ip 1]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } "3" { set ref_id [lindex $connecttx_ip 0] append ref_id ">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } } if {$len && $len3} { if {$len == 1} { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } if {$len == 2} { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]>, <&[lindex $connecttx_ip 0]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-tx" "$ref_id" reference } } set len1 [llength $end_point_ip] switch $len1 { "1" { set ref_id [lindex $end_point_ip 0] hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } "2" { set ref_id [lindex $end_point_ip 0] append ref_id ">, <&[lindex $end_point_ip 1]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } "3" { set ref_id [lindex $end_point_ip 0] append ref_id ">, <&[lindex $end_point_ip 1]>, <&[lindex $end_point_ip 2]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } } set len2 [llength $connectrx_ip] switch $len2 { "1" { set ref_id [lindex $connectrx_ip 0] hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } "2" { set ref_id [lindex $connectrx_ip 0] append ref_id ">, <&[lindex $connectrx_ip 1]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } "3" { set ref_id [lindex $connectrx_ip 0] append ref_id ">, <&[lindex $connectrx_ip 1]>, <&[lindex $connectrx_ip 2]" hsi::utils::add_new_dts_param "${ep_node}" "axistream-connected-rx" "$ref_id" reference } } } proc gen_switch_node {periph addr size numqueues parent_node drv_handle proc_type eth_ip} { set switch_node [add_or_get_dt_node -n "tsn_switch" -l epswitch -u $addr -p $parent_node] set hwaddr_learn [get_property CONFIG.EN_HW_ADDR_LEARNING $eth_ip] set mgmt_tag [get_property CONFIG.EN_INBAND_MGMT_TAG $eth_ip] if {[string match -nocase $proc_type "ps7_cortexa9"]} { set switch_reg "0x$addr 0x$size" } else { set switch_reg "0x0 0x$addr 0x0 0x$size" } hsi::utils::add_new_dts_param "${switch_node}" "reg" $switch_reg int hsi::utils::add_new_dts_param "${switch_node}" "compatible" "xlnx,tsn-switch" string hsi::utils::add_new_dts_param "${switch_node}" "xlnx,num-tc" $numqueues noformating if {[string match -nocase $hwaddr_learn "true"]} { hsi::utils::add_new_dts_param "${switch_node}" "xlnx,has-hwaddr-learning" "" boolean } if {[string match -nocase $mgmt_tag "true"]} { hsi::utils::add_new_dts_param "${switch_node}" "xlnx,has-inband-mgmt-tag" "" boolean } set inhex [format %x 3] append numports "/bits/ 16 <0x$inhex>" hsi::utils::add_new_dts_param "${switch_node}" "xlnx,num-ports" $numports noformating global tsn_ep_node global tsn_emac0_node global tsn_emac1_node set end1 "" set end1 [lappend end1 $tsn_ep_node] set end1 [lappend end1 $tsn_emac0_node] set end1 [lappend end1 $tsn_emac1_node] set len [llength $end1] switch $len { "1" { set ref_id [lindex $end1 0] hsi::utils::add_new_dts_param "${switch_node}" "ports" "$ref_id" reference } "2" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]" hsi::utils::add_new_dts_param "${switch_node}" "ports" "$ref_id" reference } "3" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]>, <&[lindex $end1 2]" hsi::utils::add_new_dts_param "${switch_node}" "ports" "$ref_id" reference } } } proc gen_mac0_node {periph addr size parent_node proc_type drv_handle numqueues freq intr_parent mac0intr eth_ip queues id end1 end_point_ip connectrx_ip connecttx_ip tsn_inst_name} { global tsn_emac0_node set tsn_mac_node [add_or_get_dt_node -n "tsn_emac_0" -l $tsn_emac0_node -u $addr -p $parent_node] if {[string match -nocase $proc_type "ps7_cortexa9"]} { set tsnreg "0x$addr $size" } else { set tsnreg "0x0 0x$addr 0x0 $size" } hsi::utils::add_new_dts_param "${tsn_mac_node}" "reg" $tsnreg int set tsn_comp "xlnx,tsn-ethernet-1.00.a" hsi::utils::add_new_dts_param "${tsn_mac_node}" "compatible" $tsn_comp stringlist set mdionode [add_or_get_dt_node -l ${drv_handle}_mdio0 -n mdio -p $tsn_mac_node] hsi::utils::add_new_dts_param "${mdionode}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${mdionode}" "#size-cells" 0 int "" set phytype [string tolower [get_property CONFIG.PHYSICAL_INTERFACE $periph]] set txcsum "0" set rxcsum "0" set mac_addr "00 0A 35 00 01 0e" set phy_type [get_phytype $phytype] set qbv_offset [get_property CONFIG.TEMAC_1_SCHEDULER_OFFSET $periph] set qbv_size [get_property CONFIG.TEMAC_1_SCHEDULER_SIZE $periph] hsi::utils::add_new_dts_param $tsn_mac_node "local-mac-address" ${mac_addr} bytelist hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,txsum" $txcsum int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,rxsum" $rxcsum int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,tsn" "" boolean hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,eth-hasnobuf" "" boolean set phymode $phytype if {$phytype == "rgmii"} { set phymode "rgmii-id" } hsi::utils::add_new_dts_param "$tsn_mac_node" "phy-mode" $phymode string hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,num-tc" $numqueues noformating hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,channel-ids" $id string hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,num-queues" $queues noformating global tsn_ep_node hsi::utils::add_new_dts_param "$tsn_mac_node" "tsn,endpoint" $tsn_ep_node reference if {[llength $qbv_offset] != 0} { set qbv_addr 0x[format %08x [expr 0x$addr + $qbv_offset]] hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,qbv-addr" $qbv_addr int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,qbv-size" $qbv_size int } set intr_len [llength $mac0intr] for {set i 0} {$i < $intr_len} {incr i} { lappend intr [lindex $mac0intr $i] lappend intr_num [get_intr_id $eth_ip [lindex $mac0intr $i]] } regsub -all "\{||\t" $intr_num {} intr_num regsub -all "\}||\t" $intr_num {} intr_num hsi::utils::add_new_dts_param $tsn_mac_node "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${tsn_mac_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${tsn_mac_node}" "interrupt-names" $mac0intr stringlist hsi::utils::add_new_dts_param "${tsn_mac_node}" "clock-frequency" $freq int if {$phytype == "rgmii" || $phytype == "gmii"} { set phynode [pcspma_phy_node $periph $tsn_inst_name] set phya [lindex $phynode 0] if { $phya != "-1"} { set phy_name "[lindex $phynode 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "phy-handle" $phy_name reference gen_phy_node $mdionode $phy_name $phya } } set len [llength $end1] switch $len { "1" { set ref_id [lindex $end1 0] hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } "2" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } "3" { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]>, <&[lindex $end1 2]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } } set len3 [llength $connecttx_ip] switch $len3 { "1" { set ref_id [lindex $connecttx_ip 0] hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } "2" { set ref_id [lindex $connecttx_ip 0] append ref_id ">, <&[lindex $connecttx_ip 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } "3" { set ref_id [lindex $connecttx_ip 0] append ref_id ">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } } if {$len && $len3} { if {$len == 1} { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $connecttx_ip 1]>, <&[lindex $connecttx_ip 2]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } if {$len == 2} { set ref_id [lindex $end1 0] append ref_id ">, <&[lindex $end1 1]>, <&[lindex $connecttx_ip 0]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-tx" "$ref_id" reference } } set len1 [llength $end_point_ip] switch $len1 { "1" { set ref_id [lindex $end_point_ip 0] hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } "2" { set ref_id [lindex $end_point_ip 0] append ref_id ">, <&[lindex $end_point_ip 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } "3" { set ref_id [lindex $end_point_ip 0] append ref_id ">, <&[lindex $end_point_ip 1]>, <&[lindex $end_point_ip 2]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } } set len2 [llength $connectrx_ip] switch $len2 { "1" { set ref_id [lindex $connectrx_ip 0] hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } "2" { set ref_id [lindex $connectrx_ip 0] append ref_id ">, <&[lindex $connectrx_ip 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } "3" { set ref_id [lindex $connectrx_ip 0] append ref_id ">, <&[lindex $connectrx_ip 1]>, <&[lindex $connectrx_ip 2]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "axistream-connected-rx" "$ref_id" reference } } } proc gen_mac1_node {periph addr size numqueues intr_parent parent_node drv_handle proc_type freq eth_ip mac1intr baseaddr queues tsn_inst_name} { global tsn_emac1_node set tsn_mac_node [add_or_get_dt_node -n "tsn_emac_1" -l $tsn_emac1_node -u $addr -p $parent_node] if {[string match -nocase $proc_type "ps7_cortexa9"]} { set tsn_reg "0x$addr $size" } else { set tsn_reg "0x0 0x$addr 0x0 $size" } set tsn_comp "xlnx,tsn-ethernet-1.00.a" hsi::utils::add_new_dts_param "${tsn_mac_node}" "reg" $tsn_reg int hsi::utils::add_new_dts_param "${tsn_mac_node}" "compatible" $tsn_comp stringlist set mdionode [add_or_get_dt_node -l ${drv_handle}_mdio1 -n mdio -p $tsn_mac_node] hsi::utils::add_new_dts_param "${mdionode}" "#address-cells" 1 int "" hsi::utils::add_new_dts_param "${mdionode}" "#size-cells" 0 int "" set tsn_emac2_ip [get_property IP_NAME $periph] set tsn_ip [get_cells -hier -filter {IP_NAME == $tsn_emac2_ip}] set phytype [string tolower [get_property CONFIG.Physical_Interface $periph]] set txcsum "0" set rxcsum "0" set mac_addr "00 0A 35 00 01 0f" set phy_type [get_phytype $phytype] set qbv_offset [get_property CONFIG.TEMAC_2_SCHEDULER_OFFSET $eth_ip] set qbv_size [get_property CONFIG.TEMAC_2_SCHEDULER_SIZE $eth_ip] hsi::utils::add_new_dts_param $tsn_mac_node "local-mac-address" ${mac_addr} bytelist hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,txsum" $txcsum int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,rxsum" $rxcsum int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,tsn" "" boolean hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,tsn-slave" "" boolean hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,eth-hasnobuf" "" boolean set phymode $phytype if {$phytype == "rgmii"} { set phymode "rgmii-id" } hsi::utils::add_new_dts_param "$tsn_mac_node" "phy-mode" $phymode string hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,num-tc" $numqueues noformating hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,num-queues" $queues noformating global tsn_ep_node hsi::utils::add_new_dts_param "$tsn_mac_node" "tsn,endpoint" $tsn_ep_node reference if {[llength $qbv_offset] != 0} { set qbv_addr 0x[format %08x [expr 0x$baseaddr + $qbv_offset]] hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,qbv-addr" $qbv_addr int hsi::utils::add_new_dts_param "$tsn_mac_node" "xlnx,qbv-size" $qbv_size int } set intr_len [llength $mac1intr] for {set i 0} {$i < $intr_len} {incr i} { lappend intr [lindex $mac1intr $i] lappend intr_num [get_intr_id $eth_ip [lindex $mac1intr $i]] } regsub -all "\{||\t" $intr_num {} intr_num regsub -all "\}||\t" $intr_num {} intr_num hsi::utils::add_new_dts_param $tsn_mac_node "interrupts" $intr_num intlist hsi::utils::add_new_dts_param "${tsn_mac_node}" "interrupt-parent" $intr_parent reference hsi::utils::add_new_dts_param "${tsn_mac_node}" "interrupt-names" $mac1intr stringlist hsi::utils::add_new_dts_param "${tsn_mac_node}" "clock-frequency" $freq int if {$phytype == "rgmii" || $phytype == "gmii"} { set phynode [pcspma_phy_node $periph $tsn_inst_name] set phya [lindex $phynode 0] if { $phya != "-1"} { set phy_name "[lindex $phynode 1]" hsi::utils::add_new_dts_param "${tsn_mac_node}" "phy-handle" $phy_name reference gen_phy_node $mdionode $phy_name $phya } } } ================================================ FILE: ttcps/data/ttcps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver ttcps OPTION supported_peripherals = (ps7_ttc psu_ttc psv_ttc psx_ttc); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = ttcps; END driver ================================================ FILE: ttcps/data/ttcps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: uartlite/data/uartlite.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver uartlite OPTION supported_peripherals = (mdm axi_uartlite); OPTION driver_state = ACTIVE; OPTION supported_os_types = (DTS); OPTION NAME = uartlite; PARAMETER name = dev_type, default = "serial", type = string; DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = dtg.alias, type = string, default = serial; DTGPARAM name = port-number, type = int, default = 0; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-uartlite-1.00.a"; DTGPARAM name = device_type, type = string, default = serial; END driver ================================================ FILE: uartlite/data/uartlite.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,xps-uartlite-1.00.a"] set_drv_prop $drv_handle compatible "$compatible" stringlist set config_baud [get_property CONFIG.dt_setbaud [get_os]] set ip [get_cells -hier $drv_handle] set consoleip [get_property CONFIG.console_device [get_os]] if { [string match -nocase $consoleip $ip] } { set ip_type [get_property IP_NAME $ip] if {!$config_baud} { if { [string match -nocase $ip_type] } { hsi::utils::set_os_parameter_value "console" "ttyUL0,115200" } else { hsi::utils::set_os_parameter_value "console" "ttyUL0,[hsi::utils::get_ip_param_value $ip C_BAUDRATE]" } } else { hsi::utils::set_os_parameter_value "console" "ttyUL0,$config_baud" } } set_drv_conf_prop $drv_handle C_BAUDRATE current-speed int set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_aclk" } } } ================================================ FILE: uartns/data/uartns.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver uartns OPTION supported_peripherals = (axi_uart16550); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = uartns; PARAMETER name = dev_type, default = "serial", type = string; DTGPARAM name = dtg.ip_params, type = boolean; DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-uart16550-2.00.a ns16550a"; DTGPARAM name = current-speed, type = int, default = 115200; DTGPARAM name = device_type, type = string, default = serial; DTGPARAM name = dtg.alias, type = string, default = serial; DTGPARAM name = reg-offset, type = hexint, default = 0x1000; DTGPARAM name = reg-shift, type = int, default = 2; DTGPARAM name = clock-frequency, type = int, default = 100000000; DTGPARAM name = port-number, type = int, default = 0; END driver ================================================ FILE: uartns/data/uartns.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { # try to source the common tcl procs # assuming the order of return is based on repo priority foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set ip [get_cells -hier $drv_handle] set has_xin [hsi::utils::get_ip_param_value $ip C_HAS_EXTERNAL_XIN] set clock_port "S_AXI_ACLK" if { [string match -nocase "$has_xin" "1"] } { set_drv_conf_prop $drv_handle C_EXTERNAL_XIN_CLK_HZ clock-frequency # TODO: update the clock-names and clocks properties and create a # fixed clock node. Currently this is causing any issue as the # driver only uses clock-frequency property } else { set freq [hsi::utils::get_clk_pin_freq $ip "$clock_port"] set_property clock-frequency $freq $drv_handle } set consoleip [get_property CONFIG.console_device [get_os]] if { [string match -nocase $consoleip $ip] } { hsi::utils::set_os_parameter_value "console" "ttyS0,115200" } set proc_type [get_sw_proc_prop IP_NAME] switch $proc_type { "microblaze" { gen_dev_ccf_binding $drv_handle "s_axi_aclk" } } } ================================================ FILE: uartps/data/uartps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver uartps OPTION supported_peripherals = (ps7_uart psu_uart psu_sbsauart psv_uart psv_sbsauart psx_sbsauart); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = uartps; DTGPARAM name = device_type , type = string, default = serial; DTGPARAM name = dtg.alias, type = string, default = serial; DTGPARAM name = port-number, type = int, default = 0; END driver ================================================ FILE: uartps/data/uartps.tcl ================================================ # # (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd # Based on original code: # (C) Copyright 2007-2014 Michal Simek # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # Michal SIMEK # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set ip [get_cells -hier $drv_handle] set consoleip [get_property CONFIG.console_device [get_os]] set config_baud [get_property CONFIG.dt_setbaud [get_os]] set port_number 0 if {[string match -nocase "$ip" "$consoleip"] == 0} { set serial_count [hsi::utils::get_os_parameter_value "serial_count"] if { [llength $serial_count] == 0 } { set serial_count 0 } incr serial_count hsi::utils::set_os_parameter_value "serial_count" $serial_count set port_number $serial_count } else { #adding os console property if this is console ip set avail_param [list_property [get_cells -hier $drv_handle]] # This check is needed because BAUDRATE parameter for psuart is available from # 2017.1 onwards if {[lsearch -nocase $avail_param "CONFIG.C_BAUDRATE"] >= 0} { set baud [get_property CONFIG.C_BAUDRATE [get_cells -hier $drv_handle]] } else { set baud "115200" } if {$config_baud} { hsi::utils::set_os_parameter_value "console" "ttyPS0,$config_baud" if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set_drv_prop $drv_handle "current-speed" $config_baud int } } else { hsi::utils::set_os_parameter_value "console" "ttyPS0,$baud" if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { set_drv_prop $drv_handle "current-speed" $baud int } } } set_property CONFIG.port-number $port_number $drv_handle set uboot_prop [get_property IP_NAME [get_cells -hier $drv_handle]] if {[string match -nocase $uboot_prop "psu_uart"] || [string match -nocase $uboot_prop "psu_sbsauart"]} { set_drv_prop $drv_handle "u-boot,dm-pre-reloc" "" boolean } set has_modem [get_property CONFIG.C_HAS_MODEM [get_cells -hier $drv_handle]] if {$has_modem == 0} { hsi::utils::add_new_property $drv_handle "cts-override" boolean "" } } ================================================ FILE: usbps/data/usbps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver usbps OPTION supported_peripherals = (ps7_usb psu_usb_xhci psv_usb_xhci psx_usb_xhci); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = usbps; END driver ================================================ FILE: usbps/data/usbps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } ps7_reset_handle $drv_handle CONFIG.C_USB_RESET CONFIG.usb-reset set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]] set default_dts [set_drv_def_dts $drv_handle] if {[string match -nocase $proctype "ps7_cortexa9"] } { set_drv_prop $drv_handle phy_type ulpi string } else { set mainline_ker [get_property CONFIG.mainline_kernel [get_os]] if {[string match -nocase $proctype "psv_cortexa72"] || [string match -nocase $proctype "psx_cortexa78"]} { #TODO:Remove this once the versal dts is fully updated. return } if {[string match -nocase $mainline_ker "none"]} { set index [string index $drv_handle end] set rt_node [add_or_get_dt_node -n usb -l usb$index -d $default_dts -auto_ref_parent] hsi::utils::add_new_dts_param "${rt_node}" "status" "okay" string } } } ================================================ FILE: vid_phy_ctrl/data/vid_phy_ctrl.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver vid_phy_ctrl OPTION supported_peripherals = (vid_phy_controller); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = vid_phy_ctrl; END driver ================================================ FILE: vid_phy_ctrl/data/vid_phy_ctrl.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,vid-phy-controller-2.1"] set_drv_prop $drv_handle compatible "$compatible" stringlist set input_pixels_per_clock [get_property CONFIG.C_INPUT_PIXELS_PER_CLOCK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,input-pixels-per-clock" $input_pixels_per_clock int set nidru [get_property CONFIG.C_NIDRU [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,nidru" $nidru int set nidru_refclk_sel [get_property CONFIG.C_NIDRU_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,nidru-refclk-sel" $nidru_refclk_sel int set Rx_No_Of_Channels [get_property CONFIG.C_Rx_No_Of_Channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-no-of-channels" $Rx_No_Of_Channels int set rx_pll_selection [get_property CONFIG.C_RX_PLL_SELECTION [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-pll-selection" $rx_pll_selection int set rx_protocol [get_property CONFIG.C_Rx_Protocol [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-protocol" $rx_protocol int set rx_refclk_sel [get_property CONFIG.C_RX_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,rx-refclk-sel" $rx_refclk_sel int set tx_no_of_channels [get_property CONFIG.C_Tx_No_Of_Channels [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-no-of-channels" $tx_no_of_channels int set tx_pll_selection [get_property CONFIG.C_TX_PLL_SELECTION [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-pll-selection" $tx_pll_selection int set tx_protocol [get_property CONFIG.C_Tx_Protocol [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-protocol" $tx_protocol int set tx_refclk_sel [get_property CONFIG.C_TX_REFCLK_SEL [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-refclk-sel" $tx_refclk_sel int set hdmi_fast_switch [get_property CONFIG.C_Hdmi_Fast_Switch [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,hdmi-fast-switch" $hdmi_fast_switch int set tx_buffer_bypass [get_property CONFIG.Tx_Buffer_Bypass [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,tx-buffer-bypass" $tx_buffer_bypass int set transceiver_width [get_property CONFIG.Transceiver_Width [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-width" $transceiver_width int set use_gt_ch4_hdmi [get_property CONFIG.C_Use_GT_CH4_HDMI [get_cells -hier $drv_handle]] if {[llength $use_gt_ch4_hdmi]} { hsi::utils::add_new_dts_param "${node}" "xlnx,use-gt-ch4-hdmi" $use_gt_ch4_hdmi int } for {set ch 0} {$ch < $Rx_No_Of_Channels} {incr ch} { set rxpinname "vid_phy_rx_axi4s_ch$ch" set channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $rxpinname] if {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} { set phy_node [add_or_get_dt_node -n "${rxpinname}${channelip}" -l ${drv_handle}rxphy_lane${ch} -p $node] hsi::utils::add_new_dts_param "$phy_node" "#phy-cells" 4 int } } for {set ch 0} {$ch < $tx_no_of_channels} {incr ch} { set txpinname "vid_phy_tx_axi4s_ch$ch" set channelip [get_connected_stream_ip [get_cells -hier $drv_handle] $txpinname] if {[llength $channelip] && [llength [hsi::utils::get_ip_mem_ranges $channelip]]} { set phy_node [add_or_get_dt_node -n "${txpinname}${channelip}" -l ${drv_handle}txphy_lane${ch} -p $node] hsi::utils::add_new_dts_param "$phy_node" "#phy-cells" 4 int } } set transceiver [get_property CONFIG.Transceiver [get_cells -hier $drv_handle]] switch $transceiver { "GTXE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 1 int } "GTHE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 2 int } "GTPE2" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 3 int } "GTHE3" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 4 int } "GTHE4" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 5 int } "GTHE5" { hsi::utils::add_new_dts_param "${node}" "xlnx,transceiver-type" 6 int } } } ================================================ FILE: vproc_ss/data/vproc_ss.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver vproc_ss OPTION supported_peripherals = (v_proc_ss); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = vproc_ss; END driver ================================================ FILE: vproc_ss/data/vproc_ss.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set ip [get_property IP_NAME [get_cells -hier $drv_handle]] set topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]] if {$topology == 0} { #scaler set name [get_property NAME [get_cells -hier $drv_handle]] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,vpss-scaler-2.2 xlnx,v-vpss-scaler-2.2 xlnx,vpss-scaler"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set csc_enable_window [get_property CONFIG.C_CSC_ENABLE_WINDOW [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,csc-enable-window" $csc_enable_window string set topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,topology" $topology int set v_scaler_phases [get_property CONFIG.C_V_SCALER_PHASES [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,v-scaler-phases" $v_scaler_phases int set v_scaler_taps [get_property CONFIG.C_V_SCALER_TAPS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,v-scaler-taps" $v_scaler_taps int hsi::utils::add_new_dts_param "${node}" "xlnx,num-vert-taps" $v_scaler_taps int set h_scaler_phases [get_property CONFIG.C_H_SCALER_PHASES [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,h-scaler-phases" $h_scaler_phases int hsi::utils::add_new_dts_param "${node}" "xlnx,max-num-phases" $h_scaler_phases int set h_scaler_taps [get_property CONFIG.C_H_SCALER_TAPS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,h-scaler-taps" $h_scaler_taps int hsi::utils::add_new_dts_param "${node}" "xlnx,num-hori-taps" $h_scaler_taps int set max_cols [get_property CONFIG.C_MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-width" $max_cols int set max_rows [get_property CONFIG.C_MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-height" $max_rows int set samples_per_clk [get_property CONFIG.C_SAMPLES_PER_CLK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,samples-per-clk" $samples_per_clk int hsi::utils::add_new_dts_param "${node}" "xlnx,pix-per-clk" $samples_per_clk int set scaler_algo [get_property CONFIG.C_SCALER_ALGORITHM [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,scaler-algorithm" $scaler_algo int set enable_csc [get_property CONFIG.C_ENABLE_CSC [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,enable-csc" $enable_csc string set color_support [get_property CONFIG.C_COLORSPACE_SUPPORT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,colorspace-support" $color_support int set use_uram [get_property CONFIG.C_USE_URAM [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,use-uram" $use_uram int set max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,video-width" $max_data_width int set ports_node [add_or_get_dt_node -n "ports" -l scaler_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l scaler_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "${port1_node}" "/* For xlnx,video-format user needs to fill as per their requirement */" "" comment hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-format" 3 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-width" $max_data_width int set scaoutip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis"] if {[llength $scaoutip]} { if {[string match -nocase [get_property IP_NAME $scaoutip] "axis_broadcaster"]} { set sca_node [add_or_get_dt_node -n "endpoint" -l sca_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "sca_out$drv_handle" hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $scaoutip$drv_handle reference gen_remoteendpoint $drv_handle "$scaoutip$drv_handle" } } foreach outip $scaoutip { if {[llength $outip]} { if {[string match -nocase [get_property IP_NAME $outip] "system_ila"]} { continue } set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $outip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set sca_node [add_or_get_dt_node -n "endpoint" -l sca_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "sca_out$drv_handle" if {[string match -nocase [get_property IP_NAME $outip] "v_mix"]} { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" "mixer_crtc$outip" reference } else { hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $outip$drv_handle reference } gen_remoteendpoint $drv_handle "$outip$drv_handle" if {[string match -nocase [get_property IP_NAME $outip] "v_frmbuf_wr"] \ || [string match -nocase [get_property IP_NAME $outip] "axi_vdma"]} { gen_sca_frm_buf_node $outip $drv_handle } } else { set connectip [get_connect_ip $outip $master_intf] if {[llength $connectip]} { set sca_node [add_or_get_dt_node -n "endpoint" -l sca_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "sca_out$drv_handle" hsi::utils::add_new_dts_param "$sca_node" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"] \ || [string match -nocase [get_property IP_NAME $connectip] "axi_vdma"]} { gen_sca_frm_buf_node $connectip $drv_handle } } } } else { dtg_warning "$drv_handle pin m_axis is not connected..check your design" } } gen_gpio_reset $drv_handle $node $topology } if {$topology == 3} { #CSC set name [get_property NAME [get_cells -hier $drv_handle]] set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,vpss-csc xlnx,v-vpss-csc"] set_drv_prop $drv_handle compatible "$compatible" stringlist set ip [get_cells -hier $drv_handle] set topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,topology" $topology int set color_support [get_property CONFIG.C_COLORSPACE_SUPPORT [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,colorspace-support" $color_support int set csc_enable_window [get_property CONFIG.C_CSC_ENABLE_WINDOW [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,csc-enable-window" $csc_enable_window string set max_cols [get_property CONFIG.C_MAX_COLS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-width" $max_cols int set max_data_width [get_property CONFIG.C_MAX_DATA_WIDTH [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,video-width" $max_data_width int set max_rows [get_property CONFIG.C_MAX_ROWS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,max-height" $max_rows int set num_video_comp [get_property CONFIG.C_NUM_VIDEO_COMPONENTS [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,num-video-components" $num_video_comp int set samples_per_clk [get_property CONFIG.C_SAMPLES_PER_CLK [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,samples-per-clk" $samples_per_clk int set topology [get_property CONFIG.C_TOPOLOGY [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,topology" $topology int set use_uram [get_property CONFIG.C_USE_URAM [get_cells -hier $drv_handle]] hsi::utils::add_new_dts_param "${node}" "xlnx,use-uram" $use_uram int set ports_node [add_or_get_dt_node -n "ports" -l csc_ports$drv_handle -p $node] hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int set port1_node [add_or_get_dt_node -n "port" -l csc_port1$drv_handle -u 1 -p $ports_node] hsi::utils::add_new_dts_param "${port1_node}" "/* For xlnx,video-format user needs to fill as per their requirement */" "" comment hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-format" 3 int hsi::utils::add_new_dts_param "$port1_node" "xlnx,video-width" $max_data_width int set outip [get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis"] if {[llength $outip]} { if {[string match -nocase [get_property IP_NAME $outip] "axis_broadcaster"]} { set csc_node [add_or_get_dt_node -n "endpoint" -l csc_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "csc_out$drv_handle" hsi::utils::add_new_dts_param "$csc_node" "remote-endpoint" $outip$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } } foreach ip $outip { if {[llength $ip]} { set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $outip] -filter {TYPE==MASTER || TYPE ==INITIATOR}] set ip_mem_handles [hsi::utils::get_ip_mem_ranges $ip] if {[llength $ip_mem_handles]} { set base [string tolower [get_property BASE_VALUE $ip_mem_handles]] set cscoutnode [add_or_get_dt_node -n "endpoint" -l csc_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "csc_out$drv_handle" hsi::utils::add_new_dts_param "$cscoutnode" "remote-endpoint" $ip$drv_handle reference gen_remoteendpoint $drv_handle "$ip$drv_handle" if {[string match -nocase [get_property IP_NAME $ip] "v_frmbuf_wr"] \ || [string match -nocase [get_property IP_NAME $ip] "axi_vdma"]} { gen_csc_frm_buf_node $ip $drv_handle } } else { if {[string match -nocase [get_property IP_NAME $ip] "system_ila"]} { continue } set connectip [get_connect_ip $ip $master_intf] if {[llength $connectip]} { set cscoutnode [add_or_get_dt_node -n "endpoint" -l csc_out$drv_handle -p $port1_node] gen_endpoint $drv_handle "csc_out$drv_handle" hsi::utils::add_new_dts_param "$cscoutnode" "remote-endpoint" $connectip$drv_handle reference gen_remoteendpoint $drv_handle "$connectip$drv_handle" if {[string match -nocase [get_property IP_NAME $connectip] "v_frmbuf_wr"] \ || [string match -nocase [get_property IP_NAME $ip] "axi_vdma"]} { gen_csc_frm_buf_node $connectip $drv_handle } } } } else { dtg_warning "$drv_handle pin m_axis is not connected..check your design" } } gen_gpio_reset $drv_handle $node $topology } } proc gen_sca_frm_buf_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] gen_endpoint $drv_handle "sca_out$drv_handle" hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" sca_out$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } proc gen_csc_frm_buf_node {outip drv_handle} { set dt_overlay [get_property CONFIG.dt_overlay [get_os]] if {$dt_overlay} { set bus_node "amba" } else { set bus_node "amba_pl" } set vcap [add_or_get_dt_node -n "vcap_$drv_handle" -p $bus_node] hsi::utils::add_new_dts_param $vcap "compatible" "xlnx,video" string hsi::utils::add_new_dts_param $vcap "dmas" "$outip 0" reference hsi::utils::add_new_dts_param $vcap "dma-names" "port0" string set vcap_ports_node [add_or_get_dt_node -n "ports" -l vcap_ports$drv_handle -p $vcap] hsi::utils::add_new_dts_param "$vcap_ports_node" "#address-cells" 1 int hsi::utils::add_new_dts_param "$vcap_ports_node" "#size-cells" 0 int set vcap_port_node [add_or_get_dt_node -n "port" -l vcap_port$drv_handle -u 0 -p $vcap_ports_node] hsi::utils::add_new_dts_param "$vcap_port_node" "reg" 0 int hsi::utils::add_new_dts_param "$vcap_port_node" "direction" input string set vcap_in_node [add_or_get_dt_node -n "endpoint" -l $outip$drv_handle -p $vcap_port_node] gen_endpoint $drv_handle "csc_out$drv_handle" hsi::utils::add_new_dts_param "$vcap_in_node" "remote-endpoint" csc_out$drv_handle reference gen_remoteendpoint $drv_handle "$outip$drv_handle" } proc gen_gpio_reset {drv_handle node topology} { set proc_type [get_sw_proc_prop IP_NAME] if {$topology == 3} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "aresetn"]] } if {$topology == 0} { set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier [get_cells -hier $drv_handle]] "aresetn_ctrl"]] } foreach pin $pins { set sink_periph [::hsi::get_cells -of_objects $pin] if {[llength $sink_periph]} { set sink_ip [get_property IP_NAME $sink_periph] if {[string match -nocase $sink_ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$sink_periph 0 1" reference } if {[string match -nocase $sink_ip "xlslice"]} { set gpio [get_property CONFIG.DIN_FROM $sink_periph] set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]] foreach pin $pins { set periph [::hsi::get_cells -of_objects $pin] if {[llength $periph]} { set ip [get_property IP_NAME $periph] if {[string match -nocase $proc_type "psv_cortexa72"] } { if { $ip in { "versal_cips" "ps_wizard" }} { # As versal has only bank0 for MIOs set gpio [expr $gpio + 26] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 1" reference break } } if {[string match -nocase $proc_type "psu_cortexa53"] } { if {[string match -nocase $ip "zynq_ultra_ps_e"]} { set gpio [expr $gpio + 78] hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 1" reference break } } if {[string match -nocase $ip "axi_gpio"]} { hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 1" reference } } else { dtg_warning "peripheral is NULL for the $pin $periph" } } } } else { dtg_warning "$drv_handle:peripheral is NULL for the $pin $sink_periph" } } } ================================================ FILE: vtc/data/vtc.mdd ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver vtc OPTION supported_peripherals = (v_tc); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = vtc; END driver ================================================ FILE: vtc/data/vtc.tcl ================================================ # # (C) Copyright 2018-2022 Xilinx, Inc. # (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { foreach i [get_sw_cores device_tree] { set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl" if {[file exists $common_tcl_file]} { source $common_tcl_file break } } set node [gen_peripheral_nodes $drv_handle] if {$node == 0} { return } set compatible [get_comp_str $drv_handle] set compatible [append compatible " " "xlnx,v-tc-6.1"] set compatible [append compatible " " "xlnx,bridge-v-tc-6.1"] set_drv_prop $drv_handle compatible "$compatible" stringlist set generate_en [get_property CONFIG.C_GENERATE_EN [get_cells -hier $drv_handle]] if {$generate_en == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,generator" "" boolean } set detect_en [get_property CONFIG.C_DETECT_EN [get_cells -hier $drv_handle]] if {$detect_en == 1} { hsi::utils::add_new_dts_param "${node}" "xlnx,detector" "" boolean } } ================================================ FILE: wdtps/data/wdtps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver wdtps OPTION supported_peripherals = (ps7_wdt psu_wdt psv_wdt psx_wwdt); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = wdtps; END driver ================================================ FILE: wdtps/data/wdtps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { } ================================================ FILE: xadcps/data/xadcps.mdd ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # OPTION psf_version = 3.0; BEGIN driver xadcps OPTION supported_peripherals = (ps7_xadc); OPTION supported_os_types = (DTS); OPTION driver_state = ACTIVE; OPTION NAME = xadcps; END driver ================================================ FILE: xadcps/data/xadcps.tcl ================================================ # # (C) Copyright 2014-2022 Xilinx, Inc. # (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved. # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # proc generate {drv_handle} { }